DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of the subspecies A: terephthaldehyde as the first precursor and subspecies B: Tris(dimethylamino)phosphine, as the second precursor, in the reply filed on June 25, 2026 is acknowledged.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-2, 5-7, 11-13, 15-17, and 20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Hanawa et al. (US 20110159673 A1), hereinafter referred to as “Hanawa673”.
Regarding claim 1: Hanawa673 teaches a method of semiconductor doping (abstract), the method comprising: flowing a first precursor over a substrate (See at least Fig. 2, step 206) comprising a semiconductor surface and a dielectric surface (In light of the specification, a dielectric surface is defined as any part of the substrate made of a dielectric material, such as silicon, see Fig. 5A annotated below, Hanawa673 teaches a silicon substrate, “For example, boron, phosphorus, and arsenic atoms or ions are routinely implanted into silicon substrates”, para. [0005]) to form a first portion of a doped carbon-containing layer on the semiconductor surface and on the dielectric surface (“reacting the first precursor material to form a layer of the first precursor on the substrate”, para. [0012], Hanawa673 teaches a first precursor containing carbon, for example, the first precursor may contain the aromatic organic functional group, para. [0034]) the first precursor comprising a first reactive group (“alcohols (e.g., ROH, where R is an aliphatic, cyclic, or aromatic organic functional group)”, para. [0034]); removing a first precursor effluent comprising the first precursor from the substrate (“Any excess of the first precursor is removed from the reaction chamber by purging with a non-reactive gas.”, para. [0027]); flowing a second precursor comprising one or more of phosphorus (P), boron (B), aluminum (Al), arsenic (As), gallium (Ga), indium (In), or zinc (Zn) over the substrate (“A second precursor, which may be a dopant precursor, is provided to the process chamber containing the substrate to be doped in step 208. The second precursor may be a boron containing compound, a phosphorus containing compound, an arsenic containing compound, a metal containing compound, or a fluorine containing compound.”, para. [0035]) to react with the first reactive group to form the doped carbon-containing layer on the semiconductor surface and on the dielectric surface (“a second precursor reacts with the deposited first precursor to yield an atomic layer of the desired component deposited on the substrate.”, para. [0026], trimethylphosphide is given as an example of a second precursor in para. [0035], which contains carbon) and removing a second precursor effluent comprising the second precursor from the substrate (“After all the available sites have been consumed, reaction stops and any excess metal precursor is removed from the reaction chamber.”, para. [0029]).
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Fig. 5A taken from Hanawa673 and annotated: Substrate is made of silicon which is a dielectric material, any surface such as a trench sidewall could be considered a dielectric surface.
Regarding claim 2: Hanawa673 teaches that the first precursor has a general formula R1-(X)n wherein R1 comprises one or more of an alkyl group, an alkenyl group, an aryl, or aromatic group, and a cycloalkyl group, (X)n comprises one or more of a hydroxide group, an aldehyde group, a ketone group, an acid group, an amino group, an isocyanate group, a thiocyanate group, and an acyl chloride group, and n is an integer in a range of from 1 to 6. (An example of a first precursor given in Hanawa673 is ROH where R is an aromatic group and OH is a hydroxide group, where the integer n = 1, para. [0034])
Regarding claim 5: Hanawa673 teaches pre-cleaning the semiconductor surface and the dielectric surface. (“Portions of the surface of the substrate may optionally be pre-treated in step 404 to clean or condition the surface of the substrate, such as wet cleaning, plasma cleaning, or functional termination (i.e. hydroxyl, amino, or hydrogen termination)”, para. [0047], see at least Fig. 4, step 404).
Regarding claim 6: Hanawa673 teaches depositing at least one additional doped carbon-containing layer on the doped carbon-containing layer. (See at least Fig. 2, step 210; para. [0012], the cycle of depositing precursor layers continues until target thickness is reached.)
Regarding claim 7: Hanawa673 teaches removing the first precursor comprises: flowing a purge gas over the substrate; and removing a mixture of the first precursor effluent and the purge gas from the substrate. (“Any excess of the first precursor is removed from the reaction chamber by purging with a non-reactive gas.”, para. [0027])
Regarding claim 11: Hanawa673 teaches exposing the doped carbon-containing layer to a plasma treatment to remove the doped carbon-containing layer from the semiconductor surface and from the dielectric surface. (“In some embodiments, a dopant source layer on the surface of the substrate, and a high-concentration dopant layer just below the surface of the substrate, may be removed after annealing. A cleaning process, such as an etching, plasma cleaning, or plasma etching process, may be used to remove the unwanted species.”, para. [0057]).
Regarding claim 12: Hanawa673 teaches etching the doped carbon-containing layer at an untargeted area. (In light of the specification, the untargeted area includes the substrate and the dielectric surface, Hanawa673 teaches plasma etching to remove the doped carbon-containing layer from the substrate, and as claimed, part of the substrate is considered a dielectric surface, See Fig. 5A annotated above, para. [0057])
Regarding claim 13: A method of semiconductor doping (abstract), the method comprising: flowing a first precursor over a substrate (See at least Fig. 2, step 206) comprising a semiconductor surface and a dielectric surface (See Fig. 5A annotated above), the first precursor having a general formula R1-(X)n wherein R1 comprises one or more of alkyl group, an alkenyl group, an aryl, or aromatic group, and a cycloalkyl group, Xn comprises one or more of a hydroxide group, an aldehyde group, a ketone group, an acid group, an amino group, an isocyanate group, a thiocyanate group, and an acyl chloride group, and n is an integer in a range of from 1 to 6 (A given example of a first precursor is ROH where R is an aromatic group and OH is a hydroxide group, where the integer n = 1, para. [0034]), wherein the first precursor reacts with a reactive group on one or more of the semiconductor surface and the dielectric surface to form a first portion of a doped carbon-containing layer on one or more of the semiconductor surface and the dielectric surface (“reacting the first precursor material to form a layer of the first precursor on the substrate”, para. [0012], Hanawa673 teaches a first precursor containing carbon, for example, the first precursor may contain the aromatic organic functional group, para. [0034]); removing a first precursor effluent comprising the first precursor from the substrate (“Any excess of the first precursor is removed from the reaction chamber by purging with a non-reactive gas.”, para. [0027]); flowing a second precursor over the substrate, the second precursor comprising one or more of phosphorus (P), boron (B), aluminum (Al), arsenic (As), gallium (Ga), indium (In), and zinc (Zn) (“A second precursor, which may be a dopant precursor, is provided to the process chamber containing the substrate to be doped in step 208. The second precursor may be a boron containing compound, a phosphorus containing compound, an arsenic containing compound, a metal containing compound, or a fluorine containing compound.”, para. [0035]), wherein the second precursor reacts with the first portion to form a doped carbon-containing layer (“a second precursor reacts with the deposited first precursor to yield an atomic layer of the desired component deposited on the substrate.”, para. [0026], trimethylphosphide is given as an example of a second precursor in para. [0035], which contains carbon); and removing a second precursor effluent comprising the second precursor from the substrate. (“After all the available sites have been consumed, reaction stops and any excess metal precursor is removed from the reaction chamber.”, para. [0029]).
Regarding claim 15: Hanawa673 teaches pre-cleaning one or more of the semiconductor surface and the dielectric surface. (“Portions of the surface of the substrate may optionally be pre-treated in step 404 to clean or condition the surface of the substrate, such as wet cleaning, plasma cleaning, or functional termination (i.e. hydroxyl, amino, or hydrogen termination)”, para. [0047], see at least Fig. 4, step 404).
Regarding claim 16: Hanawa673 teaches depositing at least one additional doped carbon-containing layer on the doped carbon-containing layer. (See at least Fig. 2, step 210; para. [0012], the cycle of depositing precursor layers continues until target thickness is reached.)
Regarding claim 17: The method of claim 13, wherein removing the first precursor comprises: flowing a purge gas over the substrate; and removing a mixture of the first precursor effluent and the purge gas from the substrate. (“Any excess of the first precursor is removed from the reaction chamber by purging with a non-reactive gas.”, para. [0027]).
Regarding claim 20: The method of claim 13, further comprising exposing the doped carbon-containing layer to a plasma treatment to remove the doped carbon-containing layer from one or more of the semiconductor surface and the dielectric surface. (“In some embodiments, a dopant source layer on the surface of the substrate, and a high-concentration dopant layer just below the surface of the substrate, may be removed after annealing. A cleaning process, such as an etching, plasma cleaning, or plasma etching process, may be used to remove the unwanted species.”, para. [0057]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 8 and 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hanawa et al. (US 20110159673 A1), hereinafter referred to as “Hanawa673” in view of Jia et al. (US 20180350587 A1) hereinafter referred to as “Jia587”.
Regarding claim 8: Hanawa673 teaches the method of claim 7, wherein the purge gas is a non-reactive gas (“Any excess of the first precursor is removed from the reaction chamber by purging with a non-reactive gas”, para. [0027]). Hanawa673 does not explicitly teach that the purge gas is selected from argon (Ar), helium (He), and nitrogen (N2).
Jia587 teaches that “In some embodiments the gas may comprise noble gas, such as helium or argon. In some embodiments the gas is helium. In some embodiments the gas is argon. The flowing gas may also serve as a purge gas for the first and/or second reactant (or reactive species). (para. [0079]).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to use argon (Ar), helium (He), or nitrogen (N.sub.2), as purge gas in the method disclosed by Hanawa673 to arrive at the claimed invention. This is simply the substitution of well-known prior art elements to yield predictable results.
Regarding claim 18: Hanawa673 teaches all the limitations of claim 17.
Hanawa673 does not explicitly teach that the purge gas is selected from argon (Ar), helium (He), and nitrogen (N2).
Jia587 teaches that “In some embodiments the gas may comprise noble gas, such as helium or argon. In some embodiments the gas is helium. In some embodiments the gas is argon. The flowing gas may also serve as a purge gas for the first and/or second reactant (or reactive species). (para. [0079]).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to use argon (Ar), helium (He), or nitrogen (N.sub.2), as purge gas in the method disclosed by Hanawa673 to arrive at the claimed invention. This is simply the substitution of well-known prior art elements to yield predictable results.
Claim(s) 9-10, 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hanawa et al. US 20110159673 A1, hereinafter referred to as Hanawa673, in view of LaVoie et al. US 20120009802 A1 hereinafter referred to as LaVoie802.
Regarding claim 9: Hanawa673 teaches annealing the doped carbon-containing layer at a temperature in a range that partially overlaps with 400 °C to 1200 ° (See at least Fig. 2, step 212, “The target temperature may be from about 700.degree. C. to about 1410.degree. C”, para. [0056]). MPEP 2144.05 I states: “In the case where the claimed ranges overlap or lie inside ranges disclosed by the prior art a prima facie case of obviousness exists.” Hanawa673 does not teach an annealing temperature range of 400 °C to 700 °C.
LaVoie teaches that annealing may be performed over a range of 400 °C to 1200 ° (“An optional post deposition anneal may be employed. After the source layer is formed (or during its formation), the film may be annealed. In certain embodiments, the anneal is performed at a temperature of between about 100 and 1200.degree. C. for about 0.5 to 60 minutes, or between about 700 and 900.degree. C. for about 1 to 5 minutes.”, para. [0200], the examiner notes that the precursors disclosed in LaVoie802 are formed from substantially the same functional groups disclosed in the claimed invention). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method disclosed in Hanawa673 to choose the most appropriate annealing temperature and annealing time based on the specific precursors chosen, and the desired amount of doping. Such a modification could be done with a reasonable chance of success.
Regarding claim 10: The examiner notes that the claimed temperature range of claim 10 also partially overlaps with the range taught by Hanawa673, therefore claim 10 is rejected in the same manner as claim 9.
Regarding claim 19: Hanawa673 teaches all the limitations of claim 13, except the specific temperature range of the annealing temperature. The examiner notes that the claimed temperature range of claim 19 also partially overlaps with the range taught by Hanawa673, therefore claim 19 is rejected using the same reasoning used to reject claims 9 and 10.
Claim(s) 3,4 and 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hanawa et al. (US 20110159673 A1), hereinafter referred to as “Hanawa673”, in view of Ogihara et al. (US 20120184103 A1) hereinafter referred to as “Ogihara103”.
Regarding claims 3, 4 and 14: Hanawa673 teaches all the limitations of claim 1 and claim 13. Hanawa673 also discloses that the first precursor can be an aromatic with a hydroxide (para. [0034]) and that the second precursor could be trimethylphosphide and trimethylphosphate (para. [0035]). Hanawa673 does not explicitly list terephthaldehyde as the first precursor and Tris(dimethylamino)phosphine, as the second precursor.
Ogihara103 explicitly teaches terephthaldehyde (para. [0079]) and hexamethyl phosphoric triamide, which is another name for Tris(dimethylamino)phosphine (para. [0088]) as part of an underlayer film. Ogihara103 also discloses that these materials may be part of a diffusion process (“As mentioned above, when the resist underlayer film composition of the present invention contains any one or more of a crosslinking agent, an acid generator, and an organic solvent, not only a coating property of the resist underlayer film composition can be improved but also a crosslinking reaction in a resist underlayer film after application thereof to a substrate etc. can be facilitated by baking and so on. Accordingly, in the resist underlayer film like this, there is no fear of intermixing with a resist upper layer film, and in addition, diffusion of a molecular component to a resist upper layer film can be made small.”, para. [0031]).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to substitute the first precursor and second precursor materials disclosed in Hanawa673, with those disclosed in Ogihara103 to arrive at the claimed invention. Terephthaldehyde and Tris(dimethylamino)phosphine are well-known precursors in the art, and the substitution could be made with a reasonable expectation of success.
Citation of Pertinent Prior Art
The prior art made of record and not relied upon is considered relevant to the Applicant’s Disclosure: Lehn et al. (US 20230304147 A1) teaches tris(dimethylamino)phosphine as a doping precursor, and Bhuyan et al. (US 20230059788 A1) teaches terephthalaldehyde as a doping precursor.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ROBERT L STEWART whose telephone number is (571)-270-0853. The examiner can normally be reached M-F 8:00am-4:00pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jessica Manno can be reached at (571)-272-2339. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ROBERT L STEWART/ Examiner, Art Unit 2898
/JESSICA S MANNO/ SPE, Art Unit 2898