DETAILED ACTION
This non-final action is responsive to communications: application filed on 03/22/2024.
Claims 1-20 are pending in the application. Claims 1, 12, and 14 are independent.
Examiner Notes
A) Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification. B) MPEP 2163 guidelines teach that drawing and specification must be examined to assess whether an originally-filed claim has adequate support in the written disclosure and/or the drawings. Possession may be shown by a clear depiction of the invention in detailed drawings C) Per MPEP 2173.04 “If the claim is too broad because it reads on the prior art, a rejection under either 35 U.S.C. 102 or 103 would be appropriate”. D) Examiner cites particular paragraphs or columns and lines in the references as applied to Applicant's claims for the convenience of the Applicant. Other passages and figures may apply as well. Per MPEP 2141.02 VI prior art must be considered in its entirety. E) Per MPEP 2112 and 2112 V, express, implicit, and inherent disclosures of a prior art reference may be relied upon in the rejection of claims under 35 U.S.C. 102 or 103.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
3. Receipt is acknowledged of certified copies of papers submitted under 35 U.S.C. 119(a)-(d), which papers have been placed of record in the file.
No Information Disclosure Statement
4. No IDS has been filed as of this Office action date.
Claim Rejections - 35 USC § 112
5. The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION. — The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
6. Claims 6-9, and 19-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 6 recite “…a pre-charging phase followed by the first sensing phase…” (in line 11) and “…a pre-charging phase following the second sensing phase…” (in line 21) are redundant terms that render the claim indefinite for being ambiguous because the terms have already been recited in antecedent claim 1 (lines 17-18) and claim 2 (line 3). It is unclear if the terms are referring to previously mentioned pre-charging phases as in claims 1-2 or, are setting forth another set of precharging phases. In context of the circuit descriptions and multiple pre-charge phases described in spec, the language is vague.
Similarly, claim 19 recite “…a pre-charging phase followed by the first sensing phase…” (in line 11) and “…a pre-charging phase following the second sensing phase…” (in line 21) are redundant terms that render the claim indefinite for being ambiguous because the terms have already been recited in antecedent claims 14 and 15.
Using language (such as any of “same”, “the”, “first”, “second”...) replacing “a” to indicate whether the pre-charging phases are same or different solves the language ambiguity issue. No art rejection provided for these claims.
All dependent claims including claims 6-9 and claims 19-20 are rejected under this category.
Applicant is requested to check other claim informality, language issues (e.g., antecedent issues, redundant limitation issues, grammar issues) for all claims to expedite prosecution since informality scrutiny in this office action is not exhaustive and applicant’s co-operation is sought in this regard.
Claim Rejections - 35 USC § 102
7. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
8. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
9. Claims 1-3, and 10-16 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Shin et al. (US 2006/0028888 A1).
Regarding independent claim 1, Shin teaches a memory device (Fig. 6: 600 “semiconductor memory device”, see para [0069]. See also Fig. 1-Fig. 10 for illustrated components and functionality), including:
an array of memory cells (Fig. 6: 610, see para [0069]);
a first sensing circuit (Fig. 6: 620 BLSA) coupled to the array of memory cells (Fig. 6: 610) through a first pair of data lines (Fig. 6: BL, /BL), and configured to: amplify a received data signal from the array of memory cells (para [0070]: data output) to a first sensing signal (para [0070]: signals associated with LIO, /LIO);
a second sensing circuit (Fig. 6: 660, 630 “local sense amplifier”) coupled to the first pair of data lines (Fig. 6: BL, /BL) through a second pair of data lines (Fig. 6: LIO, /LIO), and configured to: amplify the first sensing signal (para [0071]: signals associated with LIO, /LIO) to a second sensing signal (para [0071]: signals associated with GIO, /GIO);
an isolation circuit (Fig. 6: transistor switches with CSL) located between the first pair of data lines (Fig. 6: BL, /BL) and the second pair of data lines (Fig. 6: LIO, /LIO); and
a control circuit (Fig. 6: 650 controller and memory controller combined) coupled to (operably coupled to) each of the first sensing circuit (Fig. 6: BLSA), the second sensing circuit (Fig. 6: 660, 630) and the isolation circuit (via Fig. 6: CSL and column access strobe, see para [0009]), and configured to:
in a first sensing phase (initial data sensing from cell using Fig. 6 BLSA), control the first sensing circuit (Fig. 6: 620 BLSA) to amplify the data signal to the first sensing signal, and control the isolation circuit (Fig. 6: CSL switch turned on) to connect the first pair of data lines and the second pair of data lines to transmit the first sensing signal to the second pair of data lines (Fig. 6 in context of para [0070]: “…bit line sense amplifier 620 amplifies voltages of data output from a pair of bit lines BL and /BL connected to the memory cell arrays…transmits the data to a pair of…LIO and /LIO…”. See also e.g., para [0018]); and
in a second sensing phase following the first sensing phase (during function of “local sense amplifier”, see Fig. 8 operation) and in a precharging phase following the second sensing phase (Fig. 8: during precharge of local lines), control the isolation circuit to disconnect the first pair of data lines and the second pair of data lines (Fig. 8: CSL is low during precharge of local lines e.g., when LIOEQA is high), and
in the second sensing phase, control the second sensing circuit (Fig. 8: LSAEN is high to control second sense amp) to amplify the first sensing signal (Fig. 6: signals associated with LIO, /LIO) to the second sensing signal (Fig. 6 signals associated with GIO, /GIO. See para [0071]. See also para [0074]), and
in the pre-charging phase (Fig. 8: “D2” period when LIOEQA high), control the second sensing circuit to charge the second pair of data lines to a pre-charge voltage (Fig. 8 in context of para [0086]-para [0088]: precharges LIO, /LIO to VINT).
Regarding claim 2, Shin teaches the memory device of claim 1, wherein the control circuit is further configured to: in a pre-charging phase followed by the first sensing phase (Fig. 8: precharge during first high LIOEQA signal), control the isolation circuit to disconnect the first pair of data lines and the second pair of data lines (Fig. 8: CSL is kept low), and control the first sensing circuit to charge the first pair of data lines to the pre-charge voltage (para [0086]-para [0088]: precharges LIO, /LIO to VINT).
Regarding claim 3, Shin teaches the memory device of claim 2, wherein the control circuit includes an isolation signal generating circuit (Fig. 4: control circuit that generates CSL signal) configured to:
receive a first pulse signal (Fig. 4, para [0009]: ACT_CMD and CAS active command) and a first sensing enable signal (Fig. 4: BLSAEN signal); and
output an isolation signal (Fig. 4: CSL) in accordance with the first pulse signal and the first sensing enable signal (see Fig. 4); and
the isolation circuit (Fig. 6: transistor switches with CSL) is configured to: receive the isolation signal (Fig. 6: CSL signal); and connect or disconnect the first pair of data lines and the second pair of data lines based on the isolation signal (Fig. 6: nmos transistor switch turns on or off based on CSL signal state).
Regarding claim 10, Shin teaches the memory device of claim 1, wherein the memory device further includes a column decoding circuit (Fig. 6: CSL transistor switches) coupled between the first pair of data lines and a pair of bit lines of the array of memory cells and configured to: receive a column decoding signal (Fig. 6 CSL “column selection signal”); and
control to connect or disconnect the first pair of sensing output lines and the pair of bit lines of the array of memory cells (Fig. 6: CSL transistor switches connect or disconnect BL, /BL with LIO, /LIO).
Regarding claim 11, Shin teaches the memory device of claim 1, wherein the memory device includes a Dynamic Random Access Memory (para [0011], Fig. 6 DRAM cell).
Regarding independent claim 12, Shin teaches a method for operating a memory device, wherein the memory device includes: an array of memory cells, a first sensing circuit coupled to the array of memory cells through a first pair of data lines, a second sensing circuit coupled to the first pair of data lines through a second pair of data lines, and an isolation circuit located between the first pair of data lines and the second pair of data lines; the method including: in a first sensing phase, controlling the first sensing circuit to amplify a received data signal from the array of memory cells to a first sensing signal, and controlling the isolation circuit to connect the first pair of data lines and the second pair of data lines to transmit the first sensing signal to the second pair of data lines; and in a second sensing phase following the first sensing phase and in a pre-charging phase following the second sensing phase, controlling the isolation circuit to disconnect the first pair of data lines and the second pair of data lines, and in the second sensing phase, controlling the second sensing circuit to amplify the first sensing signal to a second sensing signal, and in the pre-charging phase, controlling the second sensing circuit to charge the second pair of data lines to a pre-charge voltage (Claimed limitations are substantially same as apparatus claim 1 limitations. See claim 1 rejection analysis where Shin teaches a memory device (Fig. 6: 600 “semiconductor memory device”, see para [0069]. See also Fig. 1-Fig. 10 for illustrated components and functionality), including: an array of memory cells (Fig. 6: 610, see para [0069]); a first sensing circuit (Fig. 6: 620 BLSA) coupled to the array of memory cells (Fig. 6: 610) through a first pair of data lines (Fig. 6: BL, /BL), and configured to: amplify a received data signal from the array of memory cells (para [0070]: data output) to a first sensing signal (para [0070]: signals associated with LIO, /LIO); a second sensing circuit (Fig. 6: 660, 630 “local sense amplifier”) coupled to the first pair of data lines (Fig. 6: BL, /BL) through a second pair of data lines (Fig. 6: LIO, /LIO), and configured to: amplify the first sensing signal (para [0071]: signals associated with LIO, /LIO) to a second sensing signal (para [0071]: signals associated with GIO, /GIO); an isolation circuit (Fig. 6: transistor switches with CSL) located between the first pair of data lines (Fig. 6: BL, /BL) and the second pair of data lines (Fig. 6: LIO, /LIO); and a control circuit (Fig. 6: 650 controller and memory controller combined) coupled to each of the first sensing circuit (Fig. 6: BLSA), the second sensing circuit (Fig. 6: 660, 630) and the isolation circuit (via Fig. 6: CSL and column access strobe), and configured to: in a first sensing phase (initial data sensing from cell using Fig. 6 BLSA), control the first sensing circuit (Fig. 6: 620 BLSA) to amplify the data signal to the first sensing signal, and control the isolation circuit (Fig. 6: CSL switch turned on) to connect the first pair of data lines and the second pair of data lines to transmit the first sensing signal to the second pair of data lines (Fig. 6 in context of para [0070]: “…bit line sense amplifier 620 amplifies voltages of data output from a pair of bit lines BL and /BL connected to the memory cell arrays…transmits the data to a pair of…LIO and /LIO…”. See also e.g., para [0018]); and in a second sensing phase following the first sensing phase (during function of “local sense amplifier”, see Fig. 8 operation) and in a precharging phase following the second sensing phase (Fig. 8: during precharge of local lines), control the isolation circuit to disconnect the first pair of data lines and the second pair of data lines (Fig. 8: CSL is low during precharge of local lines e.g., when LIOEQA is high), and in the second sensing phase, control the second sensing circuit (Fig. 8: LSAEN is high to control second sense amp) to amplify the first sensing signal (Fig. 6: signals associated with LIO, /LIO) to the second sensing signal (Fig. 6 signals associated with GIO, /GIO. See para [0071]. See also para [0074]), and in the pre-charging phase (Fig. 8: “D2” period when LIOEQA high), control the second sensing circuit to charge the second pair of data lines to a pre-charge voltage (Fig. 8 in context of para [0086]-para [0088]: precharges LIO, /LIO))
Regarding claim 13, Shin teaches the method of claim 12, further includes: in a pre-charging phase followed by the first sensing phase, controlling the isolation circuit to disconnect the first pair of data lines and the second pair of data lines, and controlling the first sensing circuit to charge the first pair of data lines to the pre-charge voltage. (See claim 2 rejection analysis)
Regarding independent claim 14, Shin teaches a sensing circuit (Fig. 6: 600 sensing circuitry employed in memory device, see para [0069]. See also Fig. 1-Fig. 10 for illustrated components and functionality), including:
a first sensing circuit (Fig. 6: 620 BLSA) coupled to an initial pair of data lines (Fig. 6: BL, /BL in array column) through a first pair of data lines (Fig. 6: input-output sense bit lines SBL, /SBL of 620);
a second sensing circuit (Fig. 6: 660, 630 “local sense amplifier”) coupled to a first pair of data lines (Fig. 6: input-output sense bit lines SBL, /SBL of 620) through a second pair of data lines (Fig. 6: LIO, /LIO);
an isolation circuit (Fig. 6: transistor switches with CSL) located between the first pair of data lines (Fig. 6: input-output sense bit lines SBL, /SBL of 620) and the second pair of data lines (Fig. 6: LIO, /LIO); and
a control circuit (Fig. 6: 650 controller and memory controller combined) coupled to each of the first sensing circuit (Fig. 6: 620), the second sensing circuit (Fig. 6: 660, 630) and the isolation circuit (via Fig. 6: CSL and column access strobe), and configured to:
in a first sensing phase (initial data sensing from cell using Fig. 6 BLSA), control the first sensing circuit (Fig. 6: 620 BLSA is activated) to amplify a data signal on the initial pair of data lines (Fig. 6: data signals on BL, /BL) to a first sensing signal on the first pair of data lines (Fig. 6: output signals on sense bit lines of 620), and control the isolation circuit (Fig. 6: CSL switch turned on) to connect the first pair of data lines (Fig. 6: input-output sense bit lines SBL, /SBL of 620) and the second pair of data lines (Fig. 6: LIO, /LIO) to transmit the first sensing signal to the second pair of data lines (Fig. 6 in context of para [0070]: “…bit line sense amplifier 620 amplifies voltages of data output from a pair of bit lines BL and /BL connected to the memory cell arrays…transmits the data to a pair of…LIO and /LIO…”. See also e.g., para [0018]); and
in a second sensing phase following the first sensing phase (during function of “local sense amplifier”, see Fig. 8 operation) and in a precharging phase following the second sensing phase (Fig. 8: during precharge of local lines), control the isolation circuit to disconnect the first pair of data lines and the second pair of data lines (Fig. 8: CSL is low during precharge of local lines e.g., when LIOEQA is high), and
in the second sensing phase, control the second sensing circuit (Fig. 8: LSAEN is high to control second sense amp) to amplify the first sensing signal (Fig. 6: signals associated with LIO, /LIO) transmitted to the second pair of data lines to a second sensing signal ((Fig. 6 signals associated with GIO, /GIO. See para [0071]. See also para [0074]), and
in the pre-charging phase (Fig. 8: “D2” period when LIOEQA high), control the second sensing circuit to charge the second sensing signal on the second pair of data lines to a pre-charge voltage (Fig. 8 in context of para [0086]-para [0088]: precharges LIO, /LIO to VINT).
Regarding claim 15, Shin teaches the sensing circuit of claim 14, wherein the control circuit is further configured to: in a pre-charging phase followed by the first sensing phase, control the isolation circuit to disconnect the first pair of data lines and the second pair of data lines, and control the first sensing circuit to charge the first pair of data lines to the pre-charge voltage. (See claim 2 rejection analysis)
Regarding claim 16, Shin teaches the sensing circuit of claim 15, wherein the control circuit includes an isolation signal generating circuit configured to: receive a first pulse signal and a first sensing enable signal; and output an isolation signal in accordance with the first pulse signal and the first sensing enable signal; and the isolation circuit is configured to: receive the isolation signal; and connect or disconnect the first pair of data lines and the second pair of data lines based on the isolation signal. (See claim 3 rejection analysis)
Allowable Subject Matter
Claims 4-5, and 17-18 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding claims 4-5, the prior art of record does not appear to teach, suggest, or provide motivation for combination for “…start to output the isolation signal in a first logic state, in response to the first pulse signal being switched to a deactivated state; output the isolation signal being switched from the first logic state to a second logic state, in response to the first sensing enable signal being switched to an enabled state…”
Regarding claims 17-18, the prior art of record does not appear to teach, suggest, or provide motivation for combination for “…isolation signal generating circuit includes a pulse elimination circuit configured to: start to output the isolation signal in a first logic state, in response to the first pulse signal being switched to a deactivated state; output the isolation signal being switched from the first logic state to a second logic state, in response to the first sensing enable signal being switched to an enabled state…”
Prior Art Not Relied Upon
The prior art made of record and not relied upon (MPEP § 707.05) is considered pertinent to applicant's disclosure: HONG (US 2010/0315893 A1): Fig. 1-Fig. 6D disclosure applicable for all claims. Nakaoka (US 2011/0103123 A1): Fig. 1-Fig. 11 disclosure applicable for all claims. See also Seo (US 2010/0157702 A1) and Kawamura (US 2020/0152249 A1) which are pertinent.
Conclusion
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/MUSHFIQUE SIDDIQUE/Primary Examiner, Art Unit 2825