DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
As per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification.
In responding to this Office action, the applicant is requested to include specific references (figures, paragraphs, lines, etc.) to the drawings/specification of the present application and/or the cited prior arts that clearly support any amendments/arguments presented in the response, to facilitate consideration of the amendments/arguments.
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on February 27, 2026 has been entered.
Information Disclosure Statement
An Information Disclosure Statement has not been entered. Applicant is reminded of the duty to disclose material information under 37 CFR 1.56. If applicant wishes to have an Information Disclosure Statement made of record, please submit form PTO/SB/08, along with any statements and fees required by 37 CFR 1.97, prior to or along with the payment of the issue fee.
Response to Amendment
The amendment filed February 27, 2026 has been entered. Claims 1-20 remain pending in this application. Claims 1, 13, and 20 have been amended. No claims have been added. No new matter has been added.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-7 and 12-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 2012/0008425 A1 to Won Sun Park (hereafter Park) in view of US 2017/0140823 A1 to Chiara Missiroli, et al. (hereafter Missiroli).
Regarding Amended Independent Claim 1, Park discloses a page buffer, comprising
a plurality of latch circuits (A plurality of latch circuits LAT1-LAT3: Park, Figure 2), wherein a latch circuit of the plurality of latch circuits includes:
a latch control configuration circuit connected with a first data node and a second data node (Latch LAT3 configured with a first data node QF and a second data node QF_N: Park, Figure 2 and ¶[0037]), and
configured to, in response to a configuration signal (Setting the data levels of LAT3 in response to a configuration signal SET_A or SET_B: Park, ¶[0040]),
configure the first data node and the second data node to different and opposite logic levels, respectively (QF and QF_N being complementary data signals: Park, ¶[0037]); and
a latch transmission circuit (Latch transmission circuit 280: Park, Figure 2) connected with
the first data node (Latch transmission circuit 280 connected with first data node QF: Park, Figure 3),
the second data node (Latch transmission circuit 280 connected with second data node QF_N: Park, Figure 3), and
a sense node (Latch transmission circuit 280 connected with sense node S): Park, Figure 3), and
configured to:
transmit a second logic level of the second data node to the sense node based on a configuration result (The logic level of the QF transmitted to SO based on configuration: Park, ¶[0015]), wherein
the second logic level is transmitted to the sense node based on the configuration result (The logic level of the QF transmitted to SO based on configuration: Park, ¶[0015])
including that the second logic level of the second data node is high (When QF is high, the data level of QF may be transmitted to SO: Park, Figure 2) and the first logic level of the first data node is low (When QF_N is low, transistor 282 is open, isolating SO from Vss: Park, Figure 2)
in response to a transmission signal (In response to a transmission signal TRAN_C: Park, ¶[0043]) to transmit the second logic level of the second data node to the sense node (The logic level of the QF transmitted to SO based on configuration: Park, ¶[0015]),
couple the second data node with the sense node (Coupling the second data node QF_N with sense node SO: Park, ¶[0043]),
to transmit a configuration result of the latch control configuration circuit to the sense node (Transmitting the configuration of the latch circuit LAT3 to the sense node: Park, ¶[0043]).
Park does not explicitly disclose a latch transmission circuit wherein the latch transmission circuit transmits to a bit line control circuit to continue programming when a first logic level of the first data node is low and a second logic level of the second data node is high; and in response to the sense node reaching the second logic level of the second data node, disconnect the second data node and the sense node. Missiroli, however, discloses a latch transmission circuit wherein:
wherein the latch transmission circuit (Showing a latch transmission circuit consisting of latches M12 and TRANS: Missiroli, Figure 3)
transmits to a bit line control circuit to continue programming (Transmitting the signal of QS to node SO: Missiroli, Figure 3; Note, The signal transmitted in this instance is complementary)
when a first logic level of the first data node is low and a second logic level of the second data node is high (Showing cross-coupled latches, resulting in complementary data signals at QS and QS_N: Missiroli, Figure 3); and
in response to the sense node reaching the second logic level of the second data node,
disconnect the second data node and the sense node (Disconnecting a circuit through transistor M6 based on an increase in the voltage of a sense node SEN: Missiroli, Figure 3).
Missiroli teaches this configuration enables control of the voltage at key nodes depending on the present voltage at specific data nodes (Missiroli, ¶[0025]). In this instance, the transmission circuit illustrated in Figure 3 differs in two respects from the present invention. First, it transmits a complement to the signal rather than the direct signal. Inverting signals and making use of complementary signals is commonplace in the art and not innovative (See Missiroli, Figure 3, including nodes QS and QS_N, for example). Therefore, it would have been obvious to one having ordinary skill in the art, before the effective filing date of this application, to combine the transmission gate control logic of Missiroli with the data latches of Park, with a reasonable expectation of success.
Second, the present invention calls for connecting the signals on a low signal, only (See Specification, ¶[0107]: “In this way, considering the nature of P-type transistors that turn on under the control of a low level signal, in order to solve the problem that the level signal received at the control electrode of the transistor cannot turn on the transistor or a turn-on degree of the transistor is relatively poor.”). The use of p-type transistors to manage low or poor signals is previously shown in the art, however (Triggering PMOS transistor M6 on sensing a reduced signal: Missiroli, ¶[0090]). Therefore, it would have been obvious to one having ordinary skill in the art, before the effective filing date of this application, to combine the low or poor data signal PMOS transistor of Park in a data transmission gate as in Park and Missiroli, with a reasonable expectation of success. Both inventions are well known in the field of data transmission gates and the combination of known inventions with predictable results is obvious and not patentable.
Regarding Amended Claim 2 and the substantially similar limitations of Claim 14, Park discloses the page buffer of claim 1, wherein
the latch control configuration circuit is configured to:
in response to a set signal being in an enabled state (Circuit responding to a set signal SET_B and reset signal RESET_B: Park, ¶[0040]),
set the first data node and the second data node to the first logic level and the second logic level respectively (Setting the first and second data nodes to first and second logic levels in response to a reset signal: Park, ¶[0040]); and
initialize the first data node and the second data node to the second logic level and the first logic level respectively in response to a reset signal being in the enabled state (Setting the first and second data nodes to second and first logic levels in response to a set signal: Park, ¶[0040]), wherein the first logic level is higher than the second logic level (Where in the first logic level is higher than the second logic level: Park, Figure 2; Note, in the Park disclosure, the ‘set’ signal sets the second data node to a high level while the ‘reset’ signal sets the first data node to a high level. This difference is a difference in nomenclature and not one of functionality. Broadest Reasonable Interpretation requires an analysis of the functional limitations, regardless of specific naming conventions.); and
the latch transmission circuit is configured to
connect the second data node with the sense node when the sense node is at the second logic level (QF_N being connected to sense node SO when QF_N is at the second logic level: Park, Figure 2; Applicant defines ‘connected’ as including direct or indirect electrical connection, Specification ¶[0031]); and
in response to the transmission signal being in the enabled state and the first data node and the second data node being at the second logic level and the first logic level respectively, to cause the sense node to change from the second logic level to the first logic level (The transmission circuit managing the potential in the sense node in response to the latch circuit data state and transmission signal: Park, ¶[0042]).
Regarding Amended Claim 3 and the substantially similar limitations of Claim 15, Park discloses the page buffer of claim 2, wherein the latch transmission circuit is further configured to
maintain the sense node at the second logic level when the sense node is at the second logic level and in response to the transmission signal being in the enabled state and the first data node and the second data node being at the first logic level and the second logic level respectively (Maintaining the sense node at a consistent potential in response to the latch circuit data state and transmission signal: Park, ¶[0042]).
Regarding Amended Claim 4 and the substantially similar limitations of Claim 16, Park discloses the page buffer of claim 1, wherein the latch control configuration circuit includes:
a data transmission circuit connected with a supply voltage node (Vdd: Park, Figure 2), the first data node (QF: Park, Figure 2), and the second data node (QF_N: Park, Figure 2), and configured to
cause the first logic level of the first data node to be opposite to the second logic level of the second data node (QF and QF_N will carry complementary signals by virtue of the inverters I5 and I6: Park, Figure 2);
a set control circuit connected with the second data node and a ground voltage node (Set_C transistors 251 connected to Vss via transistor 291: Park, Figure 2), and configured to:
receive a set signal; and control the second data node to be connected with or disconnected from the ground voltage node according to a level of the set signal (QF_N selectively coupled to ground according to signal settings: Park, Figure 2); and
a reset setting control circuit connected with the first data node and the ground voltage node, and configured to:
receive a reset signal (Reset signal RESET_C: Park, Figure 2); and control the first data node to be connected with or disconnected from the ground voltage node according to a level of the reset signal (QF selectively coupled with ground according to reset signals: Park, Figure 2).
Regarding Claim 5 and the substantially similar limitations of Claim 17, Missiroli discloses the page buffer of claim 4 wherein the data transmission circuit includes:
a first transistor, wherein
a control electrode of the first transistor is connected with the first data node,
a first electrode of the first transistor is connected with the supply voltage node, and
a second electrode of the first transistor is connected with the second data node (Disclosing a first transistor T1 connected to the supply VDC_PB and second data node and controlled by the first node: Missiroli, Figure 3, annotated below); and
a second transistor, wherein
a control electrode of the second transistor is connected with the second data node,
a first electrode of the second transistor is connected with the supply voltage node, and
a second electrode of the second transistor is connected with the first data node (Disclosing a second transistor T2 connected to the supply VDC_PB and first data node and controlled by the second node: Missiroli, Figure 3, annotated below).
PNG
media_image1.png
256
246
media_image1.png
Greyscale
Missiroli Figure 3 (Annotated)
Regarding Claim 6 and the substantially similar limitations of Claim 18, Missiroli discloses a page buffer, wherein
the set control circuit includes a third transistor, wherein
a control electrode of the third transistor is configured to receive the set signal,
a first electrode of the third transistor is connected with the ground voltage node, and
a second electrode of the third transistor is connected with the second data node (Third transistor T3 connected between ground {not shown} and the second data node and controlled by the set signal: Missiroli, Figure 3, annotated above); and
the reset setting control circuit includes a fourth transistor, wherein
a control electrode of the fourth transistor is configured to receive the reset signal,
a first electrode of the fourth transistor is connected with the ground voltage node, and
a second electrode of the fourth transistor is connected with the first data node (Fourth transistor T4 connected between ground and the first data node and controlled by a reset signal: Missiroli, Figure 3, annotated above).
Regarding Claim 7 and the substantially similar limitations of Claim 19, Missiroli discloses the page buffer of Claim 1, wherein the latch transmission circuit includes
a fifth transistor (M6: Missiroli, Figure 3) and a sixth transistor (M13: Missiroli, Figure 3) connected in series (M6 and M13 connected in series: Missiroli, Figure 3),
wherein the fifth transistor and the sixth transistor are P-type transistors (M6 and M13 are shown as p-type transistors: Missiroli, Figure 3).
Regarding Amended Claim 12, Park discloses the page buffer of claim 1, further including:
the bit line control circuit connected with a supply voltage node, a bit line, and the sense node, and configured to control a potential level of the sense node based on a current level of the bit line during a sense operation (Disclosing a bit line control circuit connected to bit line BL, source voltage Vdd, and sense node SO, including transistors 221 and 211: Park, Figure 2); and
a bit line discharging circuit connected between the bit line and a ground voltage node, and configured to discharge a potential level of the bit line in response to a discharging control signal (Disclosing a bit line discharging circuit, consisting of transistor 291, connected to the bitline and ground Vss: Park, Figure 2).
Regarding Amended Independent Claim 13, Park discloses a memory device, comprising:
a memory cell array connected with a plurality of bit lines (A memory cell array including bit lines: Park, ¶[0022]); and
a plurality of page buffers (Also including page buffers: Park, ¶[0023]),
wherein a page buffer of the plurality of page buffers is connected with a bit line of the plurality of bit lines (Showing page buffers corresponding to bit lines: Park, Figure 1 and Park, ¶[0027]), and
is configured to perform a sense operation based on a current level of the bit line (Page buffers including sense circuits: Park, ¶0032]), and
the page buffer includes:
a plurality of latch circuits (Page buffer PB1 including latch circuits LAT1-LAT3: Park, Figure 2), wherein a latch circuit of the plurality of latch circuits includes:
a latch control configuration circuit connected with a first data node and a second data node (Latch LAT3 configured with a first data node QF and a second data node QF_N: Park, Figure 2 and ¶[0037]), and configured to,
in response to a configuration signal,
configure the first data node and the second data node to different and opposite logic levels respectively (Setting the data levels of LAT3 in response to a configuration signal SET_A or SET_B: Park, ¶[0040]),
(QF and QF_N being complementary data signals: Park, ¶[0037]); and
a latch transmission circuit connected with the first data node, the second data node, and a sense node (Latch transmission circuit 280 connected with first data node QF, second data node QF_N, and sense node S: Park, Figure 3), and configured to:
transmit a second logic level of the second data node to the sense node based on a configuration result (The logic level of the QF transmitted to SO based on configuration: Park, ¶[0015]), wherein
the second logic level is transmitted to the sense node based on the configuration result (The logic level of the QF transmitted to SO based on configuration: Park, ¶[0015])
including that the second logic level of the second data node is high (When QF is high, the data level of QF may be transmitted to SO: Park, Figure 2) and the first logic level of the first data node is low (When QF_N is low, transistor 282 is open, isolating SO from Vss: Park, Figure 2)
in response to a transmission signal (In response to a transmission signal TRAN_C: Park, ¶[0043]) to transmit the second logic level of the second data node to the sense node (The logic level of the QF transmitted to SO based on configuration: Park, ¶[0015]),
couple the second data node with the sense node (Coupling the second data node QF_N with sense node SO in response to transmission signal TRAN_C: Park, ¶[0043]), to transmit a configuration result of the latch control configuration circuit to the sense node (Transmitting the configuration of the latch circuit LAT3 to the sense node: Park, ¶[0043]).
Park does not explicitly disclose a latch transmission circuit wherein the latch transmission circuit transmits to a bit line control circuit to continue programming when a first logic level of the first data node is low and a second logic level of the second data node is high; and in response to the sense node reaching the second logic level of the second data node, disconnect the second data node and the sense node. Missiroli, however, discloses a latch transmission circuit wherein:
wherein the latch transmission circuit (Showing a latch transmission circuit consisting of latches M12 and TRANS: Missiroli, Figure 3)
transmits to a bit line control circuit to continue programming (Transmitting the signal of QS to node SO: Missiroli, Figure 3; Note, The signal transmitted in this instance is complementary)
when a first logic level of the first data node is low and a second logic level of the second data node is high (Showing cross-coupled latches, resulting in complementary data signals at QS and QS_N: Missiroli, Figure 3); and
in response to the sense node reaching the second logic level of the second data node,
disconnect the second data node and the sense node (Disconnecting a circuit through transistor M6 based on an increase in the voltage of a sense node SEN: Missiroli, Figure 3).
Missiroli teaches this configuration enables control of the voltage at key nodes depending on the present voltage at specific data nodes (Missiroli, ¶[0025]). In this instance, the transmission circuit illustrated in Figure 3 differs in two respects from the present invention. First, it transmits a complement to the signal rather than the direct signal. Inverting signals and making use of complementary signals is commonplace in the art and not innovative (See Missiroli, Figure 3, including nodes QS and QS_N, for example). Therefore, it would have been obvious to one having ordinary skill in the art, before the effective filing date of this application, to combine the transmission gate control logic of Missiroli with the data latches of Park, with a reasonable expectation of success.
Second, the present invention calls for connecting the signals on a low signal, only (See Specification, ¶[0107]: “In this way, considering the nature of P-type transistors that turn on under the control of a low level signal, in order to solve the problem that the level signal received at the control electrode of the transistor cannot turn on the transistor or a turn-on degree of the transistor is relatively poor.”). The use of p-type transistors to manage low or poor signals is previously shown in the art, however (Triggering PMOS transistor M6 on sensing a reduced signal: Missiroli, ¶[0090]). Therefore, it would have been obvious to one having ordinary skill in the art, before the effective filing date of this application, to combine the low or poor data signal PMOS transistor of Park in a data transmission gate as in Park and Missiroli, with a reasonable expectation of success. Both inventions are well known in the field of data transmission gates and the combination of known inventions with predictable results is obvious and not patentable.
Regarding Independent Claim 20, Park discloses a memory system, comprising:
one or more memory devices, wherein a memory device of the one or more memory devices includes:
a memory cell array connected with a plurality of bit lines (A memory cell array including bit lines: Park, ¶[0022]); and
a plurality of page buffers, wherein a page buffer of the plurality of page buffers is connected with a bit line of the plurality of bit lines (Showing page buffers corresponding to bit lines: Park, Figure 1 and Park, ¶[0027]), and is configured to perform a sense operation based on a current level of the bit line (Page buffers including sense circuits: Park, ¶0032]), and the page buffer includes:
a plurality of latch circuits (Page buffer PB1 including latch circuits LAT1-LAT3: Park, Figure 2), wherein a latch circuit of the plurality of latch circuits includes:
a latch control configuration circuit connected with a first data node and a second data node (Latch LAT3 configured with a first data node QF and a second data node QF_N: Park, Figure 2 and ¶[0037]), and configured to:
in response to a configuration signal,
configure the first data node and the second data node to different logic levels respectively (Setting the data levels of LAT3 in response to a configuration signal SET_A or SET_B: Park, ¶[0040]),
(QF and QF_N being complementary data signals: Park, ¶[0037]); and
a latch transmission circuit connected with the first data node, the second data node, and a sense node (Latch transmission circuit 280 connected with first data node QF, second data node QF_N, and sense node S: Park, Figure 3), and configured to:
transmit a second logic level of the second data node to the sense node based on a configuration result (The logic level of the QF transmitted to SO based on configuration: Park, ¶[0015]), wherein
the second logic level is transmitted to the sense node based on the configuration result (The logic level of the QF transmitted to SO based on configuration: Park, ¶[0015])
including that the second logic level of the second data node is high (When QF is high, the data level of QF may be transmitted to SO: Park, Figure 2) and the first logic level of the first data node is low (When QF_N is low, transistor 282 is open, isolating SO from Vss: Park, Figure 2)
in response to a transmission signal (In response to a transmission signal TRAN_C: Park, ¶[0043]) to transmit the second logic level of the second data node to the sense node (The logic level of the QF transmitted to SO based on configuration: Park, ¶[0015]),
couple the second data node with the sense node (Coupling the second data node QF_N with sense node SO in response to transmission signal TRAN_C: Park, ¶[0043]),
to transmit a configuration result of the latch control configuration circuit to the sense node (Transmitting the configuration of the latch circuit LAT3 to the sense node: Park, ¶[0043]); and
a memory controller connected with the one or more memory devices and configured to control the one or more memory devices (Showing a control circuit: Park, Figure 1).
Park does not explicitly disclose a latch transmission circuit wherein the latch transmission circuit transmits to a bit line control circuit to continue programming when a first logic level of the first data node is low and a second logic level of the second data node is high; and in response to the sense node reaching the second logic level of the second data node, disconnect the second data node and the sense node. Missiroli, however, discloses a latch transmission circuit wherein:
wherein the latch transmission circuit (Showing a latch transmission circuit consisting of latches M12 and TRANS: Missiroli, Figure 3)
transmits to a bit line control circuit to continue programming (Transmitting the signal of QS to node SO: Missiroli, Figure 3; Note, The signal transmitted in this instance is complementary)
when a first logic level of the first data node is low and a second logic level of the second data node is high (Showing cross-coupled latches, resulting in complementary data signals at QS and QS_N: Missiroli, Figure 3); and
in response to the sense node reaching the second logic level of the second data node,
disconnect the second data node and the sense node (Disconnecting a circuit through transistor M6 based on an increase in the voltage of a sense node SEN: Missiroli, Figure 3).
Missiroli teaches this configuration enables control of the voltage at key nodes depending on the present voltage at specific data nodes (Missiroli, ¶[0025]). In this instance, the transmission circuit illustrated in Figure 3 differs in two respects from the present invention. First, it transmits a complement to the signal rather than the direct signal. Inverting signals and making use of complementary signals is commonplace in the art and not innovative (See Missiroli, Figure 3, including nodes QS and QS_N, for example). Therefore, it would have been obvious to one having ordinary skill in the art, before the effective filing date of this application, to combine the transmission gate control logic of Missiroli with the data latches of Park, with a reasonable expectation of success.
Second, the present invention calls for connecting the signals on a low signal, only (See Specification, ¶[0107]: “In this way, considering the nature of P-type transistors that turn on under the control of a low level signal, in order to solve the problem that the level signal received at the control electrode of the transistor cannot turn on the transistor or a turn-on degree of the transistor is relatively poor.”). The use of p-type transistors to manage low or poor signals is previously shown in the art, however (Triggering PMOS transistor M6 on sensing a reduced signal: Missiroli, ¶[0090]). Therefore, it would have been obvious to one having ordinary skill in the art, before the effective filing date of this application, to combine the low or poor data signal PMOS transistor of Park in a data transmission gate as in Park and Missiroli, with a reasonable expectation of success. Both inventions are well known in the field of data transmission gates and the combination of known inventions with predictable results is obvious and not patentable.
Claim(s) 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 2012/0008425 A1 to Won Sun Park (hereafter Park) and US 2017/0140823 A1 to Chiara Missiroli, et al. (hereafter Missiroli) in view of US 4,584,672 to Joseph D. Schutz, et al. (hereafter Schutz).
Regarding Amended Claim 8, Park discloses the page buffer of claim 7, wherein
a control electrode of the fifth transistor is connected with the first data node,
a first electrode of the fifth transistor is connected with a second electrode of the sixth transistor, and
a second electrode of the fifth transistor is connected with the second data node; and
a control electrode of the sixth transistor is configured to receive the transmission signal, and a first electrode of the sixth transistor is connected with the sense node (Disclosing transistor 283 between data node QF and the sense node SO: Park, Figure 2).
Park does not expressly disclose the further limitations of Claim 8. Shutz, however, teaches a page buffer as in Claim 7, wherein: a control electrode of the fifth transistor is connected with the first data node, a second electrode of the fifth transistor is connected with the second data node, and a first electrode of the fifth transistor is connected with a second electrode of the sixth transistor (Disclosing data signals BLI at 23 and its complement at 24, wherein the first controls the gate of a transistor 50 and the other is connected to a first side of the transistor, the other side of the transistor leading to a sensing node SAS: Schutz, Figure 4).
Schutz teaches this circuit configuration helps separate a shift between signals, ensuring a full differential between signals is reached (Schutz, col.7:1-20). Therefore, it would have been obvious to one having ordinary skill in the art, before the effective filing date of this application, to combine the waveform management configuration of Schutz with the complementary signal circuit of Park, with a reasonable expectation of success. Both inventions are well known in the field of signal management and the combination of known inventions with predictable results is obvious and not patentable.
Claim(s) 9-11 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 2012/0008425 A1 to Won Sun Park (hereafter Park) and US 2017/0140823 A1 to Chiara Missiroli, et al. (hereafter Missiroli) in view of EP 0841754 A2 to Paul E. Landman, et al. (hereafter Landman).
Regarding Amended Claim 9, Park discloses the page buffer of claim 1, but does not disclose the further limitations of Claim 9. Landman, however, discloses a circuit including a voltage regulator wherein:
a voltage regulator circuit connected with the first data node and the second data node, and configured to stabilize a voltage difference between the first data node and the second data node (Disclosing using a voltage regulator between nodes to stabilize the voltage between nodes: Landman, Page 6:15-19).
Landman teaches the inclusion of a voltage regulator circuit allows for a low-power voltage management circuit without loss of accuracy (Landman, Page 15:11-19). Therefore, it would have been obvious to one having ordinary skill in the art, before the effective filing date of this application, to combine the low power voltage regulator of Landman with the complementary signals of Park, with a reasonable expectation of success. Both inventions are well known in the field of data circuit latching and the combination of known inventions with predictable results is obvious and not patentable.
Regarding Amended Claim 10, Landman discloses the page buffer of claim 9, wherein the voltage regulator circuit includes
a capacitor, wherein a first plate of the capacitor is connected with the first data node, and a second plate of the capacitor is connected with the second data node (Disclosing using capacitors as a voltage regulator between nodes of a circuit: Landman, Page 6:15-19).
Regarding Amended Claim 11, Landman discloses the page buffer of claim 9, wherein the voltage regulator circuit includes:
a seventh transistor, wherein a control electrode of the seventh transistor is connected with the second data node, and a first electrode and second electrode of the seventh transistor both are connected with the first data node (Disclosing mimicking a capacitor by using a transistor with the control gate as one plate and the source and drain shorted together as the opposing plate: Landman, Page 6:24-27).
Response to Arguments
Applicant's arguments filed February 27, 2026 have been fully considered but they are not persuasive. Applicant’s primary argument is that the prior art fails to teach the recently added limitations, namely that the latch transmission circuit is configured to transmit a second logic level of the second data node to the sense node based on a configuration result, wherein the second logic level is transmitted to the sense node based on the configuration result including that the second logic level of the second data node is high and a first logic level of the first data node is low (Applicant Argument/Response: page 10, ¶4).
These limitations are addressed in the above rejection discussion, but for clarity of the record a few additional notes should be addressed. First, it should be noted the nodes in Park identified as QF and QF_N have been mapped to the opposite node in the present invention, that is Node 1 was previously identified with QF and Node 2 with QF_N and both are now mapped the other way around. This change has been made to better match the new limitations but does not affect the validity of prior discussion. Prior to the current amendment, labelling of these nodes was arbitrary and could reasonably have been considered fungible.
Secondly, Applicant emphasizes in the amended language that the data level of the second node is only transmitted to the sense node based on a configuration result, including the second node being high and the first node being low. The term ‘configuration result’ is open ended and may include any number of other signals or settings, such as the PROG signal and TRAN_C signal indicated in Park, Figure 2. The relative data level of the first and second nodes needs only be a single factor and, as such, is clearly demonstrated in Park.
Therefore, Applicant’s arguments are unpersuasive. Applicant's response is considered to be a bona fide attempt at a response and is being accepted as a complete response.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US 9,021,001 B2 to Dai Yamamoto, et al.: Teaching a set of cross connected latches optimized for efficiency.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHRISTOPHER LANE REECE whose telephone number is (571)272-0288. The examiner can normally be reached Monday - Friday 7:30am-5pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Richard Elms can be reached at (571) 272-1869. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/CHRISTOPHER LANE REECE/Examiner, Art Unit 2824
/UYEN SMET/Primary Examiner, Art Unit 2824
Prosecution Insights