Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the “a degeneration inductor” claimed in claim 20 must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 18 and 25-27 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 18, the claim as written is unclear. It is not clear which “gate node of a transistor” is intended. Is it “gate node of a transistor” in the second stack? Clarification is needed.
Regarding claim 25, 1st limitation as written is unclear. What does applicant mean by “providing a reference circuit of the stacked transistor amplifier”? Note, according to the specification and 2nd limitation of the claim, “reference circuit” is a separate circuit that is mirrored/scaled down version of stacked amplifier, see para. [0016]. Clarification is needed.
Regarding claims 26 and 27, also rejected due to their dependency on rejected independent claim 25.
Allowable Subject Matter
Claims 2-17 and 19-24 are allowed.
Claim 18 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims.
Claims 25-27 would be allowable if rewritten or amended to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action.
The following is an examiner’s statement of reasons for allowance:
Regarding claims 2-17 and 19-24, among other subject matters claimed, prior art(s) does not disclose a biasing circuit configured to increase or decrease a level of a biasing voltage to at least one gate node of a transistor of the first stack and a gate node of a respective transistor of the second stack, wherein the biasing circuit comprises a current boost circuit that comprises: a first current source selectively coupled to the at least one gate node to provide a positive boost current when the level of said biasing voltage is increased, and a second current source selectively coupled to the at least one gate node to provide a negative boost current when the level of said biasing voltage is decreased.
Regarding claims 25-27, prior art(s) does not disclose increasing a level of a biasing voltage to a gate node of a transistor of the stacked transistor amplifier by charging said gate node with a positive boost current; and decreasing the level of said biasing voltage by discharging said gate node with a negative boost current.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. The additional reference(s) cited in PTO-892 show further analogous prior art circuitry.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Khanh V. Nguyen whose telephone number is (571) 272-1767. The examiner can normally be reached from 8:30 AM – 5:00 PM EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, LINDGREN BALTZELL ANDREA can be reached on (571) 272-5918. The fax phone numbers for the organization where this application or proceeding is assigned is 571-273-8300.
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/KHANH V NGUYEN/ Primary Examiner, Art Unit 2843