DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-3, 6, 8-14, 16, 18-20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Hu et al US 2023/0335468.
Pertaining to claims 1, 11 and 12, Hu teaches a three-dimensional (3D) stacked chip/method, comprising:
a first die T1 having a front-side surface and a backside surface, opposite the front-side surface, the backside surface on a front-side surface of a first redistribution layer (RDL) 250 see Figure 5C and [0052];
a second die T2 having a front-side surface on the front-side surface of the first die and a backside surface being distal from the first RDL; and
a via 230 extending from the backside surface of the second die to a back-end-of-line (BEOL) layer of the second die. See Figure 3D marked up below
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Pertaining to claims 2 and 13, Hu teaches the 3D stacked chip of claims 1 and 12, further comprising a second RDL 250 see Figure 3D marked up above having a front-side surface on the backside surface of the second die, the second RDL being distal from the first RDL, in which the via 230 is directly coupled to the second RDL see Figure 3D marked up above.
Pertaining to claims 3 and 14, Hu teaches the 3D stacked chip of claims 1 and 12, in which the second die comprises a substrate 210 having an active layer (layer in which devices 212 are placed) coupled to the BEOL layer of the second die and distal from the backside surface of the second die, in which the via 230 extends through the substrate 210 and the active layer to the BEOL layer of the second die see Figure 3D.
Pertaining to claims 6 and 16, Hu teaches the 3D stacked chip of claims 3 and 14, further comprising a second RDL 250 see Figure 3D marked up above on the backside surface of the second die T2, in which the via 230 is a power via [0036] that extends from the second RDL through the substrate 210 and the active layer (layer in which devices 212 are placed) to the BEOL layer of the second die. See Figure 3D marked up above.
Pertaining to claims 8 and 18, Hu teaches the 3D stacked chip of claims 1 and 11, further comprising a printed circuit board coupled to the first die through package bumps. 44 = Figure 3C, see also Figures 7. 42 is a circuit board [0058]
Pertaining to claims 9 and 19, Hu teaches the 3D stacked chip of claims 1 and 11, in which the front-side surface of the first die is directly bonded to the front-side surface of the second die to couple the BEOL layer of the second die to a BEOL layer of the first die. Direct bonding is illustrated in Figure 3D as marked up above and denoted by ‘IF’ [0037]
Pertaining to claims 10 and 20, Hu teaches the 3D stacked chip of claims 1 and 11, further comprising a package substrate 42 coupled to a backside surface of a second RDL on the backside surface of the second die 44 = Figure 3C. 42 can also be a package substrate [0058] Figure 7
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 4, 5, 7, 15 and 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hu as applied to claims 3 and 14 above, and further in view of Katkar et al US 2016/0284672 and further in view of Matayabas Jr et al US 2005/0041406.
Pertaining to claims 4, 5, 7, 15 and 17, Hu teaches the device/method of claims 1, 3, 11 and 14, but is silent regarding a thermal plate, lead, thermal interface material and a thermal via.
Matayabas teaches a device/method further comprising:
forming a thermal plate 105 on the backside surface of the die,
forming a thermal lead 106 coupled to the thermal plate.
thermal interface material 104 on the backside surface of the die 103 See Figure 3
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to incorporate the teachings of Matayabs into the method of Hu by adding the thermal layers as claimed above. The ordinary artisan would have been motivated to modify Hu in the manner set forth above for at least the purpose of extracting heat from the chip in order to prevent device failure.
Matayabas fails to teach a thermal via.
Katkar teaches a thermal via 118 that extends from the thermal interface material/plate 42/43 and through the substrate IC Die 10-1.
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to incorporate the teachings of Katkar into the method of Hu in view of Matayabas by adding thermal vias through the chip/substrate. The ordinary artisan would have been motivated to modify Hu/Matayabas in the manner set forth above for at least the purpose of improving heat dissipation through the device, the via acting as a means of extracting heat from the opposing side and interior structures.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NICHOLAS J TOBERGTE whose telephone number is (571)272-6458. The examiner can normally be reached M-F 7:30-4:30.
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/NICHOLAS J TOBERGTE/Primary Examiner, Art Unit 2817
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