DETAILED ACTION
Notice of Pre-AIA or AIA Status
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
2. Applicants’ arguments presented in the Response dated August 30, 2018, are persuasive, therefore, the rejections of the previous Office action are withdrawn, and prosecution on the merits reopened in view of the newly applied prior art and other issues detailed below.
Claim Rejections - 35 USC § 102
3. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or other-wise available to the public before the effective filing date of the claimed invention.
4. Claim(s) 1-8 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Haba et al., US US 2009/0160065 A1.
Claim 1. Haba et al., discloses a method for aligning semiconductor dies in a die stack (such as the steps from figs. 2 to 7B), comprising:
-providing a first die (item 112, fig. 4) with a first channel (item 114, fig. 4, [0035]) that extends between a top side and a bottom side of the first die;
-repositioning the first die relative to a substrate (item 160, fig. 4) to expose an alignment structure (item 24, fig. 4) of the substrate through the first channel;
-and mounting the first die to the substrate (as seen in the structure of fig. 4).
Claim 2. Haba et al., discloses the method of claim 1, wherein the first channel is positioned along a first edge of the first die (this limitation would read through [0035] wherein is disclosed as a result of this step, portions of the traces 24 at the front face of each microelectronic element become exposed within the channels).
Claim 3. Haba et al., discloses the method of claim 1, wherein the first channel is positioned interior with respect to edges of the first die (as seen in the structure of fig. 4).
Claim 4. Haba et al., discloses the method of claim 1, wherein the alignment structure of the substrate is an optically visible mark on a top side of the substrate (this limitation would read through [0035] wherein is disclosed as a result of this step, portions of the traces 24 at the front face of each microelectronic element become exposed within the channels).
Claim 5. Haba et al., discloses the method of claim 1, wherein the alignment structure of the substrate is a second channel extending between a top side and a bottom side of the substrate (this limitation would read through [0035] wherein is disclosed as a result of this step, portions of the traces 24 at the front face of each microelectronic element become exposed within the channels).
Claim 6. Haba et al., discloses the method of claim 5, wherein after mounting the first die to the substrate, the first channel and the second channel are vertically aligned such that they expose a second alignment feature of a lower structure (this limitation would read through fig. 7A, [0037] wherein is disclosed for example, an etchant is supplied to channels 114A which run between individual ones of the microelectronic elements 112A of the second reconstituted wafer layer in order to remove material from the edges of microelectronic elements 112A so as to expose portions of the traces 24 within the channels at the front face of each microelectronic element).
Claim 7. Haba et al., discloses the method of claim 6, wherein the substrate comprises a second die and the lower structure comprises an additional substrate (this limitation would read through the structure of fig. 7A, [0046] wherein is disclosed for example, microelectronic element 230 may include one or more additional microelectronic elements).
Claim 8. Haba et al., discloses the method of claim 1, wherein the repositioning the first die relative to the substrate further comprises exposing a second alignment structure of the substrate with a second channel of the first die that extends between the top side and the bottom side of the first die, the first and second channels being laterally spaced from each other, and wherein the second alignment structure is an optically visible mark on the top side of the substrate (this limitation would read through the structure of fig. 7A, [0037] wherein is disclosed for example, an etchant is supplied to channels 114A which run between individual ones of the microelectronic elements 112A of the second reconstituted wafer layer in order to remove material from the edges of microelectronic elements 112A so as to expose portions of the traces 24 within the channels at the front face of each microelectronic element).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to WILNER JEAN BAPTISTE whose telephone number is (571)270-7394. The examiner can normally be reached M-T 8:00-6:00.
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/W.J/Examiner, Art Unit 2899 /DALE E PAGE/Supervisory Patent Examiner, Art Unit 2899