Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Claims 1-20 are pending.
Examiner Notes
Examiner cites particular paragraphs and/or columns and lines in the references as applied to Applicant’s claims for the convenience of the Applicant. Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested that, in preparing responses, the Applicant fully consider the references in entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the examiner. The prompt development of a clear issue requires that the replies of the Applicant meet the objections to and rejections of the claims. Applicant should also specifically point out the support for any amendments made to the disclosure. See MPEP § 2163.06.
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Authorization for Internet Communications in a Patent Application
Applicant is encouraged to file an Authorization for Internet Communications in a Patent Application form (http://www.uspto.gov/sites/default/files/documents/sb0439.pdf) along with the response to this office action to facilitate and expedite future communication between Applicant and the examiner. If the form is submitted then Applicant is requested to provide a contact email address in the signature block at the conclusion of the official reply.
Allowable Subject Matter
Claims 1-20 would be allowable over the prior art of record if rewritten to overcome the applicable rejection(s) and/or objection(s) set forth in this Office action because the examiner found neither prior art cited in its entirety, nor based on the prior art, found any motivation to combine any of the said prior art.
The primary reason for allowance for the independent claims 1, 10, and 12 is determining, by the DTE, responsive to the transfer stimulus and based on at least one of the source device and the destination device, a set of transfer methods to transfer a first portion of the stage data from a source memory to a destination memory, the source memory communicatively coupled to the source device, the destination memory communicatively coupled to the destination device;
selecting, by the DTE, from among the set of transfer methods, a first transfer method to transfer the first portion of the stage data; determining, by the DTE, based on the first transfer method, a first set of transfer channels to transfer the first portion of the stage data from the source memory to the destination memory; selecting, by the DTE, from among the first set of transfer channels, a first channel to transfer the first portion of the stage data from the source memory to the destination memory; acquiring, by the DTE, from a resource manager of the computing system, first resources to transfer, using the first channel, the first portion of the stage data from the source memory to the destination memory, the first resources comprising hardware of the computing system required by the first channel to transfer the first portion of the stage data from the source memory to the destination memory; and, initiating, by the DTE, using the first transfer method and the first channel, transfer of the first portion of the stage data from the source memory to the destination memory.in conjunction with the rest of the limitations set forth in the claim.
The remaining claims, not specifically mentioned, are allowed because they are dependent upon one of the independent claims mentioned above.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 1-20 are rejected under 35 U.S.C. 101 because the claimed invention is directed to a judicial exception (an abstract idea) without significantly more.
Step 1: The claim is a process, machine, manufacture, or composition of matter:
Claim 1. A computer-implemented method, the method comprising.
Step 2A Prong One: The claim recites an abstract idea because it includes limitations that can be considered mental processes (concepts performed in the human mind including an observation, evaluation, judgment, and/or opinion). If a claim limitation, under its broadest reasonable interpretation, covers performance of the limitation in the human mind or via pen and paper, then it falls within the “Mental Processes” grouping of abstract ideas. Accordingly, the claim recites an abstract idea:
determining, by the DTE, responsive to the transfer stimulus and based on at least one of the source device and the destination device, a set of transfer methods to transfer a first portion of the stage data from a source memory to a destination memory (abstract idea mental process),
selecting, by the DTE, from among the set of transfer methods, a first transfer method to transfer the first portion of the stage data (abstract idea mental process);
determining, by the DTE, based on the first transfer method, a first set of transfer channels to transfer the first portion of the stage data from the source memory to the destination memory (abstract idea mental process);
selecting, by the DTE, from among the first set of transfer channels, a first channel to transfer the first portion of the stage data from the source memory to the destination memory (abstract idea mental process).
Step 2A Prong Two: The abstract idea is not integrated into a practical application because the abstract idea is recited but for generically recited additional computer elements (i.e. data storage, processor, memory, computer readable medium, etc.) which do not add meaningful limitations to the abstract idea amounting to simply implementing the abstract idea on a generic computer using generic computing hardware and/or software (e.g. generally linking the use of the judicial exception to a particular technological environment or field of use (see MPEP 2106.05(h)). Mere instructions to apply an exception using a generic computer component cannot provide an inventive concept. The generic computing components are recited at a high-level of generality such that they amount to no more than mere instructions to apply the exception using the recited generic computer components. Accordingly, these additional elements do not integrate the abstract idea into a practical application because they do not impose any meaningful limits on practicing the abstract idea:
the source memory communicatively coupled to the source device, the destination memory communicatively coupled to the destination device (generic computing components);
receiving, by a Dynamic Transfer Engine (DTE), a transfer stimulus associated with a dynamic state of execution of a dataflow application by hardware devices of a computing system, the DTE comprising a processing component of the computing system, the dynamic state of execution requiring transfer of stage data from a source device to a destination device (generic computing components performing extra-solution activity of receiving data/information), the source device and the destination device among the hardware devices of the computing system (generic computing components);
acquiring, by the DTE, from a resource manager of the computing system, first resources to transfer, using the first channel, the first portion of the stage data from the source memory to the destination memory, the first resources comprising hardware of the computing system required by the first channel to transfer the first portion of the stage data from the source memory to the destination memory (generic computing components performing extra-solution activity of receiving data/information); and,
initiating, by the DTE, using the first transfer method and the first channel, transfer of the first portion of the stage data from the source memory to the destination memory (generic computing components performing extra-solution activity of sending/transmitting data/information).
Step 2B: The claim includes limitations which can be considered extra-solution activity (see MPEP 2106.05(g)) insufficient to amount to significantly more than the abstract idea because the additional limitations only perform at least one of collecting, gathering, displaying, generating, modifying, updating, storing, retrieving, sending, and receiving data/information data which are well-understood, routine, conventional computer functions as recognized by the court decisions listed in MPEP § 2106.05(d)II. The claim further includes limitations that do not integrate the judicial exception into a practical application because they merely recite the words "apply it" (or an equivalent) with the judicial exception, or merely including instructions to implement an abstract idea on a computer, or merely using a computer as a tool to perform an abstract idea, as discussed in MPEP § 2106.05(f). Therefore, the claim, and its limitations when considered separately and in combination, is directed to patent ineligible subject matter:
receiving, by a Dynamic Transfer Engine (DTE), a transfer stimulus associated with a dynamic state of execution of a dataflow application by hardware devices of a computing system, the DTE comprising a processing component of the computing system, the dynamic state of execution requiring transfer of stage data from a source device to a destination device (extra-solution activity of receiving data/information);
acquiring, by the DTE, from a resource manager of the computing system, first resources to transfer, using the first channel, the first portion of the stage data from the source memory to the destination memory, the first resources comprising hardware of the computing system required by the first channel to transfer the first portion of the stage data from the source memory to the destination memory (extra-solution activity of receiving data/information); and,
initiating, by the DTE, using the first transfer method and the first channel, transfer of the first portion of the stage data from the source memory to the destination memory (extra-solution activity of sending/transmitting data/information).
Claim 2. The method of claim 1, the method further comprising:
selecting, by the DTE, a second channel, among the first set of transfer channels, to transfer a second portion of the stage data from the source memory to the destination memory (abstract idea mental process); and,
initiating, by the DTE, using the first transfer method and the second channel, transfer of the second portion of the stage data, from the source memory to the destination memory (extra-solution activity of sending/transmitting data/information).
Claim 3. The method of claim 1, the method further comprising:
determining, by the DTE, a transfer status associated with the transfer of the first portion of stage data using the first channel (abstract idea mental process); and,
communicating, by the DTE, to the resource manager, the transfer status (extra-solution activity of sending/transmitting data/information).
Claim 4. The method of claim 1, the method further comprising:
selecting, by the DTE, responsive to the transfer stimulus, a second transfer method, from among the set of transfer methods, to transfer a second portion of the stage data from the source memory to the destination memory (abstract idea mental process);
determining, by the DTE, based on the second transfer method, a second set of transfer channels to transfer the second portion of the stage data from the source memory to the destination memory (abstract idea mental process);
selecting, by the DTE, from among the second set of transfer channels, a second channel to transfer the second portion of the stage data from the source memory to the destination memory (abstract idea mental process);
acquiring, by the DTE, from the resource manager, second resources to transfer, using the second channel, the second portion of the stage data from the source memory to the destination memory (extra-solution activity of receiving data/information), the second resources comprising hardware of the computing system required by the second channel to transfer the second portion of the stage data from the source memory to the destination memory (generic computing components); and,
initiating, by the DTE, using the second transfer method and the second channel, transfer of the second portion of the stage data from the source memory to the destination memory (extra-solution activity of sending/transmitting data/information).
Claim 5. The method of claim 4, the method further comprising:
determining, by the DTE, a first transfer status, the first transfer status associated with the transfer of the first portion of stage data using the first channel (abstract idea mental process);
determining, by the DTE, a second transfer status, the second transfer status associated with the transfer of the second portion of stage data using the second channel (abstract idea mental process);
determining, by the DTE, based on the first transfer status and the second transfer status a completion status associated with the transfer of the stage data from the source memory to the destination memory (abstract idea mental process); and,
communicating, by the DTE, to the resource manager, the completion status (extra-solution activity of sending/transmitting data/information).
Claim 6. The method of claim 1, wherein the method further comprises:
determining, by the DTE, based on a hardware selection criteria, at least one of the source memory and the destination memory, the hardware selection criteria associated with at least one of the source device and the destination device (abstract idea mental process).
Claim 7. The method of claim 1, wherein the first transfer method is selected from the group consisting of: direct memory access method; remote direct memory access method; memory-mapped input/output method; and, a processor direct method (abstract idea mental process).
Claim 8. The method of claim 1, wherein the method of the DTE determining the first set of transfer channels comprises the DTE determining the first set of transfer channels based further on a criterion selected from the group consisting of:
a number of direct memory access engines associated with a first channel among the first set of transfer channels;
a number of address translation windows associated with a second channel among the first set of transfer channels;
a location, within a hardware topology of the computing system, of at least one of the source memory and the destination memory;
a location, within the hardware topology, of a hardware transfer unit of a third channel among the first set of transfer channels; and,
a proximity, within the hardware topology, of a hardware transfer unit of a fourth channel, among the first set of transfer channels, to at least one of the source memory and the destination memory (abstract idea mental process).
Claim 9. The method of claim 1, wherein at least of the source device and the destination device is selected from the group consisting of a central processing unit; a coarse-graph reconfigurable processor; a graphics processing unit; a field programmable gate array; a high performance memory; and, a storage device (generic computing components).
As per claim 10, it has similar limitations as claim 1 and is therefore rejected using the same rationale.
Claim 11. The computer program product of claim 10, the first program instructions executable by at least one processor to further cause the at least one processor to:
determine, responsive to the transfer stimulus and based on at least one of the source device and the destination device, a second transfer method to transfer a second portion of the stage data from the source memory to the destination memory (abstract idea mental process);
determine, based on the second transfer method, a second set of transfer channels to transfer the second portion of the stage data from the source memory to the destination memory (abstract idea mental process);
select, from among the second set of transfer channels, a second channel to transfer the second portion of the stage data from the source memory to the destination memory (abstract idea mental process);
acquire, from the resource manager, second resources to transfer, using the second channel, the second portion of the stage data from the source memory to the destination memory, the second resources comprising hardware of the computing system required by the second channel to transfer the second portion of the stage data from the source memory to the destination memory (extra-solution activity of receiving data/information); and,
initiate, using the second transfer method and the second channel, transfer of the second portion of the stage data from the source memory to the destination memory (extra-solution activity of sending/transmitting data/information).
As per claim 12, it has similar limitations as claim 1 and is therefore rejected using the same rationale.
As per claim 13, it has similar limitations as claim 2 and is therefore rejected using the same rationale.
As per claim 14, it has similar limitations as claim 3 and is therefore rejected using the same rationale.
As per claim 15, it has similar limitations as claim 4 and is therefore rejected using the same rationale.
As per claim 16, it has similar limitations as claim 5 and is therefore rejected using the same rationale.
As per claim 17, it has similar limitations as claim 7 and is therefore rejected using the same rationale.
As per claim 18, it has similar limitations as claim 8 and is therefore rejected using the same rationale.
Claim 19. The computing system of claim 12, wherein the DTE configured to determine at least one of the first transfer method and the first set of transfer channels comprises the DTE further configured to determine the at least one of the first transfer method and the first set of transfer channels based on a dynamic availability, during runtime of the dataflow application, of hardware resources among the hardware of the computing system (abstract idea mental process).
As per claim 20, it has similar limitations as claim 9 and is therefore rejected using the same rationale.
Citation of Relevant Prior Art
The prior art made of record and not relied upon is considered pertinent to Applicant's disclosure:
Greenhalgh (US 2011/0213993) in at least the abstract disclose in response to a transfer stimulus, performance of a processing workload is transferred from a source processing circuitry to a destination processing circuitry, in preparation for the source processing circuitry to be placed in a power saving condition following the transfer.
Greenhalgh et al. (US 2011/0213934) in at least the abstract disclose a switch controller is responsive to a transfer stimulus to perform a handover operation to transfer performance of the workload from source processing circuitry to destination processing circuitry, with the source processing circuitry being one of the first and second processing circuitry and the destination processing circuitry being the other of the first and second processing circuitry.
Park et al. (US 2020/0364176) in at least claim 17 disclose a selection of one of a first communication path for communicating the data from the device to the data transfer device and a second communication path for communicating the data from the device to a memory device, the selection being determined based on instructions included in a request.
Guim Bernat et al. (US 2019/0102299) in at least [0188] disclose selecting a data transfer operation mode from a plurality of data transfer operation modes based on telemetry data, the plurality of data transfer operation modes including a first operation mode in which a first type of data is transferred from the memory to one or more shared storage devices, and a second operation mode in which a second type of data is transferred from the memory to the one or more shared storage devices.
Ishii et al. (US 2014/0129750) in at least [0048] disclose the memory getting the respective traffic flow rates of the routes R1 to R4, chooses the best one from these four, and then starts transferring data to the memory. The selected route is kept on record and will be used over and over again, whenever data needs to be transferred to the memory again. On receiving the data transferred from ENC1, Memory Controller performs access processing to Memory and returns the resultant data to ENC1. Before returning the data, Memory Controller gets the respective traffic flow rates of the routes R1 to R4, chooses the best one from these four, and then starts transferring data to ENC1. The selected route is kept on record at Memory Controller C and will be used a number of times, whenever data needs to be transferred to ENC1 again.
Kikuchi (US 2014/0281282) in at least claims 17-18 discloses a controller that, when data is transferred from a first memory to a host, selects a transmission path capable of performing data transfer from among a plurality of the transmission paths based on a first period in each of the transmission paths before a transfer of data is started after a data transfer request is received and controls the data transfer between the first memory and the host.
Gruber et al. (US 2014/0176586) in at least the abstract disclose the memory transfer mode may be selected from a set of at least two different memory transfer modes that includes an interleave memory transfer mode and a sequential memory transfer mode to improve the performance of GPU-assisted memory transfer operations.
Kanamaru et al. (US 6,629,200) in at least col. 9, ll. 3-6 disclose one cache memory transfers its unselectable swap modes to the other cache memory and the other cache memory selects its swap mode from those transferred swap modes.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Adam Lee whose telephone number is (571) 270-3369. The examiner can normally be reached on M-TH 8AM-5PM.
If attempts to reach the above noted Examiner by telephone are unsuccessful, the Examiner’s supervisor, Pierre Vital, can be reached at the following telephone number: (571) 272-4215. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Adam Lee/Primary Examiner, Art Unit 2198 July 13, 2026
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