DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Interpretation
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph:
An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is invoked.
As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph:
(A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function;
(B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and
(C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function.
Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function.
Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function.
Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action.
Claim Objections
Claims 1-17 are objected to because of the following informalities:
Regarding claim 1: Since there is a plurality of program pulses at a plurality of corresponding program voltages, meaning that each pulse has a corresponding program voltage, and one or more of the plurality of program pulses ends in a fast ramp-down then you need to be definite as to which “the corresponding program voltage” is meant to refer to.
Examiner suggests amending the claims as follows:
Claim 1: An apparatus comprising:
one or more control circuits configured to connect to a plurality of nonvolatile memory cells, wherein the one or more control circuits are configured to:
program the plurality of nonvolatile memory cells by applying a plurality of program pulses at a plurality of corresponding program voltages on control gates of the plurality of nonvolatile memory cells, one or more of the plurality of program pulses ending in a fast ramp-down from its corresponding program voltage to an offset target voltage that is offset from a post-pulse voltage by a negative kick voltage.
Claim 2: The apparatus of claim 1, wherein the one or more control circuits are further configured to selectively apply the fast ramp-down such that one or more of the plurality of program pulses ends in a ramp-down from its corresponding program voltage with the post- pulse voltage as a target voltage.
Regarding clam 6: Since claim 1 claims one or more of the plurality of program pulses ending in a fast rap-down then we need to be definite as to which one is being referred to when stating “the fast reapd0won”. Accordingly, Examiner suggests amending the claims 6-8 as follows:
Claim 6: The apparatus of claim 3, wherein the one or more control circuits are further configured to initiate ramp-down of a voltage on an unselected word line that is not connected to control gates of the plurality of memory cells at a time that is offset from initiation of the fast ramp-down of at least one of the one or more program pulses by a delay time.
Claim 7: The apparatus of claim 6, wherein the one or more control circuits are further configured to selectively extend the delay time according to the corresponding program voltage at the time of the initiation of the fast ramp-down.
Claim 8: The apparatus of claim 7, wherein the one or more control circuits are further configured to extend the delay time such that the delay time increases with increasing amount that the program voltage is above a predetermined voltage.
Claim 12: A method of programming a plurality of nonvolatile memory cells, comprising:
applying a plurality of program pulses at a plurality of corresponding program voltages on control gates of the plurality of nonvolatile memory cells, each program pulse ending in a ramp-down from its corresponding program voltage; and
for one or more of the plurality of program pulses, ramping-down from its corresponding program voltage to a target voltage that is offset from a post-pulse voltage by a negative kick voltage.
Claim 13: The method of claim 12, further comprising:
for one or more additional program pulses of the plurality of program pulses, ramping- down from its corresponding program voltage with the post-pulse voltage as a target voltage.
Claim 15: The method of claim 14, further comprising:
increasing the magnitude of the negative kick voltage for the one or more of the plurality of program pulses according to its corresponding program voltage.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 9-11 and 18-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claims 9-11: It is not understood in plain English what is meant by”to only program pulses from a predetermined pulse”. It may be possible that Applicant intended to say to pulses in a time of after a predetermined pulse or it may be possible that Applicant intended to say to pulses following a pulse having a predetermined pulse height. Hence the claim is indefinite. It is suggested the amend as follows:
Claim 9: The apparatus of claim 1, wherein the one or more control circuits are further configured to apply the plurality of program pulses at the plurality of corresponding program voltages in order of increasing program voltage and to apply the fast ramp-down to only program pulses at a predetermined pulse height.
Claim 10: The apparatus of claim 9, wherein the one or more control circuits are further configured to increase the magnitude of the negative kick voltage from a first negative kick voltage magnitude corresponding to a pulse having the predetermined pulse height to a second negative kick voltage magnitude corresponding to a pulse having a last magnitude for a last pulse of the plurality of program pulses.
Claim 11: The apparatus of claim 10, wherein the one or more control circuits are further configured to initiate ramp-down of a voltage on an unselected word line that is not connected to control gates of the plurality of memory cells at a time that is offset from the initiation of the fast ramp-down of the pulse having the predetermined pulse height by a delay time and to extend the delay time for later pulses of the plurality of program pulses.
Regarding claims 18-20: There two instances of “a post-pulse voltage” so it is not-definite as to whether the second instance is intended to refer to the same post-pulse voltage or not. Claims 19-20 depend on claim 18. It is possible that Applicant intended to write the following:
Claim 18: A storage system comprising:
a plurality of nonvolatile memory cells arranged in NAND strings; and
means for programming the plurality of nonvolatile memory cells by applying a plurality of program pulses at a plurality of corresponding program voltages on control gates of the plurality of nonvolatile memory cells, a first subset of the plurality of program pulses ending in a ramp-down from its corresponding program voltage to a post-pulse voltage and a second subset of the plurality of program pulses ending in a fast ramp-down from its corresponding program voltage to an offset target voltage that is offset from the [[a]] post-pulse voltage by a negative kick voltage.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1 and 12 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Sarin et al. (US 2010/0046300 A1; hereinafter “Sarin”).
Regarding claim 1: Sarin (FIG. 3, FIG. 5, and FIG. 7; [0030-0043]) teaches the following:
one or more control circuits (710 in FIG. 7) configured to connect to a plurality of nonvolatile memory cells (memory array 730), wherein the one or more control circuits are configured to:
program the plurality of nonvolatile memory cells by applying a plurality of program pulses (501 and 502, for example) at a plurality of corresponding program voltages on control gates of the plurality of nonvolatile memory cells (NAND type memory cells as illustrated in FIG. 3), one or more of the plurality of program pulses ending in a fast ramp-down from the corresponding program voltage to an offset target voltage (negative biasing pulse 505) that is offset from a post-pulse voltage (0V as understood to be the level at the x-axis) by a negative kick voltage (the negative voltage level of 505; see FIG. 5).
Regarding claim 12: Sarin (FIG. 3, FIG. 5, and FIG. 7; [0030-0043]) teaches a method of programming a plurality of nonvolatile memory cells (NAND type memory cells as illustrated in FIG. 3), comprising:
applying a plurality of program pulses (501 and 502, for example) at a plurality of corresponding program voltages on control gates of the plurality of nonvolatile memory cells, each program pulse ending in a ramp-down from the corresponding program voltage; and
for one or more of the plurality of program pulses, ramping-down from the corresponding program voltage to a target voltage (negative biasing pulse 505) that is offset from a post-pulse voltage (0V as understood to be the level at the x-axis) by a negative kick voltage (the negative voltage level of 505; see FIG. 5).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or non-obviousness.
Claim(s) 2, 3, 9, 13, 14 and 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Sarin et al. (US 2010/0046300) in view of Park et al. (US 2009/0059671).
Regarding claim 2: Sarin does not specifically teach the apparatus of claim 1, wherein the one or more control circuits are further configured to selectively apply the fast ramp-down such that one or more of the plurality of program pulses ends in a ramp-down from the corresponding program voltage with the post-pulse voltage as a target voltage.
Park (FIG. 3 and FIG. 4; [0067-0078]) teaches ramping down from a respective programming pulse voltage to a target voltage of 0V for a first set of programming pulses, and then ramping down from a respective programming pulse voltage to a negative voltage for a second set of programming pulses.
It would have been obvious to incorporate the teaching of Park into the device and/or method of Sarin in a manner such that the one or more control circuits would be further configured to selectively apply the fast ramp-down such that one or more of the plurality of program pulses ends in a ramp-down from the corresponding program voltage with the post-pulse voltage as a target voltage such as the pulses in a first set of programming pulses like that taught by Park. The motivation to do so would have been to use the improved ISPP scheme of Park, wherein each pulse of a first set of the programming pulses ramps down to 0V until memory cells pass at a first verification voltage. Obviously, the time to program memory cells to the first verification voltage would be shortened since no time would be spent on applying the negative perturbation pulse or pulses.
Regarding claim 3: Sarin as modified above teaches the apparatus of claim 2, wherein the one or more control circuits are further configured to selectively apply the fast ramp-down only to program pulses having a corresponding program voltage above a predetermined voltage (the voltage of each of the programming pulses in the second set is above or greater than the voltage of the last programming pulse of the first set of programming pulses as seen in FIG. 4 of Park).
Regarding claim 9: In so far as definite, Sarin (FIG. 5) teaches the one or more control circuits are further configured to apply the plurality of program pulses at the plurality of corresponding program voltages in order of increasing program voltage.
Sarin does not specifically teach the control circuit is configured to apply the fast ramp-down to only program pulses from a predetermined pulse.
Park (FIG. 3 and FIG. 4; [0067-0078]) teaches ramping down from a respective programming pulse voltage to a target voltage of 0V for a first set of programming pulses, and then ramping down from a respective programming pulse voltage to a negative voltage for a second set of programming pulses.
It would have been obvious to incorporate the teaching of Park into the device and/or method of Sarin in a manner such that the one or more control circuits would be further configured to selectively apply the fast ramp-down such that one or more of the plurality of program pulses ends in a ramp-down from the corresponding program voltage with the post-pulse voltage as a target voltage such as the pulses in a first set of programming pulses like that taught by Park. Note that the voltage of each of the programming pulses in the second set is above or greater than the voltage of the last programming pulse (a predetermined voltage) of the first set of programming pulses as seen in FIG. 4 of Park. The motivation to do so would have been to use the improved ISPP scheme of Park, wherein each pulse of a first set of the programming pulses ramps down to 0V until memory cells pass at a first verification voltage. Obviously, the time to program memory cells to the first verification voltage would be shortened since no time would be spent on applying the negative perturbation pulse or pulses.
Regarding claim 13: Sarin does not specifically teach the method of claim 12, further comprising:
for one or more additional program pulses of the plurality of program pulses, ramping- down from the corresponding program voltage with the post-pulse voltage as a target voltage.
Park (FIG. 3 and FIG. 4; [0067-0078]) teaches ramping down from a respective programming pulse voltage to a target voltage of 0V for a first set of programming pulses, and then ramping down from a respective programming pulse voltage to a negative voltage for a second set of programming pulses.
It would have been obvious to incorporate the teaching of Park into the device and/or method of Sarin in a manner such that the one or more control circuits would be further configured to selectively apply the fast ramp-down such that one or more of the plurality of program pulses ends in a ramp-down from the corresponding program voltage with the post-pulse voltage as a target voltage such as the pulses in a first set of programming pulses like that taught by Park. Hence, the method would comprise for one or more additional program pulses of a first set of programming pulses of the plurality of program pulses, ramping-down from their corresponding program voltage to a target voltage of 0V while a second set of programming pulses would ramp-down to a negative voltage. The motivation to do so would have been to use the improved ISPP scheme of Park, wherein each pulse of a first set of the programming pulses ramps down to 0V until memory cells pass at a first verification voltage. Obviously, the time to program memory cells to the first verification voltage would be shortened since no time would be spent on applying the negative perturbation pulse or pulses.
Regarding claim 14: Sarin as modified above teaches the method of claim 13, further comprising:
applying the plurality of program pulses in order of increasing program voltage, the one or more of the plurality of program pulses including final pulses of the plurality of program pulses (the pulses in the second set of programming pulses) and the one or more additional program pulses (the pulses in the first set of programming pulses) including initial pulses of the plurality of program pulses.
Regarding claim 18: Sarin (FIG. 3, FIG. 5, and FIG. 7; [0030-0043]) teaches a storage system comprising:
a plurality of nonvolatile memory cells (memory array 730) arranged in NAND strings (FIG. 3); and
means for programming the plurality of nonvolatile memory cells (at least one of 710, 770, 744, 746 in FIG. 7) by applying a plurality of program pulses at a plurality of corresponding program voltages on control gates of the plurality of nonvolatile memory cells, a second subset of the plurality of program pulses ending in a fast ramp-down from the corresponding program voltage to an offset target voltage (negative biasing pulse 505) that is offset from a post-pulse voltage by a negative kick voltage (the negative voltage level of 505; see FIG. 5).
Sarin does not specifically teach a first subset of the plurality of program pulses ending in a ramp-down from the corresponding program voltage to a post-pulse voltage.
Park (FIG. 3 and FIG. 4; [0067-0078]) teaches ramping down from a respective programming pulse voltage to a target voltage of 0V for a first set of programming pulses, and then ramping down from a respective programming pulse voltage to a negative voltage for a second set of programming pulses.
It would have been obvious to incorporate the teaching of Park into the device and/or method of Sarin in a manner such that the means for programming would be modified such that a first subset of the plurality of program pulses would end in a ramp-down from the corresponding program voltage to a post-pulse voltage of 0V and a negative volage would not be applied after the program voltage pulse in the first set of programming pulses like that taught by Park, and a second set programming pulses would be applied, wherein a negative voltage would be applied after the programming pulse. Note that each of the programming pulses in the second set is above or greater than the voltage of the last programming pulse (a predetermined voltage) of the first set of programming pulses as seen in FIG. 4 of Park. The motivation to do so would have been to use the improved ISPP scheme of Park, wherein each pulse of a first set of the programming pulses ramps down to 0V until memory cells pass at a first verification voltage. Obviously, the time to program memory cells to the first verification voltage would be shortened since no time would be spent on applying the negative perturbation pulse or pulses (programming time would be shortened).
Claim(s) 5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Sarin et al. (US 2010/0046300) as modified by Park et al. (US 2009/0059671), and further in view of Lee (20040080980).
Regarding claim 5: Sarin as modified above does not specifically teach the apparatus of claim 3, wherein the plurality of corresponding program voltages range up to 20 volts and the predetermined voltage is between 18.5 volts and 19.5 volts.
Lee (20040080980) states in [0027] “In case of a NAND flash memory which performs a program operation using an "incremental step pulse programming (ISPP) scheme", a program voltage Vpgm, for example, can be stepwise increased from 14.7V to 20V as a program cycle is repeated.”
It would have been obvious before the effective filing date of the claimed invention to incorporate the teaching of Lee into the device and/or method of Sarin as modified above in a manner such that the plurality of corresponding program voltages would range up to 20 volts and the predetermined voltage would be between 18.5 volts and 19.5 volts since Lee teach a suitable voltage range used to program a NAND memory.
Claim(s) 19-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Sarin et al. (US 2010/0046300) as modified by Park et al. (US 2009/0059671), and further in view of Yang et al. (US 2019/0304549 A1).
Regarding claim 19: Sarin as modified above (FIG. 3 and [0023] of Sarin) teaches a NAND type non-volatile memory but does not specifically teach the storage system of claim 18 wherein:
the plurality of nonvolatile memory cells are located in a memory die;
the means for programming is located in a control die; and
the memory die is bonded to the control die to form an integrated memory assembly.
Yang teaches a plurality of nonvolatile memory cells are located in a memory die (2D or 3D NAND type non-volatile memory is disclosed in [0050, 0054]; a memory die or chips 312 is disclosed in FIG. 3 and [0054]; [0016, 0017]); a means for programming is located in a control die (a memory controller die 344 is disclosed in FIG. 3 and [0055]); and a memory die is bonded to the control die to form an integrated memory assembly (PCB, see [0054]).
It would have been obvious before the effective filing date of the claimed invention to incorporate the teaching of Yang into the device and/or method of Sarin as modified above in a manner such that the plurality of nonvolatile memory cells would be located in a memory die; the means for programming would be located in a control die; and the memory die would be bonded to the control die to form an integrated memory assembly like that taught by Yang. The motivation to do so would have been to integrate the circuits into semiconductor chips and mount them interconnected onto a board like that taught by Yang, which is a typical technique used in the art to assemble integrated circuit dies to form a module to be used in a computer.
Regarding claim 20: Sarin as modified above (FIG. 3 and [0023] of Sarin) teaches a NAND type non-volatile memory but does not specifically teach the storage system of claim 18, wherein the plurality of nonvolatile memory cells are arranged in a 3D NAND structure that includes a plurality of vertical NAND strings.
Yang teaches a plurality of nonvolatile memory cells are located in a memory die (2D or 3D NAND type non-volatile memory is disclosed in [0050-0054]; a memory die or chips 312 is disclosed in FIG. 3 and [0054]; [0016, 0017]).
It would have been obvious before the effective filing date of the claimed invention to incorporate the teaching of Yang into the device and/or method of Sarin as modified above in a manner such that the plurality of nonvolatile memory cells would be arranged in a 3D NAND structure that includes a plurality of vertical NAND strings like that taught by Yang. The motivation to do so would have been to enjoy the advantages of a 3D memory structure including having a higher density memory structure compared that of a 2D. There would be more memory cells provided per unit area of the surface of the substrate or chip compared to that of a 2D memory structure.
Allowable Subject Matter
Claims 4, 6-8 and 15-17 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Note that some of these claims are also objected to above.
Regarding claim 4: The prior art made of record and considered pertinent to the applicant's disclosure does not teach or suggest the claimed limitation of the one or more control circuits are further configured to adjust the magnitude of the negative kick voltage according to the corresponding program voltage above the predetermined voltage such that the magnitude of the negative kick voltage increases with increasing program voltage in combination with the other limitations thereof as is recited in the claim.
Regarding claim 6: The prior art made of record and considered pertinent to the applicant's disclosure does not teach or suggest the claimed limitation of the one or more control circuits are further configured to initiate ramp-down of a voltage on an unselected word line that is not connected to control gates of the plurality of memory cells at a time that is offset from initiation of the fast ramp-down by a delay time in combination with the other limitations thereof as is recited in the claim. Claims 7-8 depend on claim 6.
Regarding claim 15: The prior art made of record and considered pertinent to the applicant's disclosure does not teach or suggest the claimed limitation of increasing the magnitude of the negative kick voltage for the one or more of the plurality of program pulses according to corresponding program voltage in combination with the other limitations thereof as is recited in the claim.
Regarding claim 16: The prior art made of record and considered pertinent to the applicant's disclosure does not teach or suggest the claimed limitation of initiating fast ramp-down of a voltage on an unselected word line that is not connected to control gates of the plurality of memory cells at a time that is offset from initiation of the fast ramp-down by a delay time; and extending the delay time for program pulses having a corresponding program voltage above a predetermined voltage in combination with the other limitations thereof as is recited in the claim. Claim 17 depends on claim 16.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-20 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JAY W RADKE whose telephone number is (571)270-1622. The examiner can normally be reached M-F 9-6 EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Amir Zarabian can be reached at 272-1852. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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JAY W. RADKE
Primary Examiner
Art Unit 2827
/JAY W. RADKE/Primary Examiner, Art Unit 2827
Prosecution Insights