Prosecution Insights
Last updated: October 02, 2026
Application No. 18/614,794

HYBRID INTERCONNECT STRUCTURE WITH TOPOLOGICAL CONDUCTOR INTERFACE LAYER

Non-Final OA §102
Filed
Mar 25, 2024
Examiner
GEBREMARIAM, SAMUEL A
Art Unit
Tech Center
Assignee
International Business Machines Corporation
OA Round
1 (Non-Final)
83%
Grant Probability
Favorable
1-2
OA Rounds
2m
Est. Remaining
91%
With Interview

Examiner Intelligence

Grants 83% — above average
83%
Career Allowance Rate
704 granted / 846 resolved
+23.2% vs TC avg
Moderate +8% lift
Without
With
+8.1%
Interview Lift
resolved cases with interview
Typical timeline
2y 9m
Avg Prosecution
19 currently pending
Career history
856
Total Applications
across all art units

Statute-Specific Performance

§101
0.7%
-39.3% vs TC avg
§103
38.4%
-1.6% vs TC avg
§102
28.5%
-11.5% vs TC avg
§112
22.6%
-17.4% vs TC avg
Black line = Tech Center average estimate • Based on career data from 846 resolved cases

Office Action

§102
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Election/Restrictions Applicant’s election without traverse of group I in the reply filed on 7/29/2026 is acknowledged. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claim(s) 1-6, 8 and 10 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Maniscalco et al., US 2021/0242082. Regarding claim 1, Maniscalco discloses (fig. 1F and related text) a semiconductor structure (fig. 1F), the semiconductor structure comprising: a non-topological conductor core (142); a topological conductor interface layer (130) at least partially surrounding the non-topological conductor core (142); and a dielectric layer (106) at least partially surrounding the topological conductor interface layer (130). Regarding claim 2, Maniscalco discloses the topological conductor interface layer (130) covers a top portion (upper side surface of 142) of the non-topological conductor core (142). Regarding claim 3, Maniscalco discloses the topological conductor interface layer (132) covers a bottom portion (bottom side surfaces of 142) of the non-topological conductor core. Regarding claim 4, Maniscalco discloses a liner layer (110) at least partially surrounding the topological conductor interface layer (130). Regarding claim 5, Maniscalco discloses a first portion of the liner layer and a second portion of the liner layer are intersected by sidewalls of the topological conductor interface layer (130, fig. 1F). Regarding claim 6, Maniscalco discloses the first portion of the liner (bottom of 110) is formed underneath a bottom portion of the topological conductor interface layer (bottom of 130). Regarding claim 8, Maniscalco discloses the topological conductor interface layer (130) has a thickness ranging from 1-3 nm [0048]. Regarding claim 10, Maniscalco discloses a charge carrier doping layer (120) formed conformally between the topological conductor interface layer (130) and the liner layer (110). Claim(s) 1, 4-5 and 7 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Maniscalco et al., US 2021/0242082. Regarding claim 1, Maniscalco discloses (fig. 3F and related text) a semiconductor structure (fig. 3F), the semiconductor structure comprising: a non-topological conductor core (242); a topological conductor interface layer (130) at least partially surrounding the non-topological conductor core (242); and a dielectric layer (106) at least partially surrounding the topological conductor interface layer (130). Regarding claim 4, Maniscalco discloses a liner layer (110) at least partially surrounding the topological conductor interface layer (130). Regarding claim 5, Maniscalco discloses a first portion (left side 110) of the liner layer and a second portion (right side) of the liner layer (110) are intersected by sidewalls of the topological conductor interface layer (130, fig. 3F). Regarding claim 7, Maniscalco discloses bottom surfaces of the sidewalls of the topological conductor interface layer (130) are coplanar with a bottom surface of the first portion of the liner layer (110, fig. 3F). Allowable Subject Matter Claim 9 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to SAMUEL A GEBREMARIAM whose telephone number is (571)272-1653. The examiner can normally be reached 8:30-4PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Lynne Gurley can be reached at 571-272-1670. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /SAMUEL A GEBREMARIAM/Primary Examiner, Art Unit 2811
Read full office action

Prosecution Timeline

Mar 25, 2024
Application Filed
Sep 08, 2026
Non-Final Rejection mailed — §102
Sep 24, 2026
Applicant Interview (Telephonic)
Sep 24, 2026
Examiner Interview Summary

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
83%
Grant Probability
91%
With Interview (+8.1%)
2y 9m (~2m remaining)
Median Time to Grant
Low
PTA Risk
Based on 846 resolved cases by this examiner. Grant probability derived from career allowance rate.

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