DETAILED ACTION
This action is responsive to application No. 18/614,804 filed on March 25, 2024.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Species 1 reading on Figs. 11-12 in the reply filed on 08/17/2026 is acknowledged. The Applicants indicated that claims 1-5, 7, 8, 10, and 16-20 read on the elected species. Claims 6, 9, and 11-15 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a non-elected species, there being no allowable generic or linking claim. Accordingly, pending in this Office action are claims 1-20.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-5, 7, 8, 10, and 16-20 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Lee (US 2023/0317784).
Regarding Claim 1, Lee (see, e.g., Figs. 2R-1, 2R-2, and Annotated Fig. 2R-1), teaches an integrated circuit device, comprising:
a fin-type active region 104 that protrudes from a substrate 102 and extends in a first horizontal direction X (see, e.g., par. 0018);
a plurality of nanosheets 108 disposed on the fin-type active region 104 and that are separated from each other in a vertical direction Z (see, e.g., par. 0020);
a gate line 150 that extends in a second horizontal direction Y perpendicular to the first horizontal direction X and surrounds the plurality of nanosheets 108 on the fin-type active region 104, wherein the gate line 150 includes sub-gate portions 150S interposed between the plurality of nanosheets 108 and a main gate portion 150M disposed above the uppermost layer of the plurality of nanosheets 108 (see, e.g., par. 0130);
a source/drain region 136 disposed on the fin-type active region 104, adjacent to the gate line 150, and connected to the plurality of nanosheets 108 (see, e.g., par. 0097); and
a plurality of inner spacers 132/120 interposed between the gate line 150 and the source/drain region 136, wherein shapes of first inner spacers 132 that face the sub-gate portions 150S differ from a shape of a second inner spacer 120 that faces the main gate portion 150M (see, e.g., pars. 0065, 0095).
Regarding Claim 2, Lee teaches all aspects of claim 1. Lee (see, e.g., Figs. 2R-1, 2R-2, and Annotated Fig. 2R-1), teaches that:
the main gate portion 150M has an inverted T shape in which a horizontal width W1 of a lower region 150L is greater than a horizontal width W2 of an upper region 150U,
the second inner spacer 120 is disposed on a sidewall of the lower region 150L of the main gate portion 150M, and
the integrated circuit device further includes an outer spacer 124 disposed on a sidewall of the upper region 150U of the main gate portion 150M (see, e.g., par. 0062).
Regarding Claim 3, Lee teaches all aspects of claim 2. Lee (see, e.g., Figs. 2R-1, 2R-2, and Annotated Fig. 2R-1), teaches that:
a thickness T1 of the lower region 150L of the main gate portion 150M in the vertical direction Z is less than a thickness T2 of each of the sub-gate portions 150S in the vertical direction Z, and
a horizontal width W1 of the lower region 150L of the main gate portion 150M is substantially the same as a horizontal width W1 of each of the sub-gate portions 150S.
Regarding Claim 4, Lee teaches all aspects of claim 2. Lee (see, e.g., Figs. 2R-1, 2R-2, and Annotated Fig. 2R-1), teaches that the plurality of inner spacers 132/120 overlap the outer spacer 124 in the vertical direction Z.
Regarding Claim 5, Lee teaches all aspects of claim 1. Lee (see, e.g., Figs. 2R-1, 2R-2, and Annotated Fig. 2R-1), teaches that:
a thickness t2 of each of the first inner spacers 132 in the vertical direction Z is greater than a thickness t1 of the second inner spacer 120 in the vertical direction Z, and
a width W3 of a central portion of each of the first inner spacers 132 in the first horizontal direction X is greater than a width W4 of a central portion of the second inner spacer 120 in the first horizontal direction X.
Regarding Claim 7, Lee teaches all aspects of claim 1. Lee (see, e.g., Figs. 2R-1, 2R-2, and Annotated Fig. 2R-1), teaches that:
a thickness t2 of each of the first inner spacers 132 in the vertical direction Z is greater than a thickness t1 of the second inner spacer 120 in the vertical direction Z,
each of the first inner spacers 132 and the second inner spacer 120 includes an outer wall with a recessed central portion,
widths W6/W5 of the top and the bottom of each of the first inner spacers 132 in the first horizontal direction X are substantially the same as each other, and
widths W8/W7 of the top and the bottom of the second inner spacer 120 in the first horizontal direction X differ from each other.
Regarding Claim 8, Lee teaches all aspects of claim 1. Lee (see, e.g., Figs. 2R-1, 2R-2, and Annotated Fig. 2R-1), teaches further comprising:
a gate dielectric layer 148 that surrounds the gate line 150,
wherein a shape of a first gate dielectric layer 148 adjacent to each of the first inner spacers 132 differs from a shape of a second gate dielectric layer 148 adjacent to the second inner spacer 120.
Regarding Claim 10, Lee teaches all aspects of claim 1. Lee (see, e.g., Figs. 2R-1, 2R-2, and Annotated Fig. 2R-1), teaches that the plurality of nanosheets 108 comprise three layers, and the plurality of inner spacers 132 comprise four layers.
Regarding Claim 16, Lee (see, e.g., Figs. 2R-1, 2R-2, and Annotated Fig. 2R-1), teaches an integrated circuit device, comprising:
a fin-type active region 104 that protrude from a substrate 102 and extends in a first horizontal direction X (see, e.g., par. 0018);
a plurality of nanosheet layers 108 disposed on the fin-type active region 104 and separated from each other in a vertical direction Z (see, e.g., par. 0020);
a gate line 150 that extends in a second horizontal direction Y perpendicular to the first horizontal direction X and surrounds the plurality of nanosheet layers 108 on the fin-type active region 104, wherein the gate line 150 includes sub-gate portions 150S interposed between the plurality of nanosheet layers 108 and a main gate portion 150M disposed above the uppermost layer of the plurality of nanosheet layers 108 (see, e.g., par. 0130);
a source/drain region 136 disposed on the fin-type active region 104, adjacent to the gate line 150, and connected to the plurality of nanosheet layers 108 (see, e.g., par. 0097);
an inter-gate insulating layer 140 disposed adjacent to the gate line 150 on the source/drain region 136 (see, e.g., par. 0105);
a plurality of inner spacer layers 132/120 that include first inner spacers 132 interposed between the sub-gate portions 150S and the source/drain region 136 and a second inner spacer 120 interposed between a lower region 150L of the main gate portion 150M and the source/drain region 136 (see, e.g., pars. 0065, 0095);
an outer spacer 124 interposed between an upper region 150U of the main gate portion 150M and the inter-gate insulating layer 140 (see, e.g., par. 0062); and
a gate dielectric layer 148 that surrounds the gate line 150 (see, e.g., par. 0130),
wherein shapes of the first inner spacers 132 that face the sub-gate portions 150S between the plurality of nanosheet layers 108 differ from a shape of a second inner spacer 120 that faces the lower region 150L of the main gate portion 150M (see, e.g., pars. 0065, 0095).
Regarding Claim 17, Lee teaches all aspects of claim 16. Lee (see, e.g., Figs. 2R-1, 2R-2, and Annotated Fig. 2R-1), teaches that:
the main gate portion 150M has an inverted T shape in which a horizontal width W1 of the lower region 150L is greater than a horizontal width W2 of the upper region 150U,
a thickness T1 of the lower region 150L of the main gate portion 150M in the vertical direction Z is less than a thickness T2 of each of the sub-gate portions 150S in the vertical direction Z, and
a horizontal width W1 of the lower region 150L of the main gate portion 150M is substantially the same as a horizontal width of each of the sub-gate portions 150S.
Regarding Claim 18, Lee teaches all aspects of claim 16. Lee (see, e.g., Figs. 2R-1, 2R-2, and Annotated Fig. 2R-1), teaches that:
a thickness t2 of each of the first inner spacers 132 in the vertical direction Z is greater than a thickness t1 of the second inner spacer 120 in the vertical direction Z, and
a width W3 of a central portion of each of the first inner spacers 132 in the first horizontal direction X is greater than a width W4 of a central portion of the second inner spacer 120 in the first horizontal direction X.
Regarding Claim 19, Lee teaches all aspects of claim 16. Lee (see, e.g., Figs. 2R-1, 2R-2, and Annotated Fig. 2R-1), teaches that the second inner spacer 120 is disposed on the uppermost layer 108 of the plurality of layers of nanosheets 108.
Regarding Claim 20, Lee teaches all aspects of claim 19. Lee (see, e.g., Figs. 2R-1, 2R-2, and Annotated Fig. 2R-1), teaches that:
the lower surface of the second inner spacer 120 is in contact with the uppermost layer 108 of the plurality of nanosheet layers 108, and
the upper surface of the second inner spacer 120 is in contact with the lower surface of the outer spacer 124.
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Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Nelson Garcés whose telephone number is (571)272-8249. The examiner can normally be reached on M-F 9:00 AM - 5:30 PM.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Wael Fahmy can be reached on (571)272-1705. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/Nelson Garces/
Primary Examiner, Art Unit 2814
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