DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1, 3-8, 11-16, and 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over Ray (US 2022/0137655) in view of Zhu (2011/0121802, of record).
Claim 1: Ray discloses a structure (Fig.1) comprising:
a transistor (140) including: a first terminal connected to receive an input voltage node (supply terminal receiving Vdd); a second terminal connected to an output voltage node (drain, providing Vreg); and a third terminal, wherein the third terminal is a control terminal (gate terminal);
a first feedback control loop (from Vreg to 110 to 130 to the input of 140) connected between the feedback voltage node (Vreg) and the third terminal (gate terminal of 140), wherein the first feedback control loop includes a fast amplifier (110; see [0030]) and wherein the fast amplifier includes first inputs connected to receive a feedback voltage (Vreg) from the feedback voltage node and a reference voltage (Vref); and
a second feedback control loop (from Vreg to 120 to 130 to the input of 140) connected between the feedback voltage node (Vreg) and the third terminal (gate terminal of 140), wherein the second feedback control loop includes a slow amplifier (120; see [0030]) and wherein the operational amplifier includes second inputs connected to receive the feedback voltage (Vreg) and the reference voltage (Vref; see Fig.1).
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There are two differences between the recited invention of claim 1. First, Ray does not explicitly disclose “a voltage divider connected between the second terminal and a ground voltage rail, wherein the voltage divider includes a feedback voltage node”. Second, Ray does not explicitly disclose the slow amplifier as an operational amplifier and the fast amplifier as a comparator.
Regarding the first difference, Zhu discloses that in a similar linear regulator context, a voltage divider (RF1, RF2) may be utilized to provide the feedback voltage (FB) in order to provide a desired output voltage (see [0005], where the output voltage VOUT = VREF * (RF1 + RF2)/RF2). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the application to have provided the feedback voltage of Ray via a voltage divider, as disclosed by Zhu, in order to have provided a desired output voltage.
Regarding the second difference, Zhu discloses that a slow amplifier in a similar linear regulator feedback loop may be an operational amplifier (I0; see [0029]) and that a fast amplifier may be a comparator (see [0029]). As providing an operational amplifier as the slow amplifier and a comparator as the fast amplifier would result in the same function as the generic slow and fast amplifiers described by Ray, the results of substituting the slow amplifier with an operational amplifier and the fast amplifier with a comparator would have been predictable to one of ordinary skill in the art. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the application to have provided an operational amplifier as the slow amplifier of Ray and a comparator as the fast amplifier of Ray as the simple substitution of known elements for others to obtain predictable results.
Claim 8: Ray discloses a structure comprising:
a P-type field effect transistor (140) including: a gate (see Fig.1); a source region connected to an input voltage node (connected to Vdd); and a drain region connected to an output voltage node (connected to Vref);
a first feedback control loop (110, 130) including a fast amplifier (110), wherein the comparator includes: first inputs connected to receive a feedback voltage from the feedback voltage node (Vreg) and a reference voltage (Vref); and a first output (output of 110); and
a second feedback control loop (120, 130) including a slow amplifier (120), wherein the operational amplifier includes second inputs connected to receive the feedback voltage (Vreg) and the reference voltage (Vref) and a second output connected to the gate (see Fig.1).
Claim 16: Ray discloses a structure comprising:
a P-type field effect transistor (140) including: a gate (gate); a source region connected to an input voltage node (receiving Vdd); and a drain region connected to an output voltage node (providing Vref);
a first feedback control loop (110, 130) including a fast amplifier (110), wherein the fast amplifier includes: first inputs connected to receive a feedback voltage (Vreg) from the feedback voltage node and a reference voltage (Vref); and a first output (output of 110),
a second feedback control loop (120, 130) including a slow amplifier (120), wherein the operational amplifier includes: second inputs connected to receive the feedback voltage (Vreg) and the reference voltage (Vref) and a second output connected to the gate (see Fig.1); and
a current load (150) connected to the output voltage node (see Fig.1),
wherein the current load is variable (see [0027], which discusses changes in the load),
wherein the first feedback control loop and the second feedback control loop cause changes in conductivity of the PFET in response to variations in the current load to reduce ripple of an output voltage at the output voltage node (see [0023]), and
wherein the first feedback control loop initiates the changes in the conductivity of the PFET faster than second feedback control loop (see [0030]).
There are three differences between the recited invention of claims 8 and 16. First, Ray does not explicitly disclose “a voltage divider connected between the second terminal and a ground voltage rail, wherein the voltage divider includes a feedback voltage node”. Second, Ray does not explicitly disclose the slow amplifier as an operational amplifier and the fast amplifier as a comparator. Third, Ray does not disclose the recited “capacitor … connected between the first output and the gate”.
Regarding the first difference, Zhu discloses that in a similar linear regulator context, a voltage divider (RF1, RF2) may be utilized to provide the feedback voltage (FB) in order to provide a desired output voltage (see [0005], where the output voltage VOUT = VREF * (RF1 + RF2)/RF2). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the application to have provided the feedback voltage of Ray via a voltage divider, as disclosed by Zhu, in order to have provided a desired output voltage.
Regarding the second difference, Zhu discloses that a slow amplifier in a similar linear regulator feedback loop may be an operational amplifier (I0; see [0029]) and that a fast amplifier may be a comparator (see [0029]). As providing an operational amplifier as the slow amplifier and a comparator as the fast amplifier would result in the same function as the generic slow and fast amplifiers described by Ray, the results of substituting the slow amplifier with an operational amplifier and the fast amplifier with a comparator would have been predictable to one of ordinary skill in the art. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the application to have provided an operational amplifier as the slow amplifier of Ray and a comparator as the fast amplifier of Ray as the simple substitution of known elements for others to obtain predictable results.
Regarding the third difference, Zhu discloses that a Miller capacitor Cc may be provided with one terminal connected between the output of the fast amplifier and the gate (e.g. at the gate node of MPR, which is “between” the gate terminal and the output of I1). The examiner notes that the broadest reasonable interpretation of “coupled between” includes a single terminal of the capacitor coupled at a node between the recited elements, which Zhu discloses, and does not specifically require the capacitor coupled in series between the first output and the gate. Zhu discloses that such a Miller capacitor is provided to stabilize the operational amplifier loop (see [0051]). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the application to have further provided the capacitor Cc of Zhu, with one terminal connected between the first output and the gate, to the pass transistor of Ray in order to have stabilized the operational amplifier loop.
Claim 3: the combination discloses wherein the operational amplifier further includes a second output (output of 120, corresponding to the output of I0 of Zhu), and wherein the third terminal is connected to the second output to receive an analog control voltage from the operational amplifier (output of 120, corresponding to the output I0 of Zhu).
Claim 4: the combination discloses wherein the voltage divider includes: a first resistor (RF1) connected between the second terminal and the feedback voltage node (see Fig.2 of Zhu); and a second resistor (RF2) connected between the feedback voltage node (FB) and the ground voltage rail (AVS of Zhu).
Claims 5 and 13: although neither reference explicitly discloses wherein the first resistor has a first resistance and the second resistor has a second resistance that is smaller than the first resistance, Zhu discloses that the output voltage is a function of the particular values chosen for each of RF1 and RF2 (see [0005]). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to have provided a first resistor with a smaller resistance than the second resistor in order to have provided a desired output voltage according to VOUT = VREF * (RF1 + RF2)/RF2.
Claims 6 and 14: Ray does not explicitly disclose a capacitive load connected to the output voltage node in the embodiment of Fig.1. However, Ray discloses such a capacitive load (260) in the embodiment of Fig.2 in order to reduce a ripple for the load current at frequencies greater than an open loop frequency bandwidth (see [0035]). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the application to have further provided a capacitive load connected to the output voltage load, as disclosed in Fig.2 of Ray, in order to have reduced a ripple for the load current at frequencies greater than an open loop frequency bandwidth.
Claims 7 and 15: Ray discloses a current load (150) connected to the output voltage node (see Fig.1), wherein the current load is variable (see [0027], which discusses changes in the load), wherein the first feedback control loop and the second feedback control loop cause changes in conductivity of the PFET in response to variations in the current load to reduce ripple of an output voltage at the output voltage node (see [0023]), and wherein the first feedback control loop initiates the changes in the conductivity of the PFET faster than second feedback control loop (see [0030]).
Claims 11 and 19: the combination discloses wherein the comparator has a faster switching speed than the operational amplifier (see [0029] of Zhu).
Claims 12 and 20: the combination discloses wherein the voltage divider includes: a first resistor connected between the drain region and the feedback voltage node (RF1 of Zhu, connected between the drain of the pass transistor and FB); and a second resistor connected between the feedback voltage node and the ground voltage rail (RF2 of Zhu, connected between the feedback voltage node FB and AVS).
Allowable Subject Matter
Claims 2, 9-10, and 17-18 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: the prior art does not disclose within the overall context of the claims:
a capacitor having a first capacitor plate connected to the first output to receive a digital control voltage from the comparator and further having a second capacitor plate connected to the third terminal (claims 2, 9, and 17)
wherein the second inputs include a second inverting input connected to receive the reference voltage and a second non-inverting input connected to receive the feedback voltage herein the operational amplifier outputs an analog control voltage from the second output to the gate, wherein, when the feedback voltage drops below the reference voltage, the analog control voltage decreases to increase conductivity of the PFET and to increase an output voltage at the output voltage node, and wherein, when the feedback voltage rises above the reference voltage, the analog control voltage increases to decrease the conductivity of the PFET and to decrease the output voltage at the output voltage node (claims 10 and 18).
Response to Arguments
Applicant’s arguments, see pgs.10-15, filed 2/23/2026, with respect to the rejections of claims 1, 3-4, 7-8, 11-12, 15-16, and 19-20 over Zhu, claims 1 and 2 over Milanesi, and claims 1 and 6 over Zhang have been fully considered and are persuasive. Therefore, the rejections have been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Ray, as discussed above.
With regard to Applicant’s argument pertaining to claims 5 and 13, Applicant’s argument has been considered but is not persuasive. Applicant argues that because Kwong does not specifically discloses the resistance value of the second resistor smaller than the first, the teaching of Kwong do not cure the deficiency. Initially, the examiner notes that the new rejection of the amended claim is now directed to Ray in view of Zhu. As noted above, Zhu clearly discloses each of RF1 and RF2 as result-effective variables, which provide a desired output voltage according to the equation VOUT = VREF * (RF1 + RF2)/RF2 (see [0005]). Therefore, although the particular resistor values are not disclosed, one of ordinary skill in the art would have clearly been led by this mathematical relationship to chose a lower resistance value for RF2 in order to achieve a particular value of VOUT. See MPEP 2144.02 and MPEP 2144.05.II.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/RYAN JOHNSON/ Primary Examiner, Art Unit 2849