DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Claims 8-17 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected Group II, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 07/06/2026.
Priority
Acknowledgment is made of applicant's claim for foreign priority based on an application filed in Republic of Korea on 03/24/2023. It is noted, however, that applicant has not filed a certified copy of the KR 10-2023-003866 application as required by 37 CFR 1.55.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
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Claims 1-4 and 7 are provisionally rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-19 of copending Application No.18/758,609 (reference application). Although the claims at issue are not identical, they are not patentably distinct from each other because application claims 1-4 and 7 are anticipated by claims 1-19 of the copending Application, and it is not patentably distinct from claims 1-19 of the copending Application
Application Under Examination Claims
copending Application claims
1. A lateral gallium oxide transistor, comprising:
a gallium oxide substrate; an n-type gallium oxide epitaxial layer epitaxially grown on the gallium oxide substrate;
an insulating layer defining a gate region, a source region, and a drain region on the n-type gallium oxide epitaxial layer;
a p-type nickel oxide layer deposited on the n-type gallium oxide epitaxial layer exposed in the gate region;
a dielectric layer deposited on the p-type nickel oxide layer;
a gate electrode layer deposited on the dielectric layer; and
a source electrode and a drain electrodes formed on the n-type gallium oxide epitaxial layer exposed in the source region and the drain region.
Anticipated by copending Application claim 1:
1. A lateral gallium oxide transistor, comprising:
a gallium oxide substrate; an n-type gallium oxide epitaxial layer epitaxially grown on the gallium oxide substrate;
an insulating layer defining a gate region, a source region, and a drain region on the n-type gallium oxide epitaxial layer;
a diffusion barrier layer deposited on the n-type gallium oxide epitaxial layer exposed in the gate region;
a p-type nickel oxide layer deposited on the diffusion barrier layer;
a dielectric layer deposited on the p-type nickel oxide layer;
a gate electrode layer deposited on the dielectric layer; and
a source electrode and a drain electrode formed on the n-type gallium oxide epitaxial layer exposed in the source region and the drain region.
2. The lateral gallium oxide transistor of claim 1, wherein the n-type gallium oxide epitaxial layer comprises a recessed gate trench extending inwardly in the gate region, wherein the p-type nickel oxide layer is deposited on the bottom of the recessed gate trench to form a pn heterojunction with the n-type gallium oxide epitaxial layer.
Anticipated by copending Application claims 2 and 8:
2. The lateral gallium oxide transistor of claim 1, wherein the diffusion barrier layer is deposited at a thickness such that a pn heterojunction is formed between the p-type nickel oxide layer and the n-type gallium oxide epitaxial layer while preventing nickel diffusion from the p-type nickel oxide layer to the n-type gallium oxide epitaxial layer (as claimed in copending Application claim 2).
8. The lateral gallium oxide transistor of claim 1, wherein the n-type gallium oxide epitaxial layer comprises a recessed gate trench etched inwardly in the gate region, and the diffusion barrier layer is deposited on a bottom of the recessed gate trench (as claimed in copending Application claim 8).
3. The lateral gallium oxide transistor of claim 2, wherein a sidewall of the recessed gate trench has a slope of 45 degrees to 70 degrees.
Anticipated by copending Application claim 9:
9. The lateral gallium oxide transistor of claim 8, wherein a sidewall of the recessed gate trench has a slope of 45 degrees to 70 degrees.
4. The lateral gallium oxide transistor of claim 1, wherein the dielectric layer is formed of aluminum oxide.
Anticipated by copending Application claim 10:
10. The lateral gallium oxide transistor of claim 1, wherein the dielectric layer is formed of aluminum oxide.
7. A method of manufacturing lateral gallium oxide transistor, comprising:
forming an insulating layer defining a gate region, a source region, and a drain region on an n-type gallium oxide epitaxial layer epitaxially grown on an n-type gallium oxide substrate;
depositing a p-type nickel oxide layer on the n-type gallium oxide epitaxial layer exposed in the gate region;
depositing a dielectric layer on the p-type nickel oxide layer; depositing a gate electrode layer on the dielectric layer; and
forming source and drain electrodes on the n-type gallium oxide epitaxial layer exposed in the source region and the drain region.
Anticipated by copending Application claim 11:
11. A method of manufacturing lateral gallium oxide transistor, comprising:
forming an insulating layer defining a gate region, a source region, and a drain region on an n-type gallium oxide epitaxial layer epitaxially grown on an n-type gallium oxide substrate;
depositing a diffusion barrier layer on the n-type gallium oxide epitaxial layer exposed in the gate region;
depositing a p-type nickel oxide layer on the diffusion barrier layer;
depositing a dielectric layer on the p-type nickel oxide layer; depositing a gate electrode layer on the dielectric layer; and
forming source and drain electrodes on the n-type gallium oxide epitaxial layer exposed in the source region and the drain region.
This is a provisional nonstatutory double patenting rejection because the patentably indistinct claims have not in fact been patented.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1 is rejected under 35 U.S.C. 102(a)(1) as being anticipated by Feng et al. (CN 114899238 A, hereinafter refer to Feng).
CN 114899238 A, (hereinafter refer to Feng) is relied upon solely for the English language translation of CN 114899238 A.
Regarding Claim 1: Feng discloses a lateral gallium oxide transistor (see Feng, Fig.1 as shown below and abstract), comprising:
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a gallium oxide substrate (1/2) (see Feng, Fig.1 as shown above);
an n-type gallium oxide epitaxial layer (3) epitaxially grown on the gallium oxide substrate (1/2) (see Feng, Fig.1 as shown above);
an insulating layer (note: the spacing between the gate structure and source/drain structure is considered as insulating layer since air spacing is known as the best insulating layer) defining a gate region, a source region, and a drain region on the n-type gallium oxide epitaxial layer (3) (see Feng, Fig.1 as shown above);
a p-type nickel oxide layer (4) deposited on the n-type gallium oxide epitaxial layer (3) exposed in the gate region (see Feng, Fig.1 as shown above);
a dielectric layer (5, note: “the low concentration of the p-type NiO film layer hole concentration becomes lower after the annealing process, the conductive ability is weak, so that the low concentration of the p-type NiO film layer acts as a gate dielectric layer”) deposited on the p-type nickel oxide layer (4) (see Feng, Fig.1 as shown above and page.4);
a gate electrode layer (8) deposited on the dielectric layer (5) (see Feng, Fig.1 as shown above); and
a source electrode (6) and a drain electrodes (7) formed on the n-type gallium oxide epitaxial layer (3) exposed in the source region and the drain region (see Feng, Fig.1 as shown above).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 2 is rejected under 35 U.S.C. 103 as being unpatentable over Feng et al. (CN 114899238 A, hereinafter refer to Feng) as applied to claim 1 above, and further in view of X. Zhou, Q. Liu, W. Hao, G. Xu and S. Long, "Normally-off β-Ga2O3 Power Heterojunction Field-Effect-Transistor Realized by p-NiO and Recessed-Gate" (hereinafter refer to Zhou).
CN 114899238 A, (hereinafter refer to Feng) is relied upon solely for the English language translation of CN 114899238 A.
Regarding Claim 2: Feng discloses a lateral gallium oxide transistor as applied to claim 1 above. Feng is silent upon explicitly disclosing wherein the n-type gallium oxide epitaxial layer comprises a recessed gate trench extending inwardly in the gate region, wherein the p-type nickel oxide layer is deposited on the bottom of the recessed gate trench to form a pn heterojunction with the n-type gallium oxide epitaxial layer.
For support see Zhou, which teaches wherein the n-type gallium oxide epitaxial layer comprises a recessed gate trench extending inwardly in the gate region, wherein the p-type nickel oxide layer is deposited on the bottom of the recessed gate trench to form a pn heterojunction with the n-type gallium oxide epitaxial layer (see Zhou, Fig.2 as shown below and abstract).
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Thus, it would have been obvious to one of ordinary skill in the art before effective filing date of the claimed invention to combine the teachings of Feng and Zhou to enable the n-type gallium oxide epitaxial layer to comprise a recessed gate trench extending inwardly in the gate region, wherein the p-type nickel oxide layer deposited on the bottom of the recessed gate trench to form a pn heterojunction with the n-type gallium oxide epitaxial layer as taught by Zhou in order to realize high performance normally-off β-Ga2O3 FETs.
Claim(s) 3 is rejected under 35 U.S.C. 103 as being unpatentable over Feng et al. (CN 114899238 A, hereinafter refer to Feng) and X. Zhou, Q. Liu, W. Hao, G. Xu and S. Long, "Normally-off β-Ga2O3 Power Heterojunction Field-Effect-Transistor Realized by p-NiO and Recessed-Gate" (hereinafter refer to Zhou) as applied to claim 2 above, and further in view of Rahimo et al. (U.S. 2021/0104614 A1, hereinafter refer to Rahimo).
CN 114899238 A, (hereinafter refer to Feng) is relied upon solely for the English language translation of CN 114899238 A.
Regarding Claim 3: Feng as modified teaches a lateral gallium oxide transistor as applied to claim 2 above. The combination of Feng and Zhou is silent upon explicitly disclosing wherein a sidewall of the recessed gate trench has a slope of 45 degrees to 70 degrees.
For support see Rahimo, which teaches wherein a sidewall of the recessed gate trench has a slope of 45 degrees to 70 degrees (see Rahimo, Figs.9-10, abstract, and ¶ [0061]- ¶ [0062]).
Thus, it would have been obvious to one of ordinary skill in the art before effective filing date of the claimed invention to combine the teachings of Feng, Zhou, and Rahimo to enable the sidewall of the recessed gate trench to have a slope of 45 degrees to 90 degrees as taught by Rahimo in order to reduce losses and improve controllability, reliability, and processability (narrow mesa design rules).
Claim(s) 4 is rejected under 35 U.S.C. 103 as being unpatentable over Feng et al. (CN 114899238 A, hereinafter refer to Feng) as applied to claim 1 above, and further in view of Sasaki et al. (JP 2019-192871 A, hereinafter refer to Sasaki).
CN 114899238 A, (hereinafter refer to Feng) is relied upon solely for the English language translation of CN 114899238 A.
JP 2019-192871 A (hereinafter refer to Sasaki) is relied upon solely for the English language translation of JP 2019-192871 A.
Regarding Claim 4: Feng discloses a lateral gallium oxide transistor as applied to claim 1 above. Feng is silent upon explicitly disclosing wherein the dielectric layer is formed of aluminum oxide.
For support see Sasaki, which teaches wherein the dielectric layer (15) is formed of aluminum oxide (see Sasaki, Fig.2 and page.7).
Feng discloses the claimed invention except for the materials of dielectric layer. Thus, it would have been obvious to one of ordinary skill in the art before effective filing date of the claimed invention to combine the teachings of Feng and Sasaki to enable the known dielectric layer material as taught by Sasaki in order to mprove the performance of the transistor and the amplification factor, since it has been held to be within the general skill of a worker in the art to select a known material on the base of its suitability, for its intended use involves only ordinary skill in the art. In re Leshin, 125 USPQ 416.
Claim(s) 5-6 are rejected under 35 U.S.C. 103 as being unpatentable over Feng et al. (CN 114899238 A, hereinafter refer to Feng) as applied to claim 1 above, and further in view of Carey, Patrick H., et al. "Improvement of Ohmic contacts on Ga2O3 through use of ITO-interlayers." Journal of Vacuum Science and Technology B, (hereinafter refer to Patrick).
CN 114899238 A, (hereinafter refer to Feng) is relied upon solely for the English language translation of CN 114899238 A.
Regarding Claim 5: Feng discloses a lateral gallium oxide transistor as applied to claim 1 above. Feng is silent upon explicitly disclosing wherein the source and drain electrodes comprises: an n-type contact layer deposited on the n-type gallium oxide epitaxial layer exposed in the source region and the drain region; a first electrode layer deposited on the n-type contact layer; and a second electrode layer deposited on the first electrode layer.
For support see Patrick, which teaches wherein the source and drain electrodes comprises: an n-type contact layer (ITO) deposited on the n-type gallium oxide epitaxial layer exposed in the source region and the drain region (see Patrick, Fig.1(b) as shown below and abstract);
a first electrode layer (Ti) deposited on the n-type contact layer (ITO) (see Patrick, Fig.1(b) as shown below and abstract); and
a second electrode layer (Au) deposited on the first electrode layer (Ti) (see Patrick, Fig.1(b) as shown below and abstract).
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Thus, it would have been within the scope of one of ordinary skill in the art before effective filing date of the claimed invention to combine the teachings of Feng and Patrick to enable the Feng source/drain electrode to be performed according to the teachings of Patrick because one of ordinary skill in the art before effective filing date of the claimed invention would have been motivated to look to alternative suitable methods of performing the disclosed source/drain electrode of Feng and art recognized suitability for improving an ohmic contact of source/drain electrode with n-type doped Ga2O3 layer has been recognized to be motivation to combine. MPEP § 2144.07.
Regarding Claim 6: Feng as modified teaches a lateral gallium oxide transistor as set forth in claim 5 as above. The combination of Feng and Patrick further teaches wherein the n-type contact layer is formed of ITO (Indium tin oxide) (see Patrick, Fig.1(b) as shown above and abstract).
Claim(s) 7 is rejected under 35 U.S.C. 103 as being unpatentable over Feng et al. (CN 114899238 A, hereinafter refer to Feng) in view of Kang (KR 2020-0050485 A, hereinafter refer to Kang).
CN 114899238 A, (hereinafter refer to Feng) is relied upon solely for the English language translation of CN 114899238 A.
KR 2020-0050485 A (hereinafter refer to Kang) is relied upon solely for the English language translation of KR 2020-0050485 A.
Regarding Claim 7: Feng discloses a method of manufacturing lateral gallium oxide transistor (see Feng, Fig.1 as shown above and abstract), comprising:
forming an insulating layer (note: the spacing between the gate structure and source/drain structure is considered as insulating layer since air spacing is known as the best insulating layer) defining a gate region, a source region, and a drain region on an n-type gallium oxide epitaxial layer (3) epitaxially grown on (non-intentionally doped UID) gallium oxide substrate (2) (see Feng, Fig.1 as shown above);
depositing a p-type nickel oxide layer (4) on the n-type gallium oxide epitaxial layer (3) exposed in the gate region (see Feng, Fig.1 as shown above);
depositing a dielectric layer (5, note: “the low concentration of the p-type NiO film layer hole concentration becomes lower after the annealing process, the conductive ability is weak, so that the low concentration of the p-type NiO film layer acts as a gate dielectric layer”) on the p-type nickel oxide layer (4) (see Feng, Fig.1 as shown above);
depositing a gate electrode layer (8) on the dielectric layer (5) (see Feng, Fig.1 as shown above); and
forming source and drain electrodes (6/7) on the n-type gallium oxide epitaxial layer (3) exposed in the source region and the drain region (see Feng, Fig.1 as shown above).
Feng is silent upon explicitly disclosing wherein on an n-type gallium oxide epitaxial layer epitaxially grown on an n-type gallium oxide substrate.
For support see Kang, which teaches wherein on an n-type gallium oxide epitaxial layer (110) epitaxially grown on an n-type gallium oxide substrate (100) (see Kang, Fig.1 as shown below, abstract, and page.3).
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Thus, it would have been obvious to one of ordinary skill in the art before effective filing date of the claimed invention to combine the teachings of Feng and Kang to enable the Feng n-type gallium oxide epitaxial layer epitaxial layer to grown on an n-type gallium oxide substrate as taught by Kang in order to improve the power semiconductor device.
Conclusion
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/BITEW A DINKE/ Primary Examiner, Art Unit 2812
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