DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of claims 1-9 and 18-24 in the reply filed on 6/24/2026 is acknowledged.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-4, 8, and 9 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Scanlan et al (U.S. Pub #2015/0187710).
With respect to claim 1, Scanlan teaches a method, comprising:
laminating first (Fig. 1B, 36 and Paragraph 48) and second insulating films (Fig. 1E, 50 and Paragraph 53) on opposed first and second surfaces, respectively, of a semiconductor wafer (Fig. 1B, 22 and Paragraph 45) having a plurality of semiconductor dice integrated therein, the semiconductor dice having die pads (Fig. 1B, 32) at the first surface;
opening vias (Fig. 1B, 38) to the semiconductor wafer through the first insulating film laminated on the first surface of the semiconductor wafer;
providing electrically conductive formations (Fig. 1C, 40 and Paragraph 49) towards said die pads, the electrically conductive formations extending in said vias; and
singulating the semiconductor wafer (Fig. 1E, and Paragraph 53) provided with said electrically conductive formations at separation lines (Fig. 1E, 26) between neighboring semiconductor dice in the plurality of semiconductor dice;
wherein singulating the semiconductor wafer produces individual semiconductor devices each having opposed first and second device surfaces with portions of the first and second insulating films laminated thereon as well as side surfaces of the singulated semiconductor wafer extending between the opposed first and second device surfaces,
the side surfaces left uncovered by said first and second insulating films (Fig. 1E, 36 and 50).
With respect to claim 2, Scanlan teaches providing the electrically conductive formations towards said die pads comprises growing electrically conductive material at the vias to the semiconductor wafer opened through the first insulating film laminated on the first surface of the semiconductor wafer (Paragraph 49).
With respect to claim 3, Scanlan teaches that providing the electrically conductive formations towards said die pads comprises providing contact pads (Fig. 1E, 44) on the first insulating film laminated on the first surface of the semiconductor wafer.
With respect to claim 4, Scanlan teaches that providing contact pads on the first insulating film laminated on the first surface of the semiconductor wafer comprises performing an electroplating deposition (Paragraph 49).
With respect to claim 8, Scanlan teaches that the side surfaces left uncovered by said first and second insulating films are made of semiconductor material of said wafer (Fig. 1E, 22).
With respect to claim 9, Scanlan teaches that each individual semiconductor device (Fig. 1E and Paragraph 53) is not encapsulated by a package material other than said first and second insulating films.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 5, 6 are rejected under 35 U.S.C. 103 as being unpatentable over Scanlan, in view of Chew (U.S. Pub #2022/0102254).
With respect to claim 5, Scanlan does not teach finishing the contact pads with a solderable protective electroless-nickel immersion-gold (ENIG) layer or electroless Ni – electroless Pd – immersion Au (ENEPIG) layer.
Chew teaches finishing contact pads with a solderable protective electroless-nickel immersion-gold (ENIG) layer or electroless Ni – electroless Pd – immersion Au (ENEPIG) layer (Paragraph 193).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to finish the contact pads of Scanlan with an ENIG or ENEPIG layer as taught by Chew in order to achieve the predictable result of surface treating the contacts pads (Paragraph 193).
With respect to claim 6, Scanlan does not teach one or both of the first and second insulating films is an Ajinomoto-Build-Up film.
Chew teaches an insulating film that can be formed as an Ajinomoto build-up film (Paragraph 211). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to form one or both of the first and second insulating films of Scanlan as an Ajinomoto-Build-Up film as taught by Chew in order to achieve the predictable result of providing an insulating film for incorporate contact pads in the structure.
Claims 7, 18-20, 23, and 24 are rejected under 35 U.S.C. 103 as being unpatentable over Scanlan, in view of De Cruz et al (U.S. Pub #2021/0175094).
With respect to claim 7, Scanlan teaches a method, comprising:
laminating first (Fig. 1B, 36 and Paragraph 48) and second insulating films (Fig. 1E, 50 and Paragraph 53) on opposed first and second surfaces, respectively, of a semiconductor wafer (Fig. 1B, 22 and Paragraph 45) having a plurality of semiconductor dice integrated therein, the semiconductor dice having die pads (Fig. 1B, 32) at the first surface;
opening vias (Fig. 1B, 38) to the semiconductor wafer through the first insulating film laminated on the first surface of the semiconductor wafer;
providing electrically conductive formations (Fig. 1C, 40 and Paragraph 49) towards said die pads, the electrically conductive formations extending in said vias; and
singulating the semiconductor wafer (Fig. 1E, and Paragraph 53) provided with said electrically conductive formations at separation lines (Fig. 1E, 26) between neighboring semiconductor dice in the plurality of semiconductor dice;
wherein singulating the semiconductor wafer produces individual semiconductor devices each having opposed first and second device surfaces with portions of the first and second insulating films laminated thereon as well as side surfaces of the singulated semiconductor wafer extending between the opposed first and second device surfaces,
the side surfaces left uncovered by said first and second insulating films (Fig. 1E, 36 and 50).
Scanlan does not teach
wherein singulating the semiconductor wafer at said separation lines between neighboring semiconductor dice comprises partially cutting the semiconductor wafer starting from the first surface of the semiconductor wafer having the first insulating film laminated thereon, wherein wettable flanks are formed at said selected ones of said electrically conductive formations in response to said partial cutting.
De Cruz teaches
wherein singulating the semiconductor wafer at said separation lines between neighboring semiconductor dice comprises partially cutting the semiconductor wafer starting from the first surface of the semiconductor wafer having the first insulating film laminated thereon (Fig. 7), wherein wettable flanks (Fig. 9, 193 and Paragraph 114) are formed at said selected ones of said electrically conductive formations in response to said partial cutting.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to partially cut the wafer of Scanlan to form wettable flanks as taught by De Cruz in order to allow the chip to be surface mounted to another device (Paragraph 2).
With respect to claim 18, Scanlan teaches providing the electrically conductive formations towards said die pads comprises growing electrically conductive material at the vias to the semiconductor wafer opened through the first insulating film laminated on the first surface of the semiconductor wafer (Paragraph 49).
With respect to claim 19, Scanlan teaches that providing the electrically conductive formations towards said die pads comprises providing contact pads (Fig. 1E, 44) on the first insulating film laminated on the first surface of the semiconductor wafer.
With respect to claim 20, Scanlan teaches that providing contact pads on the first insulating film laminated on the first surface of the semiconductor wafer comprises performing an electroplating deposition (Paragraph 49).
With respect to claim 23, Scanlan teaches that the side surfaces left uncovered by said first and second insulating films are made of semiconductor material of said wafer (Fig. 1E, 22).
With respect to claim 24, Scanlan teaches that each individual semiconductor device (Fig. 1E and Paragraph 53) is not encapsulated by a package material other than said first and second insulating films.
Claims 21 and 22 are rejected under 35 U.S.C. 103 as being unpatentable over Scanlan, in view of Chew (U.S. Pub #2022/0102254).
With respect to claim 21, Scanlan does not teach finishing the contact pads with a solderable protective electroless-nickel immersion-gold (ENIG) layer or electroless Ni – electroless Pd – immersion Au (ENEPIG) layer.
Chew teaches finishing contact pads with a solderable protective electroless-nickel immersion-gold (ENIG) layer or electroless Ni – electroless Pd – immersion Au (ENEPIG) layer (Paragraph 193).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to finish the contact pads of Scanlan with an ENIG or ENEPIG layer as taught by Chew in order to achieve the predictable result of surface treating the contacts pads (Paragraph 193).
With respect to claim 22, Scanlan does not teach one or both of the first and second insulating films is an Ajinomoto-Build-Up film.
Chew teaches an insulating film that can be formed as an Ajinomoto build-up film (Paragraph 211). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to form one or both of the first and second insulating films of Scanlan as an Ajinomoto-Build-Up film as taught by Chew in order to achieve the predictable result of providing an insulating film for incorporate contact pads in the structure.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BENJAMIN P SANDVIK whose telephone number is (571)272-8446. The examiner can normally be reached M-F: 10-6.
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/BENJAMIN P SANDVIK/Primary Examiner, Art Unit 2812
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