Prosecution Insights
Last updated: October 02, 2026
Application No. 18/615,032

SEMICONDUCTOR STRUCTURE AND FORMING METHOD THEREOF

Non-Final OA §102
Filed
Mar 25, 2024
Priority
Mar 28, 2023 — CN 202310317113.3
Examiner
KIM, SU C
Art Unit
Tech Center
Assignee
Semiconductor Manufacturing International Corporation
OA Round
1 (Non-Final)
78%
Grant Probability
Favorable
1-2
OA Rounds
3m
Est. Remaining
66%
With Interview

Examiner Intelligence

Grants 78% — above average
78%
Career Allowance Rate
718 granted / 923 resolved
+17.8% vs TC avg
Minimal -12% lift
Without
With
+-11.8%
Interview Lift
resolved cases with interview
Typical timeline
2y 9m
Avg Prosecution
35 currently pending
Career history
962
Total Applications
across all art units

Statute-Specific Performance

§101
0.2%
-39.8% vs TC avg
§103
59.5%
+19.5% vs TC avg
§102
23.8%
-16.2% vs TC avg
§112
6.4%
-33.6% vs TC avg
Black line = Tech Center average estimate • Based on career data from 923 resolved cases

Office Action

§102
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. Claim(s) 1-20 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Peng et al. (US 20230066230). Regarding claim 1, Peng discloses that a semiconductor structure, comprising: a base 110; a channel protrusion structure 120, suspended on the base 110, the channel protrusion structure comprising one or more channel layers arranged at intervals along a longitudinal direction (Fig. 1); a gate structure, spanning the channel protrusion structure and covering part of a top and part of a side wall of the channel protrusion structure, the gate structure further surrounding and covering the one or more channel layers, the gate structure located between the adjacent channel layers in the longitudinal direction and between the adjacent channel layers and the base serving as an inner gate structure, and at least one of the inner gate structure and the adjacent channel layers or the inner gate structure, the adjacent channel layers and the base forming an inner trench 130b; an inner spacer 130b, located in the inner trench 130b; and a source/drain doped layer 125 (para. 0017), located on the base on two sides of the gate structure and connected to two ends of the channel layer, the source/drain doped layer and the inner spacer having a gap 100 therebetween, and the gap being used as an air spacer 130b (para. 0018, Fig. 12-13). Reclaim 2, Peng discloses that the inner spacer fills part of space in the inner trench 130a; and the source/drain doped layer 125 seals the inner trench and forms the gap with the inner spacer (Fig. 12-13). Reclaim 3, Peng discloses that the inner spacer conformally covers an inner wall of the inner trench (Fig. 10). Reclaim 4, Peng discloses that along a direction perpendicular to a side wall of the inner gate structure, the inner gate structure between the inner trenches has a smaller width near a middle position than a top width and a bottom width, so that the inner trench has a larger lateral depth near the middle position than a lateral depth at a position near the channel layer (Fig. 16). Reclaim 5, Peng discloses that a side wall of the inner trench facing the inner gate structure is Σ-shaped or bowl-shaped (Fig. 16 & 10). Reclaim 6, Peng discloses that the inner spacer comprises a first inner spacer covering the inner wall of the inner trench, and a second inner spacer covering the first inner spacer, and there is an etch selectivity between the second inner spacer and the first inner spacer. Reclaim 7, Peng discloses that a thickness of the first inner spacer is 0.5 nm to 50 nm (para. 0059). Reclaim 8, Peng discloses that a material of the inner spacer comprises at least one of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide or silicon oxycarbonitride (para. 0018). Reclaim 9, Peng discloses that a shape of the gap comprises at least one of crescent, ellipsoidal, hemispherical or irregular shapes (Fig 1). Reclaim 10, Peng discloses that the base comprises a substrate and a bottom fin protruding from the substrate; the channel protrusion structure is suspended on the bottom fin; and the semiconductor structure further comprises: a first isolation layer, located on the substrate on a side of the bottom fin, the first isolation layer covering a side wall of the bottom fin (Fig. 1) Regarding claim 11, Peng discloses that forming method of a semiconductor structure, comprising: providing a base 100, one or more channel stacks sequentially stacked along a longitudinal direction being formed on the base, where each channel stack comprises a sacrificial layer 300a and a channel layer located on the sacrificial layer 300b (Fig. 3); forming a gate structure spanning the one or more channel stacks, the gate structure covering part of a top and part of a side wall of the one or more channel stacks (Fig. 5); removing the channel stack on two sides of the gate structure (Fig. 6); laterally removing, after removing the channel stack on the two sides of the gate structure, part of a width of the sacrificial layer along a direction perpendicular to a side wall of the gate structure to form an inner trench between the channel layers and/or between the channel layers and the base (Fig. 7); forming an inner spacer in the inner trench (Fig. 8); and forming a source/drain doped layer connected to two ends of the channel layer on the base on the two sides of the gate structure, the source/drain doped layer and the inner spacer having a gap therebetween, and the gap being used as an air spacer (Fig. 16). Reclaim 12, Peng discloses that the step of forming the inner spacer in the inner trench comprises: forming an inner spacer material layer covering the side wall and the top of the gate structure, the ends of the channel stack and the base on the sides of the gate structure, the inner spacer material layer further filling the inner trench; and removing the inner spacer material layer on the side wall and the top of the gate structure, the ends of the channel stack and the base on the sides of the gate structure, and removing part of the inner spacer material layer located in the inner trench, such that the inner spacer material layer fills part of space in the inner trench and the remaining inner spacer material layer serves as the inner spacer; and in the step of forming the source/drain doped layer, the source/drain doped layer seals the inner trench and forms the gap with the inner spacer (Fig. 8-12). Reclaim 13, Peng discloses that process of forming the inner spacer material layer comprises an atomic layer deposition process (Fig. 8-12). Reclaim 14, Peng discloses that in the step of removing part of the inner spacer material layer located in the inner trench, the inner spacer material layer conformally covers an inner wall of the inner trench (Fig. 8-12). Reclaim 15, Peng discloses that the step of forming the inner spacer material layer comprises: forming a first inner spacer material layer on the side wall and the top of the gate structure, the ends of the channel stack and the base on the sides of the gate structure, the first inner spacer material layer further covering an inner wall of the inner trench; and forming a second inner spacer material layer covering the first inner spacer material layer, the second inner spacer material layer further filling the inner trench, the first inner spacer material layer and the second inner spacer material layer forming the inner spacer material layer, and there being an etch selectivity between the second inner spacer material layer and the first inner spacer material layer; and the step of removing the inner spacer material layer on the side wall and the top of the gate structure, the ends of the channel stack and the base on the sides of the gate structure, and removing part of the inner spacer material layer located in the inner trench comprises: removing the second inner spacer material layer on the side wall and the top of the gate structure, the ends of the channel stack and the base on the sides of the gate structure, and removing part of the second inner spacer material layer located in the inner trench, such that the second inner spacer material layer fills part of the space in the inner trench; and removing, after the second inner spacer material layer fills part of the space in the inner trench, the first inner spacer material layer on the side wall and the top of the gate structure, the ends of the channel stack and the base on the sides of the gate structure, the remaining first inner spacer material layer and the second inner spacer material layer forming the inner spacer (Fig. 8-12). Reclaim 16. , Peng discloses that before forming the source/drain doped layer, the method further comprises: precleaning the base on the two sides of the gate structure and the ends of the channel stack, and during the precleaning process, removing the first inner spacer material layer on the side wall and the top of the gate structure, the ends of the channel stack and the base on the sides of the gate structure (Fig. 8-12). Reclaim 17, Peng discloses that a process of removing the second inner spacer material layer on the side wall and the top of the gate structure, the ends of the channel stack and the base on the sides of the gate structure comprises an anisotropic plasma etching process, and a process of removing part of the second inner spacer material layer located in the inner trench comprises an isotropic plasma etching process; and a process of removing the first inner spacer material layer on the side wall and the top of the gate structure, the ends of the channel stack and the base on the sides of the gate structure comprises one or two of a wet etching process or a chemical vapor etching process (Fig. 8-12). Reclaim 18, Peng discloses that in the process of removing part of the second inner spacer material layer located in the inner trench, the etch selectivity between the second inner spacer material layer and the first inner spacer material layer is larger than 80; and in the process of removing the first inner spacer material layer on the side wall and the top of the gate structure, the ends of the channel stack and the base on the sides of the gate structure, the etch selectivity between the first inner spacer material layer and the second inner spacer material layer is larger than 100 (Fig. 8-12). Reclaim 19, Peng discloses that in the step of laterally removing part of the width of the sacrificial layer along the direction perpendicular to the side wall of the gate structure to form the inner trench between at least one of the channel layers or the channel layers and the base, the remaining sacrificial layer between the inner trenches has a smaller width near a middle position than a top width and a bottom width, SO that the inner trench has a larger lateral depth near the middle position than a lateral depth at a position near the channel layer (Fig. 8-12). Reclaim 20, Peng discloses that a process of laterally removing part of the width of the sacrificial layer comprises: one or two of a chemical vapor etching process and a plasma etching process (Fig. 8-12). Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to SU C KIM whose telephone number is (571)272-5972. The examiner can normally be reached M-F 9:00 to 5:00. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Dale Page can be reached at 571-270-7877. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /SU C KIM/Primary Examiner, Art Unit 2899
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Prosecution Timeline

Mar 25, 2024
Application Filed
Aug 20, 2026
Non-Final Rejection mailed — §102 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
78%
Grant Probability
66%
With Interview (-11.8%)
2y 9m (~3m remaining)
Median Time to Grant
Low
PTA Risk
Based on 923 resolved cases by this examiner. Grant probability derived from career allowance rate.

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