DETAILED ACTION
Specification
1. The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Claim Objections
2. Claims 8 - 10, 18, 19are objected to because of the following informalities:
In claims 8, 9, 18, 19, line 1, “in plan view” should be changed to “in a plan view”
In claim 10, line 1, “the second sealing member” should be changed to “a second sealing member” because it lacks of antecedent basis.
Appropriate correction is required.
Claim Rejections - 35 USC § 102
3. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
4. Claim(s) 1, 3 – 5, 7 – 11, 13 – 15, 17 - 19 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Wu et al. (20210335726).
With regard to claim 1, Wu et al. disclose a semiconductor package (for example, see figs. 1 – 3), comprising:
a substrate structure (referred to as “SUB” by examiner’s annotation shown in fig. 2 below) having a first upper surface (a top surface) and a first lower surface (a bottom surface) opposite to the first upper surface (the top surface),
the substrate structure (SUB) having at least one bridge chip (a component die 120 functions as bridge chip; for example, paragraphs [0038], [0039]) therein;
a semiconductor memory device (514) on the first upper surface of the substrate structure (SUB) and electrically connected to the at least one bridge chip (120); and
a semiconductor logic device (512) on the first upper surface of the substrate structure (SUB) and spaced apart from the semiconductor memory device (514), and the semiconductor logic device (512) electrically connected to the bridge chip (120; for example, see paragraph [0054]), wherein the semiconductor memory device (514) includes a redistribution wiring layer (conductive lines 110 and conductive vias 112, together, form the metallization pattern for redistribution wiring layer 90, 92, fig. 1, or fig. 2 as shown below, functions as a redistribution wiring layer) having a second upper surface (referred to as “92A” by examiner’s annotation shown in fig. 2 below) and a second lower surface (referred to as “92B” by examiner’s annotation shown in fig. 2 below) opposite to the second upper surface,
the redistribution wiring layer (90, 92) on the substrate structure (SUB), and the redistribution wiring layer (90, 92) having a plurality of redistribution wirings (110), a plurality of buffer dies (referred to as “514A” by examiner’s annotation shown in fig. 2 below) on the second upper surface (the top surface) of the redistribution wiring layer (92) and electrically connected to the at least one bridge chip (120; for example, see paragraph [0054]) through the plurality of redistribution wirings (110), and a plurality of semiconductor chips (referred to as “514B” by examiner’s annotation shown in fig. 2 below; wherein the semiconductor chips 514B are ones of semiconductor chips 514) sequentially stacked on each of the plurality of buffer dies (514B) and electrically connected to the plurality of buffer dies (514A; the chip 120 provide electrical connection between semiconductor chips 514 and the logic die 512. Therefore, a plurality of semiconductor chips 514B electrically connected to the plurality of buffer dies 514A and the redistribution layer 90, 92).
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With regard to claim 3, Wu et al. disclose the redistribution wiring layer (90, 92) includes: a plurality of first redistribution pads (conductive redistribution portions 106 functions as first redistribution pads) electrically connected to the plurality of redistribution wirings (110) and exposed from the second upper surface (92A); and a plurality of second redistribution pads (conductive redistribution portions 112 functions as second redistribution pads) electrically connected to the plurality of redistribution wirings (110) and exposed from the second lower surface (92B).
With regard to claim 4, Wu et al. disclose the redistribution wiring layer further includes a plurality of solder bumps (bumps 390, fig. 1 functions as solder bumps) on (on the bottom surface) the plurality of second redistribution pads respectively.
With regard to claim 5, Wu et al. disclose each of the plurality of buffer dies (514A) includes a plurality of lower buffer pads (186) that are exposed toward the redistribution wiring layer (90, 92), and wherein the plurality of lower buffer pads (186) are bonded to the plurality of first redistribution pads (106) and are electrically connected to the plurality of first redistribution pads (106).
With regard to claim 7, Wu et al. disclose the substrate structure includes a first number (for example, a first number is 1) of the at least one bridge chip (120), the semiconductor memory device includes a second number (for example, a second number is 2) of the plurality of buffer dies, and the first number is smaller than the second number.
With regard to claim 8, Wu et al. disclose wherein in a plan view (fig. 3), at least a portion of the semiconductor logic device (512) overlaps at least a portion of the at least one bridge chip (120).
With regard to claim 9, Wu et al. disclose wherein in a plan view (fig. 3), at least a portion of the semiconductor memory device (514) overlaps at least a portion of the at least one bridge chip (120).
With regard to claim 10, Wu et al. disclose the substrate structure includes: a semiconductor substrate (a silicon substrate 300; for example see paragraph [0069]), and the at least one bridge chip (120) is on the semiconductor substrate (300); a plurality of conductive structures (390) on the semiconductor substrate (300) and spaced apart from the at least one bridge chip (120); a sealing member (referred to as “380A1” by examiner’s annotation shown in fig. 1 below; wherein the encapsulant 380 may be formed of a molding compound, epoxy functions as a sealing member) covering (covering the bottom surface) the at least one bridge chip (120) and the plurality of conductive structures (390) on the semiconductor substrate (300); first external connection pads (referred to as “620A1” by examiner’s annotation shown in fig. 1 below) exposed from the sealing member (380A1) and electrically connected to the at least one bridge chip (120); and second external connection pads (referred to as “620A2” by examiner’s annotation shown in fig. 1 below) exposed from the second sealing member (referred to as “380A2” by examiner’s annotation shown in fig. 1 below; wherein the encapsulant 380 may be formed of a molding compound, epoxy functions as a sealing member) and electrically connected to the plurality of conductive structures (390).
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With regard to claim 11, Wu et al. disclose a semiconductor package (for example, see figs. 1 – 3), comprising:
a substrate structure (referred to as “SUB” by examiner’s annotation shown in fig. 2 below) having a first upper surface (a top surface) and a first lower surface (a bottom surface) opposite to the first upper surface (the top surface),
the substrate structure (SUB) having at least one bridge chip (a component die 120 functions as bridge chip; for example, paragraphs [0038], [0039]) therein;
a semiconductor logic device (512) on the first upper surface of the substrate structure (SUB) and electrically connected to the at least one bridge chip (120); and
a semiconductor memory device (514) on the first upper surface of the substrate structure (SUB) and spaced apart from the semiconductor logic device (512), and he semiconductor memory device (514) electrically connected to the semiconductor logic device (512) through the bridge chip (120; for example, see paragraph [0054]), wherein the semiconductor memory device (514) includes a redistribution wiring layer (conductive lines 110 and conductive vias 112, together, form the metallization pattern for redistribution wiring layer 90, 92, fig. 1, or fig. 2 as shown below, functions as a redistribution wiring layer) having a second upper surface (referred to as “92A” by examiner’s annotation shown in fig. 2 below) and a second lower surface (referred to as “92B” by examiner’s annotation shown in fig. 2 below) opposite to the second upper surface having a plurality of redistribution wirings (110), a plurality of buffer dies (referred to as “514A” by examiner’s annotation shown in fig. 2 below) on the second upper surface (the top surface) of the redistribution wiring layer (92) and electrically connected to the at least one bridge chip (120; for example, see paragraph [0054]) through the plurality of redistribution wirings (110), and
a plurality of semiconductor chips (referred to as “514B” by examiner’s annotation shown in fig. 2 below; wherein the semiconductor chips 514B are ones of semiconductor chips 514) sequentially stacked on each of the plurality of buffer dies (514B) and electrically connected to the plurality of buffer dies (514A; the chip 120 provide electrical connection between semiconductor chips 514 and the logic die 512. Therefore, a plurality of semiconductor chips 514B electrically connected to the plurality of buffer dies 514A and the redistribution layer 90, 92).
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With regard to claim 13, Wu et al. disclose the redistribution wiring layer (90, 92) includes: a plurality of first redistribution pads (conductive redistribution portions 106 functions as first redistribution pads) electrically connected to the plurality of redistribution wirings (110) and exposed from the second upper surface (92A); and a plurality of second redistribution pads (conductive redistribution portions 112 functions as second redistribution pads) electrically connected to the plurality of redistribution wirings (110) and exposed from the second lower surface (92B).
With regard to claim 14, Wu et al. disclose the redistribution wiring layer further includes a plurality of solder bumps (bumps 390, fig. 1 functions as solder bumps) on (on the bottom surface) the plurality of second redistribution pads respectively.
With regard to claim 15, Wu et al. disclose each of the plurality of buffer dies (514A) includes a plurality of lower buffer pads (186) that are exposed toward the redistribution wiring layer (90, 92), and wherein the plurality of lower buffer pads (186) are bonded to the plurality of first redistribution pads (106) and are electrically connected to the plurality of first redistribution pads (106).
With regard to claim 17, Wu et al. disclose the substrate structure includes a first number (for example, a first number is 1) of the at least one bridge chip (120), the semiconductor memory device includes a second number (for example, a second number is 2) of the plurality of buffer dies, and the first number is smaller than the second number.
With regard to claim 18, Wu et al. disclose wherein in a plan view (fig. 3), at least a portion of the semiconductor logic device (512) overlaps at least a portion of the at least one bridge chip (120).
With regard to claim 19, Wu et al. disclose wherein in a plan view (fig. 3), at least a portion of the semiconductor memory device (514) overlaps at least a portion of the at least one bridge chip (120).
Claim Rejections - 35 USC § 103
5. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
6. Claims 2, 12, 20 are rejected under 35 U.S.C. 103 as being unpatentable over Wu et al. (20210335726) in view of Youn et al. (8659136).
With regard to claims 2, 12, Wu et al. disclose a sealing member (a material 610 inherently functions as a sealing member) that covers the plurality of buffer dies (514A) on the redistribution wiring layer (92).
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Wu et al. do not clearly disclose the sealing member that covers the plurality of semiconductor chips.
However, Youn et al. disclose the sealing member (a molding 4650 functioning as the sealing member) that covers the plurality of semiconductor chips (4200 – 4500). (for example, see fig. 5C).
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Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the Wu et al.’s device to have the sealing member that covers the plurality of semiconductor chips as taught by Youn et al. in order to minimize the signal interference for enhancing a stability operation of the semiconductor device, as is known to one of ordinary skill in the art.
With regard to claim 20, Wu et al. disclose a semiconductor package (for example, see figs. 1 – 3), comprising:
a substrate structure (referred to as “SUB” by examiner’s annotation shown in fig. 2 below) having a first upper surface (a top surface) and a first lower surface (a bottom surface) opposite to the first upper surface (the top surface),
the substrate structure (SUB) having a bridge chip (a component die 120 functions as bridge chip; for example, paragraphs [0038], [0039]) therein;
a semiconductor memory device (514) on the first upper surface of the substrate structure (SUB); and
a semiconductor logic device (512) on the first upper surface of the substrate structure (SUB) and spaced apart from the semiconductor memory device (514), and the semiconductor logic device (512) electrically connected to the semiconductor memory device (514) through the bridge chip (120; for example, see paragraph [0054]), wherein the semiconductor memory device (514) includes a redistribution wiring layer (conductive lines 110 and conductive vias 112, together, form the metallization pattern for redistribution wiring layer 90, 92, fig. 1, or fig. 2 as shown below, functions as a redistribution wiring layer) having a second upper surface (referred to as “92A” by examiner’s annotation shown in fig. 2 below) and a second lower surface (referred to as “92B” by examiner’s annotation shown in fig. 2 below) opposite to the second upper surface,
the redistribution wiring layer (90, 92) on the substrate structure (SUB), and the redistribution wiring layer (90, 92) having a plurality of redistribution wirings (110), a plurality of buffer dies (referred to as “514A” by examiner’s annotation shown in fig. 2 below) on the second upper surface (the top surface) of the redistribution wiring layer (92) and electrically connected to the bridge chip (120; for example, see paragraph [0054]) through the plurality of redistribution wirings (110), and a plurality of semiconductor chips (referred to as “514B” by examiner’s annotation shown in fig. 2 below; wherein the semiconductor chips 514B are ones of semiconductor chips 514) sequentially stacked on each of the plurality of buffer dies (514B) and electrically connected to the plurality of buffer dies (514A; the chip 120 provide electrical connection between semiconductor chips 514 and the logic die 512. Therefore, a plurality of semiconductor chips 514B electrically connected to the plurality of buffer dies 514A and the redistribution layer 90, 92);
a sealing member (a material 610 inherently functions as a sealing member) that covers the plurality of buffer dies (514A) on the redistribution wiring layer (92).
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Wu et al. do not clearly disclose the sealing member that covers the plurality of semiconductor chips.
However, Youn et al. disclose the sealing member (a molding 4650 functioning as the sealing member) that covers the plurality of semiconductor chips (4200 – 4500). (for example, see fig. 5C).
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Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the Wu et al.’s device to have the sealing member that covers the plurality of semiconductor chips as taught by Youn et al. in order to minimize the signal interference for enhancing a stability operation of the semiconductor device, as is known to one of ordinary skill in the art.
7. Claims 6, 16 are rejected under 35 U.S.C. 103 as being unpatentable over Wu et al. (20210335726) in view of Leow et al. (12677696).
With regard to claims 6, 16, Wu et al. do not clearly disclose each of the plurality of buffer dies and the plurality of semiconductor chips include a high bandwidth memory device.
However, Leow et al. disclose each of the plurality of buffer dies and the plurality of semiconductor chips include a high bandwidth memory device. each of the plurality of buffer dies (125d, 125c) and the plurality of semiconductor chips (125a, 125b) include a high bandwidth memory device (for example, column 2, lines 36 – 46, fig. 1A).
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Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the Wu et al.’s device to have each of the plurality of buffer dies and the plurality of semiconductor chips include a high bandwidth memory device as taught by Leow et al. in order to enhance a high speed efficiency of the semiconductor device for enhancing a stability operation of the semiconductor device, as is known to one of ordinary skill in the art.
Conclusion
8. Any inquiry concerning this communication or earlier communications from the examiner should be directed to TAN N TRAN whose telephone number is (571) 272 - 1923. The examiner can normally be reached on 8:30-5:00PM.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Davienne Monbleau can be reached on (571) 272-1945. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/TAN N TRAN/
Primary Examiner, Art Unit 2812
Prosecution Insights