DETAILED ACTION
The present application is being examined under the pre-AIA first to invent provisions.
Status of Claims
The status of the claims as amended/presented in the response received 4/9/2026, is as follows:
- Claims 1-4, 6-9, 16-21 are pending.
- Claims 1, 6, 7, 9 and 16 have been amended.
- Claims 5 and 10-15 have been canceled.
- Claims 3, 6, 18 and 21 are withdrawn from consideration.
Response to Arguments
Applicant’s arguments with respect to claim 1 as amended has been considered but are moot because the new ground of rejection. The examiner notes that the previous interpretation of the prior art of record (Ohtsuka) fails to teach all elements in amended claim 1. Please refer to the new interpretation of the prior art for any teaching or matter specifically challenged in the argument.
Claim Objections
Claim 16 is objected to because of the following informalities:
In line 17 of claim 16, the recitation “of electrically conductive trace” appears to be missing the article “the”.
For the purpose of examination, the examiner interprets the claim as reciting: “of the electrically conductive trace”.
Claims 17, 19 and 20 are objected as they inherit the deficiencies of claim 16 noted above.
Appropriate correction is required.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1, 4 and 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over the Japanese Patent Publication JP-4200358 B2 (Ohtsuka hereafter - a copy of the foreign document is provided with this Office Action), in view of the US Patent US 11,340,318 by Uemura et al., (Uemura hereafter).
Regarding claim 1, Ohtsuka teaches in Figure 1-3, device, comprising:
an insulating encapsulation (resin 18, see paragraph 0010, line 7 in the provided translation) encapsulating a semiconductor substrate (23) encapsulated within resin 18 as illustrated in Figure 2), wherein the semiconductor die has integrated therein a Hall current sensor (1) configured to measure an electric current flowing adjacent an active surface of the semiconductor die (current flowing through portions 3 and 4);
an electrically conductive trace (13+15+14) embedded in the insulating encapsulation, the electrically conductive trace having opposed ends (end of portion 13 contacting formation 3 and facing away from portion 14; end of portion 14 contacting formation 4 and facing away from portion 13) providing therebetween a current flow path adjacent the active surface of the semiconductor die;
first electrically conductive formations (3 and 4) through the insulating encapsulation towards the opposed ends of the electrically conductive trace embedded in the insulating encapsulation, the first electrically conductive formations configured to cause an electrical current subject to measurement to flow in said current flow path adjacent the active surface of the semiconductor die (in the manner explained for example, in paragraph 0023 of the provided translation); and
second electrically conductive formations (6+36, 8+38, 9+39 and 7+37) through the insulating encapsulation towards the active surface of the semiconductor die, the second electrically conductive formations configured to activate the Hall current sensor integrated in the semiconductor die (see paragraph 0023 in the provided translation);
wherein the electrically conductive trace embedded in the insulating encapsulation has an intermediate portion between said opposed ends (portion where 13 expands into 15, as illustrated in annotated Figure 1 below); and
wherein the intermediate portion has a width perpendicular to the flow of the electrical current that is wider than a width perpendicular to the flow of the electrical current at the opposed ends (as illustrated in annotated Figure 1 below).
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Annotated Figure 1
Although Ohtsuka mentions the Hall current sensor (1) is formed on a semiconductor substrate (23), Ohtsuka doesn’t explicitly mention the semiconductor substrate (23) is a die.
Uemura teaches in Figures 1 and 12, a sensor comprising a semiconductor die (hall IC 120), wherein the semiconductor die has integrated therein a hall sensor (121), the sensor being encapsulated by an insulating resin.
It would have been obvious to a person having ordinary skill in the art before the invention was effectively filed, to apply the teaching of Hall sensors disposed on a semiconductor die as taught by Uemura, and dispose the Hall current sensor (1) on a semiconductor die, as it would allow for the device to be manufactured with high precision, while being compact and portable.
Regarding claim 4, Ohtsuka shows in Figures 1-3, the device of claim 1, wherein the electrically conductive trace (13+15+14) embedded in the insulating encapsulation (8) has a slab shape (the trace is flat and elongated as a slab at least in portion 15).
Regarding claim 9, Ohtsuka teaches in Figures 1-3, the device of claim 1, further comprising:
an electrical current subject to measurement (current Is2 shown by the arrow in Figure 1) that is applied across the first electrically conductive formations (3 and 4), wherein the current subject to measurement flows in said current flow path adjacent the active surface of the semiconductor die; and
signals (signals provided by leads 6-9) applied to the second electrically conductive formations are configured to activate the Hall current sensor (Hall sensor 1) to measure the electrical current flowing in said current flow path adjacent the active surface of the semiconductor die (see paragraph 0023 in the provided translation).
Claim(s) 2 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ohtsuka in view of Uemura and further in view of the US Patent US 8,400,139 by Ausserlechner et al., (Ausserlechner hereafter).
Regarding claims 2, Ohtsuka teaches in Figures 1-3, the device of claim 1, further comprising an insulating film (32) laminated on the active surface of the semiconductor die (see paragraph 0024, lines 15-18) wherein the second electrically conductive formations comprise electrically conductive material (material of electrically conductive lines 36, 38, 39 or 37) through the insulating encapsulation. Ohtsuka however, fails to teach the use of vias opened through the insulating film (Ohtsuka uses bond wires 36, 38, 39, 37 that connect to the exterior of the encapsulation through leadframe terminals 6, 8, 9, 7).
Ausserlechner teaches in Figure 6A, a sensor chip (130) encapsulated on insulating material and including an insulating layer (layer of PCB material 610). The sensor chip including conductive formations (112) made of conductive material at vias (614) opened through the insulating layer.
It would have been obvious to a person having ordinary skill in the art before the invention was effectively filed, to apply the teaching of vias as connecting elements as taught by Ausserlechner, in the device/system/method of Ohtsuka in view of Uemura, in order to eliminate the need to solder/attach the bond wire and prevent any sources of failure (e.g., misalignment and/or poor bonding, while using a another connector (i.e, via) which can allow for high density integration of interconnects, see MPEP 2144.06 and/or 2144.07.
Allowable Subject Matter
Claims 7-8 and 16-17 and 19-20 are allowed. The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 7, the prior art of record doesn’t teach alone or in combination device comprising a third body of encapsulating material covering the second body; wherein the electrically conductive trace is positioned between the third body and second body; wherein portions of the first electrically conductive formations extend through the third body; and
wherein further portions of the second electrically conductive formations extend through the third body, in combination with all other elements recited in the claim and claims it depends from.
Claim 8 is allowed as it further limits objected claim 7.
Regarding claim 16, the prior art of record doesn’t teach alone or in combination device comprising device wherein the first electrically conductive formations comprise studs located at opposed ends of the electrically conductive trace, said surface being parallel to the first and second surfaces of the insulating encapsulation, and having an end exposed at one of the first and second surfaces of the insulating encapsulation, in combination with all other elements recited in the claim and claims it depends from.
Claims 17 and 19-20 are allowed as it further limits objected claim 16.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
- The US Patent US 7,166,807 by Gagnon et al.
- The US Patent Application Publication PGPub 2024/0096767 by Sung et al.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Richard Isla whose telephone number is (571)272-5056. The examiner can normally be reached Monday-Friday 9a - 5:30p.
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/RICHARD ISLA/Primary Patent Examiner, Art Unit 2858 June 11, 2026
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