DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Group I claims 1-9 and Species B, directed to Figures 3+4, readable on claims 1-2, 4-5, 7-9, as well as newly presented claims 16-17 and 19-20, in the reply filed on 12/11/2025 is acknowledged. In the reply, claims 3, 6, 18-21 have been withdrawn as being directed to an unelected Group and/or Species. Claims 10-15 have been canceled.
Status of Claims
The status of the claims as amended/presented in the response received 12/11/2025, is as follows:
- Claims 1-9, 16-21 are pending.
- Claims 10-15 have been canceled.
- Claims 3, 6, 18 and 21 are withdrawn from consideration.
Priority
Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d). Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 4/5/2024 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Objections
Claims 1-2, 4-5 and 7-9 are objected to because of the following informalities:
In claim 1, line 2, in the recitation “an insulating encapsulation encapsulates a semiconductor die”, the word “encapsulates” appears to be a typographical error.
For the purpose of examination, the examiner considers the recitation: “an insulating encapsulation encapsulating a semiconductor die”
Claims 2, 4-5 and 7-9 are also objected as they inherit the deficiencies noted above.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
Claim 9 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 9 recites the limitation “signals applied to the second electrically conductive formations of the Hall current sensor” in line 5. There is insufficient antecedent basis for this limitation in the claim.
For the purpose of examination, the examiner considers the recitation:
“signals applied to the second electrically conductive formations configured to activate the Hall current sensor”
Appropriate correction is required.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1, 4-5, 9, 16 and 19-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over the Japanese Patent Publication JP-4200358 B2 (Ohtsuka hereafter - a copy of the foreign document is provided with this Office Action), in view of the US Patent US 11,340,318 by Uemura et al., (Uemura hereafter).
Regarding claim 1, Ohtsuka teaches in Figure 1-3, device, comprising:
an insulating encapsulation (resin 18, see paragraph 0010, line 7 in the provided translation) encapsulating a semiconductor substrate (23) encapsulated within resin 18 as illustrated in Figure 2), wherein the semiconductor die has integrated therein a Hall current sensor (1) configured to measure an electric current flowing adjacent an active surface of the semiconductor die (current flowing through portions 3 and 4);
an electrically conductive trace (15) embedded in the insulating encapsulation, the electrically conductive trace having opposed ends (ends “A” and “B”, connected to line 13 and 14 respectively, see annotated Figure 3 below, provided in an effort to clarify the examiner’s position) providing therebetween a current flow path adjacent the active surface of the semiconductor die;
first electrically conductive formations (13+3 and 14+4) through the insulating encapsulation towards the opposed ends of the electrically conductive trace embedded in the insulating encapsulation, the first electrically conductive formations configured to cause an electrical current subject to measurement to flow in said current flow path adjacent the active surface of the semiconductor die (in the manner explained for example, in paragraph 0023 of the provided translation); and
second electrically conductive formations (6+36, 8+38, 9+39 and 7+37) through the insulating encapsulation towards the active surface of the semiconductor die, the second electrically conductive formations configured to activate the Hall current sensor integrated in the semiconductor die (see paragraph 0023 in the provided translation).
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Annotated Figure 3, showing opposite ends of electrically
conductive trace 15 and the width of the intermediate portion
Although Ohtsuka mentions the Hall current sensor (1) is formed on a semiconductor substrate (23), Ohtsuka doesn’t explicitly mention the semiconductor substrate (23) is a die.
Uemura teaches in Figures 1 and 12, a sensor comprising a semiconductor die (hall IC 120), wherein the semiconductor die has integrated therein a hall sensor (121), the sensor being encapsulated by an insulating resin.
It would have been obvious to a person having ordinary skill in the art before the invention was effectively filed, to apply the teaching of Hall sensors disposed on a semiconductor die as taught by Uemura, and dispose the Hall current sensor (1) on a semiconductor die, as it would allow for the device to be manufactured with high precision, while being compact and portable.
Regarding claim 4, Ohtsuka shows in Figures 1-3, the device of claim 1, wherein the electrically conductive trace (15) embedded in the insulating encapsulation (8) has a slab shape (the trace is flat and elongated as a slab).
Regarding claim 5, Ohtsuka teaches in Figures 1-3, the device of claim 1, wherein the electrically conductive trace (15) embedded in the insulating encapsulation has an intermediate portion between said opposed ends, and wherein the intermediate portion (please see annotated Figure 3 above) is wider than the opposed ends.
Regarding claim 9, Ohtsuka teaches in Figures 1-3, the device of claim 1, further comprising:
an electrical current (current Is shown by the arrow in Figure 1) subject to measurement that is applied across the first electrically conductive formations (13+3 and 14+4), wherein the current subject to measurement flows in said current flow path adjacent the active surface of the semiconductor die; and
signals (signals provided by leads 6-9) applied to the second electrically conductive formations configured to activate the Hall current sensor (Hall sensor 1) integrated in the semiconductor die, wherein said signals are configured to activate the Hall current sensor to measure the electrical current flowing in said current flow path adjacent the active surface of the semiconductor die (see paragraph 0023 in the provided translation).
Regarding claim 16, Ohtsuka teaches in Figures 1-3, device, comprising:
an insulating encapsulation (resin 18, see paragraph 0010, line 7 in the provided translation) comprising a molding compound (resin) that encapsulates a semiconductor substrate (23), wherein the semiconductor die has integrated therein a Hall current sensor (1) configured to measure an electric current flowing adjacent an active surface of the semiconductor die (in the manner explained in paragraph 0023 of the provided translation);
an electrically conductive trace (15) embedded in the insulating encapsulation (see Figure 2), the electrically conductive trace having opposed ends (See annotated Figure 3 below) providing therebetween a current flow path adjacent the active surface of the semiconductor die (23);
first electrically conductive formations (3+13 and 14+4) through the insulating encapsulation towards the opposed ends of the electrically conductive trace embedded in the insulating encapsulation, the first electrically conductive formations configured to cause an electrical current subject to measurement (current Is flowing through 3+13, 15, 14+4) to flow in said current flow path adjacent the active surface of the semiconductor die;
wherein the first electrically conductive formations comprise studs (13 and 14) located at opposed ends of electrically conductive trace; and
second electrically conductive formations (6+36, 8+38, 9+39 and 7+37) through the insulating encapsulation towards the active surface of the semiconductor die, the second electrically conductive formations configured to activate the Hall current sensor integrated in the semiconductor die (see paragraph 0023 in the provided translation);
wherein the second electrically conductive formations comprise traces at the active surface of the semiconductor die (for example, the unlabeled traces connecting portion 19 to portion 24, or portion 21 to portion 29, also shown in Figure 7) and embedded in a layer of the insulating encapsulation between the electrically conductive trace and the active surface of the semiconductor die (see Figure 2).
Although Ohtsuka mentions the Hall current sensor (1) is formed on a semiconductor substrate (23), Ohtsuka doesn’t explicitly mention the semiconductor substrate (23) is a die.
Uemura teaches in Figures 1 and 12, a sensor comprising a semiconductor die (hall IC 120), wherein the semiconductor die has integrated therein a hall sensor (121), the sensor being encapsulated by an insulating resin.
It would have been obvious to a person having ordinary skill in the art before the invention was effectively filed, to apply the teaching of Hall sensors disposed on a semiconductor die as taught by Uemura, and dispose the Hall current sensor (1) on a semiconductor die, as it would allow for the device to be manufactured with high precision, while being compact and portable.
Regarding claim 19, Ohtsuka shows in Figure 2, the device of claim 16, wherein the electrically conductive trace (15) embedded in the insulating encapsulation (8) has a slab shape (the trace is flat and elongated).
Regarding claim 20, Ohtsuka teaches in Figure 1, the device of claim 16, wherein the electrically conductive trace (15) embedded in the insulating encapsulation (18) has an intermediate portion (shown in annotated Figure 3 above) between said opposed ends, and wherein the intermediate portion is wider than the opposed ends.
Claim(s) 2 and 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ohtsuka in view of Uemura and further in view of the US Patent US 8,400,139 by Ausserlechner et al., (Ausserlechner hereafter).
Regarding claims 2 and 17, Ohtsuka teaches in Figures 1-3, the device of claim 1 or 16, further comprising an insulating film (32) laminated on the active surface of the semiconductor die (see paragraph 0024, lines 15-18) wherein the second electrically conductive formations comprise electrically conductive material (material of electrically conductive lines 36, 38, 39 or 37) through the insulating encapsulation. Ohtsuka however, fails to teach the use of vias opened through the insulating film (Ohtsuka uses bond wires 36, 38, 39, 37 that connect to the exterior of the encapsulation through leadframe terminals 6, 8, 9, 7).
Ausserlechner teaches in Figure 6A, a sensor chip (130) encapsulated on insulating material and including an insulating layer (layer of PCB material 610). The sensor chip including conductive formations (112) made of conductive material at vias (614) opened through the insulating layer.
It would have been obvious to a person having ordinary skill in the art before the invention was effectively filed, to apply the teaching of vias as connecting elements as taught by Ausserlechner, in the device/system/method of Ohtsuka in view of Uemura, in order to eliminate the need to solder/attach the bond wire and prevent any sources of failure (e.g., misalignment and/or poor bonding, while using a another connector (i.e, via) which can allow for high density integration of interconnects, see MPEP 2144.06 and/or 2144.07.
Allowable Subject Matter
Claims 7-8 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding claim 7, the prior art of record doesn’t teach alone or in combination device comprising a third body of encapsulating material covering the second body; wherein the electrically conductive trace is positioned between the third body and second body; wherein portions of the first electrically conductive formations extend through the third body; and
wherein further portions of the second electrically conductive formations extend through the third body, in combination with all other elements recited in the claim and claims it depends from.
Claim 8 is objected as it further limits objected claim 7.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
- The US Patent US 9,372,240 by Tamura et al., directed to current sensors positioned within dies and configured to be placed in close proximity to a current carrying conductor. See figure below:
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- The Japanese Patent Publication JP 4146625, directed to encapsulated hall sensors including flux enhancing means positioned in close proximity to the sensors. A copy of the foreign document and partial translation are provided with this Office Action. See below:
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- The US Patent Application Publication PGPub 2007/0096717 by Ishihara et al., directed to current sensors including encapsulated means for enhancing flux distribution. See figure below:
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/RICHARD ISLA/ Primary Patent Examiner, Art Unit 2858 January 7, 2026