Prosecution Insights
Last updated: October 02, 2026
Application No. 18/615,263

DISPLAY PANEL AND DISPLAY DEVICE

Non-Final OA §102
Filed
Mar 25, 2024
Priority
Dec 18, 2023 — CN 202311747232.9
Examiner
DIAZ, JOSE R
Art Unit
Tech Center
Assignee
Wuhan Tianma Micro-Electronics Co., Ltd.
OA Round
1 (Non-Final)
87%
Grant Probability
Favorable
1-2
OA Rounds
0m
Est. Remaining
95%
With Interview

Examiner Intelligence

Grants 87% — above average
87%
Career Allowance Rate
841 granted / 967 resolved
+27.0% vs TC avg
Moderate +8% lift
Without
With
+7.9%
Interview Lift
resolved cases with interview
Typical timeline
2y 5m
Avg Prosecution
21 currently pending
Career history
977
Total Applications
across all art units

Statute-Specific Performance

§101
0.4%
-39.6% vs TC avg
§103
42.2%
+2.2% vs TC avg
§102
33.8%
-6.2% vs TC avg
§112
8.3%
-31.7% vs TC avg
Black line = Tech Center average estimate • Based on career data from 967 resolved cases

Office Action

§102
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claims 1, 3 and 22 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Wu et al. (US2022/0171225). Regarding claim 1, Wu discloses a display panel, comprising: a substrate (S) [Fig. 11, annotated below]; at least one light-emitting element (72) [Fig. 11]; and sensing elements (20/10/21/22) [Fig. 11], wherein the sensing elements and the at least one light-emitting element are located at a same side of the substrate (S) [Fig. 11, annotated below]; the sensing elements comprise at least one first sensing element each configured to recognize fingerprint (10), and further comprises at least one second sensing element (20) [AltContent: arrow][AltContent: textbox (T)][AltContent: textbox (W)][AltContent: arrow][AltContent: textbox (LED)][AltContent: arrow][AltContent: arrow][AltContent: textbox (S)] PNG media_image1.png 336 676 media_image1.png Greyscale Regarding claim 3, Wu discloses: an array layer (71) [Fig. 1 and 11]; and a light-emitting element layer (72) located at a side of the array layer away from the substrate (S) [Fig. 1 and 11 (annotated above)], wherein the array layer (71) comprises at least one pixel circuit (T), wherein one of the at least one pixel circuit (T) is electrically connected to one of the at least one light-emitting element (LED), and the light-emitting element layer (72) comprises the at least one light-emitting element (LED) [Fig. 11, annotated above]; and wherein the sensing elements (W) are located between the array layer (71) and the light-emitting element layer (72) [Fig. 11, annotated above]. Regarding claim 4, Wu discloses wherein the at least one light-emitting element (LED) comprises a plurality of light-emitting elements (LED) [Figs. 1 and 11, annotated above], and one of the at least one first sensing element (20/10/21/22) and/or one of the at least one second sensing element (20/10/21/22) is located between adjacent light-emitting elements (LED) of the plurality of light-emitting elements in a direction perpendicular to a plane of the substrate (S) [Fig. 1 and 11, annotated above]. Regarding claim 22, Wu discloses a display device, comprising: a display panel (100) [Fig. 1 and 11], wherein the display panel comprises: a substrate (S) [Fig. 11, annotated below]; at least one light-emitting element (72) [Fig. 11]; and sensing elements (20/10/21/22) [Fig. 11], wherein the sensing elements and the at least one light-emitting element are located at a same side of the substrate (S) [Fig. 11, annotated below]; the sensing elements comprise at least one first sensing element each configured to recognize fingerprint (10), and further comprises at least one second sensing element (20) . Allowable Subject Matter Claims 2 and 4-21 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to JOSE R DIAZ whose telephone number is (571)272-1727. The examiner can normally be reached Monday-Friday. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Joshua Benitez can be reached at 571-270-1435. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /Jose R Diaz/Primary Examiner, Art Unit 2815
Read full office action

Prosecution Timeline

Mar 25, 2024
Application Filed
Jul 29, 2026
Non-Final Rejection mailed — §102 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12740490
MOLDED DIRECT BONDED AND INTERCONNECTED STACK
1y 6m to grant Granted Sep 15, 2026
Patent 12727485
METHOD FOR FORMING ALIGNMENT KEYS OF SEMICONDUCTOR STRUCTURE AND SEMICONDUCTOR STRUCTURE HAVING ALIGNMENT KEYS
3y 11m to grant Granted Sep 01, 2026
Patent 12720813
SEMICONDUCTOR POWER DEVICE WITH IMPROVED RUGGEDNESS
2y 11m to grant Granted Aug 25, 2026
Patent 12721232
SEMICONDUCTOR PACKAGE HAVING MEMORY DEVICES STACKED IN STAIRCASE
2y 9m to grant Granted Aug 25, 2026
Patent 12721138
SEMICONDUCTOR STRUCTURES WITH THROUGH VIA
2y 9m to grant Granted Aug 25, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

Strategy Recommendation AI-generated — please review before filing

Get a prosecution strategy drawn from examiner precedents, rejection analysis, and claim mapping.
Typically takes 5-10 seconds — AI-generated, attorney review required before filing

Prosecution Projections

1-2
Expected OA Rounds
87%
Grant Probability
95%
With Interview (+7.9%)
2y 5m (~0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 967 resolved cases by this examiner. Grant probability derived from career allowance rate.

Sign in with your work email

Enter your email to receive a magic link. No password needed.

Personal email addresses (Gmail, Yahoo, etc.) are not accepted.

Free tier: 3 strategy analyses per month