Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Each of claims 8 and 41 are missing a period at the end of the respective claim.
Each of claims 9 and 42 recites: “comprises a second external termination and said second termination is in electrical contact with a conductor.” This should be: “comprises a second external termination and said external second termination is in electrical contact with a conductor.”
Appropriate correction is required.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 3-11, 17, 20, 25, 28, 31-34, 36-46, 52, 55, 60, 63 and 66-68 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Park et al. (US 10,863,627, “Park”).
Regarding claim 1, Park anticipates 1. A circuit board core material comprising: a laminate comprising: a prepreg layer comprising prepreg (Fig. 3, col. 4, lines 32-50, col. 9, lines 31-36; the core structure 110 is a laminate comprising the insulator 130 comprising thermosetting resin and an inorganic filler, for example, prepreg);
wherein said prepreg layer comprises a pocket (Fig. 3, col. 4, lines 32-50, col. 9, lines 31-36; the insulator 130 comprises a pocket);
and an electronic component in said pocket and in a direct physical bond with said prepreg (Fig. 3, col. 4, lines 32-50, col. 9, lines 31-36; the electronic component 120A is in the pocket, and is in direct physical bond with the insulator 130 prepreg).
Regarding claim 3, Park anticipates 3. The circuit board core material of claim 1 wherein said electronic component comprises a first external termination and a second external termination (Fig. 3, col. 4, lines 32-50; the electronic component 120A comprises the connection electrode 122a which is a first external termination and the connection electrode 123a which is a second external termination).
Regarding claim 4, Park anticipates 4. The circuit board core material of claim 3 wherein said first external termination and said second external termination are planer with clad layers on said prepreg (Fig. 3, col. 4, lines 32-50; the connection electrodes 122a, 122b are planer with metal layers 115a and 115b which are clad layers on the insulator 130).
Regarding claim 5, Park anticipates 5. The circuit board core material of claim 1 wherein said laminate comprises a first clad layer on a first side of said prepreg layer (Fig. 3, col. 4, lines 32-50; the metal layer 115a is a first clad layer on a first side of the insulator 130).
Regarding claim 6, Park anticipates 6. The circuit board core material of claim 5 further comprising a second clad layer on a second side of said prepreg (Fig. 3, col. 4, lines 32-50; the metal layer 115b is a second clad layer on a second side of the insulator 130).
Regarding claim 7, Park anticipates 7. The circuit board core material of claim 5 wherein said electronic component comprises a first external termination and said first external termination is in electrical contact with said first clad layer (Fig. 3, col. 4, lines 32-50; the electronic component 120A comprises the connection electrode 122a which is in electrical contact with the metal layer 115a).
Regarding claim 8, Park anticipates 8. The circuit board core material of claim 7 wherein said first external termination is laminated to and in electrical contact with said first clad layer (Fig. 3, col. 4, lines 32-50; the connection electrode 122a is laminated to and in electrical contact with the metal layer 115a. Examiner’s note: see the claim objections above regarding this claim.)
Regarding claim 9, Park anticipates 9. The circuit board core material of claim 1 wherein said electronic component comprises a second external termination and said second external termination is in electrical contact with a conductor (Fig. 3, col. 4, lines 32-50; the connection electrode 122b is in electrical contact with the via 113b which is a conductor. Examiner’s note: see the claim objections above regarding this claim.).
Regarding claim 10, Park anticipates 10. The circuit board core material of claim 1 wherein said electronic component is selected from the group consisting of capacitor, resistor, silicon die, diode, inductive material, and magnetic device (Fig. 3, col. 4, lines 32-50; the electronic component 120A is a ceramic capacitor).
Regarding claim 11, Park anticipates 11. The circuit board core material of claim 10 wherein said capacitor is selected from a foil capacitor, a pressed powder capacitor, and a ceramic capacitor (Fig. 3, col. 4, lines 32-50; the electronic component 120A is a ceramic capacitor).
Regarding claim 17, Park anticipates 17. The circuit board core material of claim 1 wherein said first external termination is a counter electrode (Fig. 3, col. 4, lines 32-50; the connection electrode 122a is a counter electrode).
Regarding claim 20, Park anticipates 20. The circuit board core material of claim 1 wherein said first clad layer comprises copper (Fig. 3, col. 8, lines 66-67; the metal layers 115a-b are copper).
Regarding claim 25, Park anticipates 25. The circuit board core material of claim 1 further comprising a via pass through section (Fig. 3, col. 5, lines 32-50; the via 113a is a via pass through section).
Regarding claim 28, Park anticipates 28. The circuit board core material of claim 1 comprising multiple electronic components (Fig. 4, col. 10, line 25; the second electronic component 160 is on the circuit board).
Regarding claim 31, Park anticipates 31. The circuit board core material of claim 1 further comprising a prepreg layer laminated on opposite side of electronic component from a first clad layer (Fig. 3, col. 9, line 41; the passivation layer 140 is a prepreg layer laminated on opposite side of electronic component 120a from the metal layer 115a).
Regarding claim 32, Park anticipates 32. The circuit board core material of claim 31 wherein said first clad layer has been etched (the limitation regarding the method to form the clad layer is a process limitation in a product claim and is treated in accordance with MPEP 2113. As this process limitation uses a product structure that is the same as the product of Park, this claim is therefore anticipated by Park).
Regarding claim 33, Park anticipates 33. The circuit board core material of claim 1 wherein said circuit board core material is flexible (Fig. 3, col. 9, line 41; the circuit board core material is flexible).
Regarding claim 34, Park anticipates 34. A circuit board comprising: a primary laminate comprising: a circuit board core material layered with circuit board material wherein said circuit board material is laminated to said circuit board core material to form said laminate (Fig. 3, col. 4, lines 32-50, col. 9, lines 31-36; the core structure 110 is a primary laminate comprising the insulating layers 111a-c which is a circuit board core material layered with circuit board material wherein said circuit board material is laminated to said circuit board core material to form said laminate)
wherein said circuit board core material comprises: a laminate comprising: a prepreg layer comprising prepreg (Fig. 3, col. 4, lines 32-50, col. 9, lines 31-36; the core structure 110 is a laminate comprising the insulator 130 comprising thermosetting resin and an inorganic filler, for example, prepreg)
wherein said prepreg layer comprises a pocket (Fig. 3, col. 4, lines 32-50, col. 9, lines 31-36; the insulator 130 comprises a pocket);
and an electronic component in said pocket and in a direct physical bond with said prepreg (Fig. 3, col. 4, lines 32-50, col. 9, lines 31-36; the electronic component 120A is in the pocket, and is in direct physical bond with the insulator 130 prepreg).
Regarding claim 36, Park anticipates 36. The circuit board of claim 34 wherein said electronic component comprises a first external termination and a second external termination (Fig. 3, col. 4, lines 32-50; the electronic component 120A comprises the connection electrode 122a which is a first external termination and the connection electrode 123a which is a second external termination).
Regarding claim 37, Park anticipates 37. The circuit board of claim 36 wherein said first external termination and said second external termination are planer with clad layers on said prepreg (Fig. 3, col. 4, lines 32-50; the connection electrodes 122a, 122b are planer with metal layers 115a and 115b which are clad layers on the insulator 130).
Regarding claim 38, Park anticipates 38. The circuit board of claim 34 wherein said laminate comprises a first clad layer on a first side of said prepreg layer (Fig. 3, col. 4, lines 32-50; the metal layer 115a is a first clad layer on a first side of the insulator 130).
Regarding claim 39, Park anticipates 39. The circuit board of claim 38 further comprising a second clad layer on a second side of said prepreg (Fig. 3, col. 4, lines 32-50; the metal layer 115b is a second clad layer on a second side of the insulator 130).
Regarding claim 40, Park anticipates 40. The circuit board of claim 38 wherein said electronic component comprises a first external termination and said first external termination is in electrical contact with said first clad layer (Fig. 3, col. 4, lines 32-50; the electronic component 120A comprises the connection electrode 122a which is in electrical contact with the metal layer 115a).
Regarding claim 41, Park anticipates 41. The circuit board of claim 40 wherein said first external termination is laminated to and in electrical contact with said first clad layer (Fig. 3, col. 4, lines 32-50; the connection electrode 122a is laminated to and in electrical contact with the metal layer 115a. Examiner’s note: see the claim objections above regarding this claim.)
Regarding claim 42, Park anticipates 42. The circuit board of claim 34 wherein said electronic component comprises a second external termination and said second external termination is in electrical contact with a conductor (Fig. 3, col. 4, lines 32-50; the connection electrode 122b is in electrical contact with the via 113b which is a conductor. Examiner’s note: see the claim objections above regarding this claim.).
Regarding claim 43, Park anticipates 43. The circuit board of claim 34 further comprising at least one via (Fig. 3, col. 5, lines 32-50; the via 113a is a via).
Regarding claim 44, Park anticipates 44. The circuit board of claim 34 further comprising at least one electronic component on said circuit board (Fig. 4, col. 10, line 25; the second electronic component 160 is on the circuit board).
Regarding claim 45, Park anticipates 45. The circuit board of claim 34 wherein said electronic component is selected from the group consisting of capacitor, resistor, silicon die, diode, inductive material and magnetic device (Fig. 3, col. 4, lines 32-50; the electronic component 120A is a ceramic capacitor).
Regarding claim 46, Park anticipates 46. The circuit board of claim 45 wherein said capacitor is selected from a foil capacitor, a pressed powder capacitor and a ceramic capacitor (Fig. 3, col. 4, lines 32-50; the electronic component 120A is a ceramic capacitor).
Regarding claim 52, Park anticipates 52. The circuit board of claim 34 wherein said electronic component comprises a counter electrode (Fig. 3, col. 4, lines 32-50; the connection electrode 122a is a counter electrode).
Regarding claim 55, Park anticipates 55. The circuit board of claim 34 wherein said laminate comprises a first claim layer wherein said first clad layer comprises copper (Fig. 3, col. 8, lines 66-67; the metal layers 115a-b are copper).
Regarding claim 60, Park anticipates 60. The circuit board of claim 34 further comprising a via pass through region (Fig. 3, col. 5, lines 32-50; the via 113a is a via pass through section).
Regarding claim 63, Park anticipates 63. The circuit board of claim 34 comprising multiple electronic components (Fig. 4, col. 10, line 25; the second electronic component 160 is on the circuit board).
Regarding claim 66, Park anticipates 66. The circuit board of claim 34 further comprising a prepreg layer laminated on opposite side of electronic component from first clad layer (Fig. 3, col. 9, line 41; the passivation layer 140 is a prepreg layer laminated on opposite side of electronic component 120a from the metal layer 115a).
Regarding claim 67, Park anticipates 67. The circuit board of claim 34 wherein said laminate comprises a first clad layer wherein said first clad layer has been etched (the limitation regarding the method to form the clad layer is a process limitation in a product claim and is treated in accordance with MPEP 2113. As this process limitation uses a product structure that is the same as the product of Park, this claim is therefore anticipated by Park).
Regarding claim 68, Park anticipates 68. The circuit board of claim 34 wherein said circuit board core material is flexible (Fig. 3, col. 9, line 41; the circuit board core material is flexible).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 2 and 35 are rejected under 35 U.S.C. 103 as being unpatentable over Park as applied to respective claims 1 and 34, above, in view of Shimabe et al. (US 2015/0264815, “Shimabe”).
Regarding claim 2, Park discloses the claimed invention as applied to claim 1, above.
Park does not disclose the limitations of claim 2.
Shimabe discloses 2. The circuit board core material of claim 1 wherein said prepreg layer is cured (Fig. 4A, [0053]; the prepregs on the first surface and the second surface of the core substrate are cured).
It would have been obvious to a person having ordinary skill in the art, before the effective filing date of the claimed invention, to have constructed Park’s structure with Shimabe’s cured prepreg so that there is no scattering of potassium ions so that it does not become a factor causing migration as suggested by Shimabe at [0054].
Regarding claim 35, Park discloses the claimed invention as applied to claim 34, above.
Park does not disclose the limitations of claim 35.
Shimabe discloses 35. The circuit board of claim 34 wherein said prepreg layer is cured (Fig. 4A, [0053]; the prepregs on the first surface and the second surface of the core substrate are cured).
It would have been obvious to a person having ordinary skill in the art, before the effective filing date of the claimed invention, to have constructed Park’s structure with Shimabe’s cured prepreg so that there is no scattering of potassium ions so that it does not become a factor causing migration as suggested by Shimabe at [0054].
Claims 12-15 and 47-50 are rejected under 35 U.S.C. 103 as being unpatentable over Park as applied to respective claims 1 and 34, above, in view of Takahashi et al. (US 2019/0392997, “Takahashi”).
Regarding claim 12, Park discloses the claimed invention as applied to claim 10, above.
Park does not disclose the limitations of claim 12.
Takahashi discloses 12. The circuit board core material of claim 10 wherein said capacitor comprises a porous valve metal layer (Figs. 1-2, [0019]; the capacitor comprises a porous valve metal layer foil made from tantalum, aluminum or niobium).
It would have been obvious to a person having ordinary skill in the art, before the effective filing date of the claimed invention, to have constructed Park’s structure with Takahashi’s capacitor in order to suppress an increase in ESR and an increase in leakage current as suggested by Takahashi at Abstract.
Regarding claim 13, Park in view of Takahashi discloses the claimed invention as applied to claim 12, above.
Park does not disclose the limitations of claim 13.
Takahashi discloses 13. The circuit board core material of claim 12 wherein said capacitor comprises a dielectric on said porous valve metal layer (Figs. 1-2, [0019]; the capacitor comprises a porous valve metal layer foil made from tantalum, aluminum or niobium).
Regarding claim 14, Park in view of Takahashi discloses the claimed invention as applied to claim 12, above.
Park does not disclose the limitations of claim 14.
Takahashi discloses 14. The circuit board core material of claim 12 wherein said valve metal is selected from the group consisting of aluminum, tantalum, niobium and NbO (Figs. 1-2, [0019]; the capacitor comprises a porous valve metal layer foil made from tantalum, aluminum or niobium).
Regarding claim 15, Park in view of Takahashi discloses the claimed invention as applied to claim 12, above.
Park does not disclose the limitations of claim 15.
Takahashi discloses 15. The circuit board core material of claim 12 wherein said porous valve metal layer is a foil (Figs. 1-2, [0019]; the capacitor comprises a porous valve metal layer foil made from tantalum, aluminum or niobium).
Regarding claim 47, Park discloses the claimed invention as applied to claim 45, above.
Park does not disclose the limitations of claim 47.
Takahashi discloses 47. The circuit board of claim 45 wherein said capacitor comprises a porous valve metal layer (Figs. 1-2, [0019]; the capacitor comprises a porous valve metal layer foil made from tantalum, aluminum or niobium).
It would have been obvious to a person having ordinary skill in the art, before the effective filing date of the claimed invention, to have constructed Park’s structure with Takahashi’s capacitor in order to suppress an increase in ESR and an increase in leakage current as suggested by Takahashi at Abstract.
Regarding claim 48, Park in view of Takahashi discloses the claimed invention as applied to claim 47, above.
Park does not disclose the limitations of claim 48.
Takahashi discloses 48. The circuit board of claim 47 wherein said capacitor comprises a dielectric on said porous valve metal layer (Figs. 1-2, [0018]; the dielectric layer 12 is on the porous valve metal layer).
Regarding claim 49, Park in view of Takahashi discloses the claimed invention as applied to claim 47, above.
Park does not disclose the limitations of claim 49.
Takahashi discloses 49. The circuit board of claim 47 wherein said valve metal is selected from the group consisting of aluminum, tantalum, niobium and NbO (Figs. 1-2, [0019]; the capacitor comprises a porous valve metal layer foil made from tantalum, aluminum or niobium).
Regarding claim 50, Park discloses the claimed invention as applied to claim 45, above.
Park does not disclose the limitations of claim 50.
Takahashi discloses 50. The circuit board of claim 45 wherein said porous valve metal layer is a foil (Figs. 1-2, [0019]; the capacitor comprises a porous valve metal layer foil made from tantalum, aluminum or niobium).
It would have been obvious to a person having ordinary skill in the art, before the effective filing date of the claimed invention, to have constructed Park’s structure with Takahashi’s capacitor in order to suppress an increase in ESR and an increase in leakage current as suggested by Takahashi at Abstract.
Claims 16 and 51 are rejected under 35 U.S.C. 103 as being unpatentable over Park as applied to respective claims 10 and 45, above, in view of Chako et al. (US 2016/0329156, “Chako”).
Regarding claim 16, Park discloses the claimed invention as applied to claim 10, above.
Park does not disclose the limitations of claim 16.
Chako discloses 16. The circuit board core material of claim 10 wherein said capacitor comprises a metalized cathode layer (Fig. 1, [0032]; the capacitor 1 comprises a metalized cathode layer).
It would have been obvious to a person having ordinary skill in the art, before the effective filing date of the claimed invention, to have constructed Park’s structure with Chako’s capacitor in order to improve the volumetric efficiency of a hermetically sealed capacitor by conformal hermetic elements, as suggested by Chako at [0002].
Regarding claim 51, Park discloses the claimed invention as applied to claim 45, above.
Park does not disclose the limitations of claim 51.
Chako discloses 51. The circuit board of claim 45 wherein said capacitor comprises a metalized cathode layer (Fig. 1, [0032]; the capacitor 1 comprises a metalized cathode layer).
It would have been obvious to a person having ordinary skill in the art, before the effective filing date of the claimed invention, to have constructed Park’s structure with Chako’s capacitor in order to improve the volumetric efficiency of a hermetically sealed capacitor by conformal hermetic elements, as suggested by Chako at [0002].
Claims 18-19 and 53-54 are rejected under 35 U.S.C. 103 as being unpatentable over Park as applied to respective claims 17 and 52, above, in view of Nishino et al. (US 4,737,889, “Nishino”).
Regarding claim 18, Park discloses the claimed invention as applied to claim 17, above.
Park does not disclose the limitations of claim 18.
Nishino discloses 18. The circuit board core material of claim 17 further comprising a conductive paint on said counter electrode (Fig. 1, col. 7, lines 45-62; the conductive paint, which has carbon and a resin as a binding medium is on the electrode).
It would have been obvious to a person having ordinary skill in the art, before the effective filing date of the claimed invention, to have constructed Park’s structure with Nishino’s conductive paint in order to make the conductive layer and the conditions of electrolyte, casing, etc., about the same capacitor value as that of the example, while the impedances of the present embodiment show larger values in comparison, because the metal conductive layer has stronger bonding to the polarizable electrode body and because of having difference of resistance values of the conductive body per se, as suggested by Nishino at col. 7, lines 45-62.
Regarding claim 19, Park in view of Nishino discloses the claimed invention as applied to claim 18, above.
Park does not disclose the limitations of claim 19.
Nishino discloses 19. The circuit board core material of claim 18 wherein said conductive paint comprises at least one of a carbon filled resin or a metal filled resin (Fig. 1, col. 7, lines 45-62; the conductive paint, which has carbon and a resin as a binding medium is on the electrode).
Regarding claim 53, Park discloses the claimed invention as applied to claim 52, above.
Park does not disclose the limitations of claim 53.
Nishino discloses 53. The circuit board of claim 52 further comprising a conductive paint on said counter electrode (Fig. 1, col. 7, lines 45-62; the conductive paint, which has carbon and a resin as a binding medium is on the electrode).
It would have been obvious to a person having ordinary skill in the art, before the effective filing date of the claimed invention, to have constructed Park’s structure with Nishino’s conductive paint in order to make the conductive layer and the conditions of electrolyte, casing, etc., about the same capacitor value as that of the example, while the impedances of the present embodiment show larger values in comparison, because the metal conductive layer has stronger bonding to the polarizable electrode body and because of having difference of resistance values of the conductive body per se, as suggested by Nishino at col. 7, lines 45-62.
Regarding claim 54, Park in view of Nishino discloses the claimed invention as applied to claim 53, above.
Park does not disclose the limitations of claim 54.
Nishino discloses 54. The circuit board of claim 53 wherein said conductive paint comprises at least one of a carbon filled resin or a metal filled resin (Fig. 1, col. 7, lines 45-62; the conductive paint, which has carbon and a resin as a binding medium is on the electrode).
Claims 21-24 and 56-59 are rejected under 35 U.S.C. 103 as being unpatentable over Park as applied to respective claims 1 and 34, above, in view of Salcedo et al. (US 2006/0151836, “Salcedo”).
Regarding claim 21, Park discloses the claimed invention as applied to claim 1, above.
Park does not disclose the limitations of claim 21.
Salcedo discloses 21. The circuit board core material of claim 1 further comprising a cathode isolation region (claim 14, the electrostatic discharge (ESD) device comprises a cathode comprising a cathode isolation region).
It would have been obvious to a person having ordinary skill in the art, before the effective filing date of the claimed invention, to have constructed Park’s structure with Salcedo’s isolation region in order to provide for an electrostatic discharge protection device for applications with input/output bipolar voltage higher than the core circuit power supply, as suggested by Salcedo at Abstract.
Regarding claim 22, Park in view of Salcedo discloses the claimed invention as applied to claim 21, above.
Park does not disclose the limitations of claim 22.
Salcedo discloses 22. The circuit board core material of claim 21 further wherein said cathode isolation region comprises an isolation material (claim 14, the electrostatic discharge (ESD) device comprises a cathode comprising a cathode isolation region having an isolation material of a length of L1).
Regarding claim 23, Park discloses the claimed invention as applied to claim 1, above.
Park does not disclose the limitations of claim 23.
Salcedo discloses 23. The circuit board core material of claim 1 further comprising an anode isolation region (claim 17, the electrostatic discharge (ESD) device comprises an anode comprising an anode isolation region).
It would have been obvious to a person having ordinary skill in the art, before the effective filing date of the claimed invention, to have constructed Park’s structure with Salcedo’s isolation region in order to provide for an electrostatic discharge protection device for applications with input/output bipolar voltage higher than the core circuit power supply, as suggested by Salcedo at Abstract.
Regarding claim 24, Park in view of Salcedo discloses the claimed invention as applied to claim 23, above.
Park does not disclose the limitations of claim 24.
Salcedo discloses 24. The circuit board core material of claim 23 further wherein said anode isolation region comprises an isolation material (claim 17, the electrostatic discharge (ESD) device comprises an anode comprising an anode isolation region having an isolation material of a length of L2).
Regarding claim 56, Park discloses the claimed invention as applied to claim 34, above.
Park does not disclose the limitations of claim 56.
Salcedo discloses 56. The circuit board of claim 34 further comprising a cathode isolation region (claim 14, the electrostatic discharge (ESD) device comprises a cathode comprising a cathode isolation region).
It would have been obvious to a person having ordinary skill in the art, before the effective filing date of the claimed invention, to have constructed Park’s structure with Salcedo’s isolation region in order to provide for an electrostatic discharge protection device for applications with input/output bipolar voltage higher than the core circuit power supply, as suggested by Salcedo at Abstract.
Regarding claim 57, Park in view of Salcedo discloses the claimed invention as applied to claim 56, above.
Park does not disclose the limitations of claim 57.
Salcedo discloses 57. The circuit board core material of claim 56 further wherein said cathode isolation region comprises an isolation material (claim 14, the electrostatic discharge (ESD) device comprises a cathode comprising a cathode isolation region having an isolation material of a length of L1).
Regarding claim 58, Park discloses the claimed invention as applied to claim 34, above.
Park does not disclose the limitations of claim 58.
Salcedo discloses 58. The circuit board of claim 34 further comprising an anode isolation region (claim 17, the electrostatic discharge (ESD) device comprises an anode comprising an anode isolation region).
It would have been obvious to a person having ordinary skill in the art, before the effective filing date of the claimed invention, to have constructed Park’s structure with Salcedo’s isolation region in order to provide for an electrostatic discharge protection device for applications with input/output bipolar voltage higher than the core circuit power supply, as suggested by Salcedo at Abstract.
Regarding claim 59, Park in view of Salcedo discloses the claimed invention as applied to claim 58, above.
Park does not disclose the limitations of claim 59.
Salcedo discloses 59. The circuit board of claim 58 further wherein said anode isolation region comprises an isolation material (claim 17, the electrostatic discharge (ESD) device comprises an anode comprising an anode isolation region having an isolation material of a length of L2).
Claims 26-27 and 61-62 are rejected under 35 U.S.C. 103 as being unpatentable over Park as applied to respective claims 1 and 34, above, in view of Hahn et al. (US 2018/0211790, “Hahn”).
Regarding claim 26, Park discloses the claimed invention as applied to claim 1, above.
Park does not disclose the limitations of claim 26.
Hahn discloses 26. The circuit board core material of claim 1 further comprising a conductive node (Figs. 2-3, [0021]; the conductive node, 28, is in electrical contact with the anode lead, 14).
It would have been obvious to a person having ordinary skill in the art, before the effective filing date of the claimed invention, to have constructed Park’s structure with Hahn’s anode conductive node in order to provide a preferred conductive path due to a resistance which is lower than the resistance of the current path through the dielectric 16, as suggested by Hahn at [0021].
Regarding claim 27, Park in view of Hahn discloses the claimed invention as applied to claim 26, above.
Park does not disclose the limitations of claim 27.
Hahn discloses 27. The circuit board core material of claim 26 wherein said conductive node is an anode conductive node (Figs. 2-3, [0021]; the conductive node, 28, is in electrical contact with the anode lead, 14).
Regarding claim 61, Park discloses the claimed invention as applied to claim 34, above.
Park does not disclose the limitations of claim 61.
Hahn discloses 61. The circuit board of claim 34 further comprising a conductive node (Figs. 2-3, [0021]; the conductive node, 28, is in electrical contact with the anode lead, 14).
It would have been obvious to a person having ordinary skill in the art, before the effective filing date of the claimed invention, to have constructed Park’s structure with Hahn’s anode conductive node in order to provide a preferred conductive path due to a resistance which is lower than the resistance of the current path through the dielectric 16, as suggested by Hahn at [0021].
Regarding claim 62, Park in view of Hahn discloses the claimed invention as applied to claim 61, above.
Park does not disclose the limitations of claim 62.
Hahn discloses 62. The circuit board of claim 61 wherein said conductive node is an anode conductive node (Figs. 2-3, [0021]; the conductive node, 28, is in electrical contact with the anode lead, 14).
Claims 29-30 and 64-65 are rejected under 35 U.S.C. 103 as being unpatentable over Park as applied to respective claims 1 and 34, above, in view of Naito et al. (US 2017/0169957, “Naito”).
Regarding claim 29, Park discloses the claimed invention as applied to claim 1, above.
Park does not disclose the limitations of claim 29.
Naito discloses 29. The circuit board core material of claim 1 further comprising at least one clad bonding layer (Figs. 3-4, [0102]; the conductive adhesive layer 410 is between the adjacent external terminal 400 and the counter electrode 20).
It would have been obvious to a person having ordinary skill in the art, before the effective filing date of the claimed invention, to have constructed Park’s structure with Naito’s bonding layer in order to obtain a high capacitance even with a small number of times of polymerization treatments, as suggested by Naito at Abstract.
Regarding claim 30, Park discloses the claimed invention as applied to claim 1, above.
Park does not disclose the limitations of claim 30.
Naito discloses 30. The circuit board core material of claim 1 further comprising at least one electrical connection layer between adjacent said external termination and clad layer (Figs. 3-4, [0102]; the conductive adhesive layer 410 is between the adjacent external terminal 400 and the counter electrode 20).
It would have been obvious to a person having ordinary skill in the art, before the effective filing date of the claimed invention, to have constructed Park’s structure, as modified by Naito, with Naito’s bonding layer in order to obtain a high capacitance even with a small number of times of polymerization treatments, as suggested by Naito at Abstract.
Regarding claim 64, Park discloses the claimed invention as applied to claim 34, above.
Park does not disclose the limitations of claim 64.
Naito discloses 64. The circuit board of claim 34 further comprising at least one clad bonding layer (Figs. 3-4, [0102]; the conductive adhesive layer 410 is between the adjacent external terminal 400 and the counter electrode 20).
It would have been obvious to a person having ordinary skill in the art, before the effective filing date of the claimed invention, to have constructed Park’s structure with Naito’s bonding layer in order to obtain a high capacitance even with a small number of times of polymerization treatments, as suggested by Naito at Abstract.
Regarding claim 65, Park discloses the claimed invention as applied to claim 34, above.
Park does not disclose the limitations of claim 65.
Naito discloses 65. The circuit board of claim 34 further comprising at least one electrical connection layer between adjacent said external termination and clad layer (Figs. 3-4, [0102]; the conductive adhesive layer 410 is between the adjacent external terminal 400 and the counter electrode 20).
It would have been obvious to a person having ordinary skill in the art, before the effective filing date of the claimed invention, to have constructed Park’s structure with Naito’s bonding layer in order to obtain a high capacitance even with a small number of times of polymerization treatments, as suggested by Naito at Abstract.
In the event that a tribunal determines that claims 32 and 57 are not properly rejected under 35 U.S.C. 102 (above), claims 32 and 67 are alternately rejected under 35 U.S.C. 103 as being unpatentable over Park as applied to respective claims 31 and 56, above, in view of Park et al. (US 20140104798, “Park ‘798”).
Regarding claim 32, Park discloses the claimed invention as applied to claim 31, above.
Alternately, Park does not disclose the limitations of claim 32.
Park ‘798 discloses 32. The circuit board core material of claim 31 wherein said first clad layer has been etched ([0074], [0086]; the clad layer is etched).
It would have been obvious to a person having ordinary skill in the art, before the effective filing date of the claimed invention, to have constructed Park’s structure with Park ‘798’s etched clad layer in order to form the pattern by the plating using the clad layer as the seed layer, as suggested by Park ‘798 at [0074].
Regarding claim 67, Park discloses the claimed invention as applied to claim 34, above.
Alternately, Park does not disclose the limitations of claim 67.
Park ‘798 discloses 67. The circuit board of claim 34 wherein said first clad layer has been etched ([0074], [0086]; the clad layer is etched).
It would have been obvious to a person having ordinary skill in the art, before the effective filing date of the claimed invention, to have constructed Park’s structure with Park ‘798’s etched clad layer in order to form the pattern by the plating using the clad layer as the seed layer, as suggested by Park ‘798 at [0074].
Conclusion
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/STANLEY TSO/Primary Examiner, Art Unit 2847
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