DETAILED ACTION
This action is responsive to the amendment filed on 09/26/2025.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-4 and 6-22 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 2023/0065925 A1; Koshimizu et al.; 03/2023; (“Koshimizu”) in view of US 2020/0119189 A1; Huang et al.; 04/2020; (“Huang”). An annotated version of Figure 18 from Koshimizu (925) is provided below.
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Regarding Claim 1. Koshimizu discloses a structure (Figure 18) comprising:
a first device (MOS transistor, Figure 18) on a semiconductor substrate (#SB, Figure 18, [0038], semiconductor substrate that MOS is on); and
a second device (Right LDMOS, Figure 18 annotated) on the semiconductor substrate (Figure 18 annotated, Right LDMOS is on #SB), the second device comprising a recessed channel region (#RC, Figure 18 annotated) below a surface of the first device (Figure 18 annotated, #RC is below a surface of the MOS transistor) the recessed channel region being defined by a sidewall of the semiconductor substrate and a shallow trench isolation structure (Figure 18 annotated, the #RC of the right LDMOS is defined by a sidewall of #SB on its left side and a shallow trench isolation structure, #BI trench insulating layer, on its right side),
wherein the second device (Right LDMOS, Figure 18 annotated) comprises a gate insulator material (#GI, Figure 18 annotated, gate insulator) and a gate electrode (#GE, Figure 18 annotated, gate electrode) on the gate insulator material (Figure 18, #GE is on #GI) confined within the recessed channel region in the horizontal direction (Figure 18, #GE is confined in #RC in a horizontal direction).
Koshimizu does not disclose that the second device comprises a gate insulator material having a first thickness thicker than a second thickness with both the first thickness and the second thickness of the gate insulator material being confined within the recessed channel region in a horizontal direction, and the gate insulator material with the first thickness confined within the recessed channel region in the horizontal direction extends above a height of the recessed channel region in a vertical direction, and the gate insulator material contacts the sidewall of the semiconductor substrate within the recessed channel region and is separated from the shallow trench isolation structure by a space between the second thickness of the gate insulator material and the shallow trench isolation structure thereby exposing the semiconductor substrate within the recessed channel region.
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However, Huang teaches a device (#200, Figure 2A, high voltage device) on a semiconductor substrate (#21 and #21’, Figure 2A, [0040], “semiconductor layer 21′ . . . is a part of the substrate 21”), the device comprising a recessed channel region (#23a, Figure 2A, operation region) below a surface of the substrate (Figure 2A, #23a is recessed below an uppermost surface of #21’), the recessed channel region being defined by a sidewall of the semiconductor substrate and a shallow trench isolation structure (Figure 2A, let #23a be bounded on the left by isolation region #23 and bounded on the right by #29 see annotated Figure 2A above),
wherein the device comprises a gate insulator material (#271 and #24, Figure 2A, dielectric layer and drift oxide region) having a first thickness (Figure 2A, #24 has a first thickness) thicker than a second thickness (Figure 2A, #271 has a second thickness under #272 such that the thickness of #24 is greater) with both the first thickness and the second thickness of the gate insulator material being confined within the recessed channel region in a horizontal direction (Figure 2A annotated, both #24 and #271 are confined within the recessed channel region in the horizontal direction),
a gate electrode (#272 of #27, Figure 2A, conductive layer of the gate) on the gate insulator material (Figure 2A, #272 is on both #271 and #24) also confined within the recessed channel region in the horizontal direction (Figure 2A annotated, #272 is confined within the recessed channel region in the horizontal direction),
the gate insulator material with the first thickness confined within the recessed channel region in the horizontal direction extends above a height of the recessed channel region in a vertical direction (Figure 2A annotated, #24 extends above a height of the recessed channel region in the vertical direction), and
the gate insulator material contacts the sidewall of the semiconductor substrate within the recessed channel region (Figure 2A annotated, #24 contacts the sidewall of #21’ within the recessed channel region) and is separated from the shallow trench isolation structure by a space between the second thickness of the gate insulator material and the shallow trench isolation structure thereby exposing the semiconductor substrate within the recessed channel region (Figure 2A annotated, #271 is separated from #23 by a space between #271 and the left #23 to expose a surface of #21’ within the recessed channel region).
It would have been obvious to one or ordinary skill in the art before the effective filing date of the claimed invention to consider utilizing the high breakdown voltage device of Huang as the high breakdown voltage LDMOS of Koshimizu, the device in Huang is beneficial for reducing the conductive resistance and withstanding a higher operation volage (see [0006], [0042], and [0054] of Huang).
Regarding Claim 2. Koshimizu in view of Huang discloses the structure of claim 1, wherein the second device comprises a recessed source region (Koshimizu, #SR, Figure 18 annotated, [0045], source region #SR which is recessed next to #RC in the Right LDMOS; Huang, Figure 2A, source region #28 is recessed below the surface of the substrate #21’) and
the gate insulator material comprises a local oxidation of semiconductor material (Koshimizu, [0071], #GI is oxidized semiconductor substrate and Huang, [0041], #24 is formed in the same fashion as #23 which may be local oxidation of silicon) and comprises a stepped feature comprising the first thickness and the second thickness (Huang, Figure 2A, the combination of #271 and #24 forms a stepped feature from their two thicknesses).
Regarding Claim 3. Koshimizu in view of Huang discloses the structure of claim 2, wherein the second device comprises a raised drain region (Huang, Figure 2A, drain region #29 is raised to the top of the substrate such that current follows the upward motion of the arrow; Koshimizu, Figure 18, raised drain region #DR),
the raised drain region having a vertical topography higher than the recessed channel region and the recessed source region (Koshimizu, Figure 18 annotated, #DR has a higher topography than the #RC and #SR; Huang, Figure 2A annotated, #29 has a vertical topography which is higher than the recessed channel and recessed source regions), wherein the first thickness is closer to the raised drain region (Huang, Figure 2A, #24 is closer to #29) and the second thickness is closer to the recessed source region (Huang, Figure 2A, #271 is closer to #28).
Regarding Claim 4. Koshimizu in view of Huang discloses the structure of claim 3, wherein the raised drain region is shared amongst the second device and a third device (Koshimizu, Figure 18 annotated, #DR is shared by the Left LDMOS transistor and the Right LDMOS transistor), the third device comprising the recessed channel region (Koshimizu, Figure 18 annotated, the Left LDMOS transistor #RC) and a second recessed source region (Koshimizu, Figure 18 annotated, the Left LDMOS transistor includes another #SR), with the third device comprising the gate insulator material and the gate electrode both extending above the recessed channel region (Koshimizu, Figure 18 annotated, the Left LDMOS transistor includes the gate electrode #GE and the gate insulator #GI extending above the recessed channel region #RC).
Regarding Claim 6. Koshimizu in view of Huang discloses the structure of claim 1, wherein the gate insulator material is a local oxidation of the semiconductor substrate (Koshimizu, [0071], #GI is oxidized semiconductor substrate and Huang, [0041], #24 is formed in the same fashion as #23 which may be local oxidation of silicon).
Regarding Claim 7. Koshimizu in view of Huang discloses the structure of claim 6, wherein the local oxidation of the semiconductor substrate comprises a bottom planar surface in the recessed channel region in a horizontal orientation (Huang, Figure 2A annotated, #24 has a bottom planar surface in the recessed channel region), and the bottom surface is below a surface of the semiconductor substrate (Huang, Figure 2A annotated, the bottom planar surface of #24 is below a top surface of #21’) and a top planar surface in a horizontal orientation is above the surface of the semiconductor substrate (Huang, Figure 2A annotated, #24 has a top planar surface in above the top surface of #21’).
Regarding Claim 8. Koshimizu in view of Huang discloses the structure of claim 1, wherein the second device comprises a laterally-diffused metal-oxide semiconductor device (Koshimizu, Figure 18 annotated, the Right LDMOS transistor is a Laterally Diffused Metal Oxide Semiconductor device) and the first device comprises a logic device (Koshimizu, Figure 18 annotated, the MOS transistor is a transistor which is necessarily a logic device).
Regarding Claim 9. Koshimizu in view of Huang discloses the structure of claim 1, further comprising additional shallow trench isolation structures (Koshimizu, plurality of #BIs, Figure 18, [0044], insulating layer #BI in the trenches #TRE) isolating the first device and the second device (Koshimizu, Figure 18 annotated, one of the #Bis isolates the MOS transistor from the Right LDMOS transistor), the shallow trench isolation structures having a planar surface with a top surface of the semiconductor substrate (Koshimizu, Figure 18, the #BIs have a planar upper surface with the top surface of #SB).
Regarding Claim 10. Koshimizu discloses a structure (Figure 18) comprising:
a first device (MOS transistor, Figure 18) on a first surface of a semiconductor substrate (#SB, Figure 18 annotated, [0038], semiconductor substrate with MOS transistor on first surface #SB1 in Figure 18 annotated);
a second device (Right LDMOS transistor, Figure 18 annotated) on a second surface of the semiconductor substrate (#SB, Figure 18, [0038], semiconductor substrate with Right LDMOS transistor on second surface #SB2 in Figure 18 annotated), the second surface being lower than the first surface (Figure 18 annotated, #SB2 is lower than #SB1) and being defined as a recessed channel region (#RC, Figure 18 annotated) defined by a sidewall of the semiconductor substrate and a shallow trench isolation structure (Figure 18 annotated, the #RC of the right LDMOS is defined by a sidewall of #SB on its left side and a shallow trench isolation structure, #BI trench insulating layer, on its right side), the second device (Right LDMOS, Figure 18 annotated) comprising an insulator material (#GI, Figure 18 annotated, [0054], gate insulator over #RC) and a gate electrode on the insulator material (#GE, Figure 18 annotated, gate electrode on #GI); and
wherein the shallow trench isolation structures (#BI, Figure 18, [0044], insulating layer #BI in the trenches #TRE) isolating the first device and the second device (Figure 18 annotated, one of the #BIs isolates the MOS transistor from the Right LDMOS transistor), the shallow trench isolation structures comprising a surface that is planar with the first surface of the semiconductor substrate (Figure 18 annotated, the #BIs have a planar upper surface with #SB1).
Koshimizu does not disclose that the second device comprising an insulator material with a stepped feature comprising various thicknesses and a gate electrode on the stepped feature of the insulator material within the recessed channel region in a horizontal direction, wherein the various thicknesses include a first thickness thicker than a second thickness both of which are confined within the recessed channel region in the horizontal direction, the gate insulator with the first thickness extends above a height of the recessed channel region in a vertical direction; and
wherein the insulator material contacts the sidewall of the semiconductor substrate within the recessed channel region and is separated from the shallow trench isolation structure by a space between the second thickness of the gate insulator material and the shallow trench isolation structure thereby exposing the semiconductor substrate within the recessed channel region.
However, Huang teaches a device (#200, Figure 2A, high voltage device) on a semiconductor substrate (#21 and #21’, Figure 2A, [0040], “semiconductor layer 21′ . . . is a part of the substrate 21”), the device comprising a recessed channel region (#23a, Figure 2A, operation region) below a surface of the substrate (Figure 2A, #23a is recessed below an uppermost surface of #21’), the recessed channel region being defined by a sidewall of the semiconductor substrate and a shallow trench isolation structure (Figure 2A, let #23a be bounded on the left by isolation region #23 and bounded on the right by #29 see annotated Figure 2A above),
wherein the device comprises a gate insulator material (#271 and #24, Figure 2A, dielectric layer and drift oxide region) with a stepped feature comprising various thicknesses (Figure 2A, #24 has a first thickness and #271 has a second thickness under #272 together they form a stepped feature) and a gate electrode (#272 of #27, Figure 2A, conductive layer of the gate) on the stepped feature of the insulator material within the recessed channel region in a horizontal direction (Figure 2A annotated, #272 is the stepped feature of #24 and #271 and confined within the recessed channel region in the horizontal direction), wherein the various thicknesses include a first thickness thicker than a second thickness (Figure 2A, #271 has a second thickness under #272 such that the thickness of #24 is greater) both of which are confined within the recessed channel region in the horizontal direction (Figure 2A annotated, both #24 and #271 are confined within the recessed channel region in the horizontal direction), the gate insulator with the first thickness extends above a height of the recessed channel region in a vertical direction (Figure 2A, #24 extends above a height of the recessed channel region in the vertical direction); and
wherein the insulator material contacts the sidewall of the semiconductor substrate within the recessed channel region (Figure 2A annotated, #24 contacts the sidewall of #21’ within the recessed channel region) and is separated from the shallow trench isolation structure by a space between the second thickness of the gate insulator material and the shallow trench isolation structure thereby exposing the semiconductor substrate within the recessed channel region (Figure 2A annotated, #271 is separated from #23 by a space between #271 and the left #23 to expose a surface of #21’ within the recessed channel region).
It would have been obvious to one or ordinary skill in the art before the effective filing date of the claimed invention to consider utilizing the high breakdown voltage device of Huang as the high breakdown voltage LDMOS of Koshimizu, the device in Huang is beneficial for reducing the conductive resistance and withstanding a higher operation volage (see [0006], [0042], and [0054] of Huang).
Regarding Claim 11. Koshimizu in view of Huang discloses the structure of claim 10, wherein the recessed channel region is below the first surface and the first device (Koshimizu, Figure 18 annotated, the Right LDMOS has the right recessed channel region #RC below #SB1 and the MOS transistor).
Regarding Claim 12. Koshimizu in view of Huang discloses the structure of claim 11, wherein the second device comprises a recessed source region (Koshimizu, #SR, Figure 18 annotated, [0045], source region #SR which is recessed next to #RC in the Right LDMOS; Huang, Figure 2A, source region #28 is recessed below the surface of the substrate #21’) and a raised drain region (Huang, Figure 2A, drain region #29 is raised to the top of the substrate such that current follows the upward motion of the arrow; Koshimizu, Figure 18, raised drain region #DR).
Regarding Claim 13. Koshimizu in view of Huang discloses the structure of claim 12, wherein the raised drain region comprises a vertical topography higher than the recessed channel region and the recessed source region (Koshimizu, Figure 18 annotated, #DR has a higher topography than the #RC and #SR; Huang, Figure 2A annotated, #29 has a vertical topography which is higher than the recessed channel and recessed source regions).
Regarding Claim 14. Koshimizu in view of Huang discloses the structure of claim 13, further comprising a third device (Koshimizu, Left LDMOS transistor, Figure 18 annotated) on the second surface of the semiconductor substrate (Koshimizu, Figure 18 annotated, the Left LDMOS is on #SB2), the third device comprising the raised drain region shared with the second device (Koshimizu, Figure 18 annotated, #DR is shared by the Left LDMOS transistor and the Right LDMOS transistor).
Regarding Claim 15. Koshimizu in view of Huang discloses the structure of claim 14, wherein the third device comprises a second recessed channel region (Koshimizu, Figure 18, the Left LDMOS transistor includes a left #RC) and a second recessed source region (Koshimizu, Figure 18, the Left LDMOS transistor includes a #SR next to #RC).
Regarding Claim 16. Koshimizu in view of Huang discloses the structure of claim 11, further comprising an oxide material over the recessed channel region of the second device (Koshimizu, #GI, Figure 18 annotated, [0054], #GI is made of an oxide according to [0071]; Huang, [0041], #24 is formed in the same fashion as #23 which may be local oxidation of silicon), extending from a raised drain region to a recessed source region of the second device (Koshimizu, [0071], #GI covers entire substrate extending from #DR in the #CON region to #SR of the Right LDMOS transistor).
Regarding Claim 17. Koshimizu in view of Huang discloses the structure of claim 16, wherein the oxide material is a local oxidation of the semiconductor substrate (Koshimizu, [0071], #GI is oxidized semiconductor substrate and Huang, [0041], #24 is formed in the same fashion as #23 which may be local oxidation of silicon).
Regarding Claim 18. Koshimizu in view of Huang discloses the structure of claim 17, wherein the local oxidation of the semiconductor substrate comprises a bottom surface in the recessed channel region of the second device that is below the first surface of the semiconductor substrate (Koshimizu, Figure 18 annotated, [0071], GI is formed to cover the #RC below #GE such that it has a bottom surface below #SB1; Huang, Figure 2A annotated, #24 has a bottom planar surface in the recessed channel region below a top surface of #21’), and a top surface above the second surface of the semiconductor substrate (Koshimizu, Figure 18 annotated, [0071], #GI is formed to cover the surface #CON of #SB which is part of #SB1 such that it has a top surface above #SB2; Huang, Figure 2A annotated, #24 has a top planar surface in above the top surface of #21’).
Regarding Claim 19. Koshimizu in view of Huang discloses the structure of claim 10, wherein the second device comprises a laterally-diffused metal-oxide semiconductor device (Koshimizu, Figure 18 annotated, the Right LDMOS transistor is a Laterally Diffused Metal Oxide Semiconductor device) and the first device comprises a logic device (Koshimizu, Figure 18 annotated, the MOS transistor is a transistor which is necessarily a logic device).
Regarding Claim 20. Koshimizu discloses a method (Figure 18, [0129]-[0134]) comprising:
Forming a first device (MOS transistor, Figure 18) on a semiconductor substrate (#SB, Figure 18, [0038], semiconductor substrate that MOS is formed on); and
forming a second device (Right LDMOS, Figure 18 annotated) on the semiconductor substrate (Figure 18 annotated, Right LDMOS is formed on #SB), the second device the second device being formed with a recessed channel region (#RC, Figure 18 annotated) below a surface of the first device (Figure 18 annotated, #RC is below a surface of the MOS transistor) the recessed channel region being defined by a sidewall of the semiconductor substrate and a shallow trench isolation structure (Figure 18 annotated, the #RC of the right LDMOS is defined by a sidewall of #SB on its left side and a shallow trench isolation structure, #BI trench insulating layer, on its right side),
wherein the second device (Right LDMOS, Figure 18 annotated) comprises a gate insulator material (#GI, Figure 18 annotated, gate insulator) and a gate electrode (#GE, Figure 18 annotated, gate electrode) on the gate insulator material (Figure 18, #GE is on #GI) confined within the recessed channel region in the horizontal direction (Figure 18, #GE is confined in #RC in a horizontal direction).
Koshimizu does not disclose that the second device comprises a gate insulator material having a first thickness thicker than a second thickness with both the first thickness and the second thickness of the gate insulator material being confined within the recessed channel region in a horizontal direction, and the gate insulator material with the first thickness confined within the recessed channel region in the horizontal direction extends above a height of the recessed channel region in a vertical direction, and the gate insulator material contacts the sidewall of the semiconductor substrate within the recessed channel region and is separated from the shallow trench isolation structure by a space between the second thickness of the gate insulator material and the shallow trench isolation structure thereby exposing the semiconductor substrate within the recessed channel region.
However, Huang teaches a device (#200, Figure 2A, high voltage device) on a semiconductor substrate (#21 and #21’, Figure 2A, [0040], “semiconductor layer 21′ . . . is a part of the substrate 21”), the device comprising a recessed channel region (#23a, Figure 2A, operation region) below a surface of the substrate (Figure 2A, #23a is recessed below an uppermost surface of #21’), the recessed channel region being defined by a sidewall of the semiconductor substrate and a shallow trench isolation structure (Figure 2A, let #23a be bounded on the left by isolation region #23 and bounded on the right by #29 see annotated Figure 2A above),
wherein the device comprises a gate insulator material (#271 and #24, Figure 2A, dielectric layer and drift oxide region) having a first thickness (Figure 2A, #24 has a first thickness) thicker than a second thickness (Figure 2A, #271 has a second thickness under #272 such that the thickness of #24 is greater) with both the first thickness and the second thickness of the gate insulator material being confined within the recessed channel region in a horizontal direction (Figure 2A annotated, both #24 and #271 are confined within the recessed channel region in the horizontal direction),
a gate electrode (#272 of #27, Figure 2A, conductive layer of the gate) on the gate insulator material (Figure 2A, #272 is on both #271 and #24) also confined within the recessed channel region in the horizontal direction (Figure 2A annotated, #272 is confined within the recessed channel region in the horizontal direction),
the gate insulator material with the first thickness confined within the recessed channel region in the horizontal direction extends above a height of the recessed channel region in a vertical direction (Figure 2A annotated, #24 extends above a height of the recessed channel region in the vertical direction), and
the gate insulator material contacts the sidewall of the semiconductor substrate within the recessed channel region (Figure 2A annotated, #24 contacts the sidewall of #21’ within the recessed channel region) and is separated from the shallow trench isolation structure by a space between the second thickness of the gate insulator material and the shallow trench isolation structure thereby exposing the semiconductor substrate within the recessed channel region (Figure 2A annotated, #271 is separated from #23 by a space between #271 and the left #23 to expose a surface of #21’ within the recessed channel region).
It would have been obvious to one or ordinary skill in the art before the effective filing date of the claimed invention to consider forming the high breakdown voltage device of Huang as the high breakdown voltage LDMOS of Koshimizu as the device in Huang is beneficial for reducing the conductive resistance and withstanding a higher operation volage (see [0006], [0042], and [0054] of Huang).
Regarding Claim 21. Koshimizu in view of Huang discloses the structure of claim 10, wherein the stepped feature comprises a first thickness (Huang, Figure 2A, #271 has a thickness) adjacent to a source region (Huang, Figure 2A, source region #28 is recessed below the surface of the substrate #21’) of the second device (Huang, Figure 2A, #271 is closer to #28) and a second thickness (Huang, Figure 2A, #24 has a first thickness) adjacent to a raised drain region (Huang, Figure 2A, drain region #29 is raised to the top of the substrate such that current follows the upward motion of the arrow; Koshimizu, Figure 18, raised drain region #DR) of the second device (Huang, Figure 2A, #24 is closer to #29).
Regarding Claim 22. Koshimizu in view of Huang discloses the structure of claim 10, wherein the first thickness is different from the second thickness (Figure 2A, #271 has a second thickness under #272 such that the thickness of #24 is greater).
Response to Arguments/Amendments
Applicant’s amendments to claim 22 and corresponding remarks, see page 6 of the remarks, filed 09/26/2025, with respect to the objection to claims 22 have been fully considered. The objection to claim 22 has been withdrawn.
Applicant’s amendments to claims 1, 10, and 20 and corresponding remarks, see page 6 of the remarks, filed 09/26/2025, with respect to the 35 U.S.C. 112(b) rejections of claims 1-4 and 6-22 have been fully considered. The 35 U.S.C. 112(b) rejections of claims 1-4 and 6-22 have been withdrawn.
Applicant’s amendments to claims 1, 10, and 20, see pages 6-10 of the remarks, filed 09/26/2025, with respect to the 35 U.S.C. 103 rejections of claims 1, 10, and 20, along with their corresponding dependent claims, have been fully considered and are persuasive. The originally cited references do not appear to teach the amended limitations to the independent claims. The original 35 U.S.C. 103 rejections of claims 1-4 and 6-22 have been withdrawn. However, applicant’s amendment to the independent claims has led to the introduction of new art. US 2020/0119189 A1; Huang et al.; 04/2020; (“Huang”) teaches the all of the amended limitations not taught by the previous references and provides the necessary motivation to combine with as described above. Claim(s) 1-4 and 6-22 stand rejected under 35 U.S.C. 103 as being unpatentable over US 2023/0065925 A1; Koshimizu et al.; 03/2023; (“Koshimizu”) in view of US 2020/0119189 A1; Huang et al.; 04/2020; (“Huang”).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/TYLER J WIEGAND/Examiner, Art Unit 2812
/CHRISTINE S. KIM/Supervisory Patent Examiner, Art Unit 2812