CTNF 18/615,490 CTNF 91545 Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. DETAILED ACTION Claims 1-20 are pending and have been examined. Priority Acknowledgment is made that the instant application is a continuation of application 17887903 filed on 08/15/2022, application 17887903 is a divisional of application 16725643 filed on 12/23/2019 and application 16725643 has a provisional 62785136 filed on 12/26/2018. Double Patenting 08-33 AIA The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg , 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman , 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi , 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum , 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel , 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington , 418 F.2d 528, 163 USPQ 644 (CCPA 1969). A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP §§ 706.02(l)(1) - 706.02(l)(3) for applications not subject to examination under the first inventor to file provisions of the AIA. A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b). The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA/25, or PTO/AIA/26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/process/file/efs/guidance/eTD-info-I.jsp. Claims 1, 4-8, 10-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1, 3-4, 6, 8, 11-15, 17-18 of the U.S. Patent No. US 11417381 B2. Although the claims at issue are not identical, they are not patentably distinct from each other because they are simple changes of a statutory category. A person of ordinary skill in the art would conclude that the invention defined in the claims at issue would have been obvious variation of the invention defined in the claims of the U.S. Patent No. US 11417381 B2. The following table compares the limitations of the claim/claims of the instant application 18615490 and patentably non-distinct claim/claims of the U.S. Patent No. US 11417381 B2. Instant Application: 18615490 U.S. Patent No. US 11417381 B2 Claim 1. An apparatus comprising: a first conductive region; a second conductive region located over the first conductive region; a third conductive region located over the second conductive region and separated from the first and second conductive regions; a memory cell coupled to the first, second, and third conductive regions, the memory cell including: a first material between the first and second conductive regions and coupled to the first and second conductive regions; a second material located over the second conductive region, the second material separated from the first material and the first and second conductive regions and coupled to the third conductive region; and a memory element coupled to the second material and separated from the first material and first and second conductive regions. Claim 1. An apparatus comprising: a first data line located over a substrate; a second data line located over the first data line; a third data line located over the second data line and electrically separated from the first and second data lines; a memory cell coupled to the first, second, and third data lines, the memory cell including: a first material between the first and second data lines and electrically coupled to the first and second data lines; a second material located over the first data line and the first material, the second material electrically separated from the first material and electrically coupled to the third data line; and a memory element electrically coupled to the second material and electrically separated from the first material and first and second data lines. Claim 4. The apparatus of claim 1, wherein the second material includes a piece of semiconductor material. Claim 3. The apparatus of claim 1, wherein the second material includes a piece of semiconductor material. Claim 5. The apparatus of claim 4, wherein the memory element includes a piece of semiconductor material contacting the second material. Claim 4. The apparatus of claim 3, wherein the memory element includes a piece of semiconductor material contacting the second material. Claim 6. The apparatus of claim 4, wherein the memory element includes a piece of metal contacting the second material. Claim 4. The apparatus of claim 3, wherein the memory element includes a piece of semiconductor material contacting the second material. Claim 7. The apparatus of claim 1, wherein the second material includes at least one of zinc tin oxide (ZTO), indium zinc oxide (IZO), zinc oxide (ZnOx), indium gallium zinc oxide (IGZO), indium gallium silicon oxide (IGSO), indium oxide (InOx,In203), tin oxide (SnO2), titanium oxide (TiOx), zinc oxide nitride (ZnxOyNz), magnesium zinc oxide (MgxZnyOz), indium zinc oxide (InxZnyOz), indium gallium zinc oxide (InxGayZnzOa), zirconium indium zinc oxide (ZrxInyZnzOa), hafnium indium zinc oxide (HfxInyZnzOa), tin indium zinc oxide (SnxInyZnzOa), aluminum tin indium zinc oxide (AlxSnyInzZnaOd), silicon indium zinc oxide (SixInyZnzOa), zinc tin oxide (ZnxSnyOz), aluminum zinc tin oxide (AlxZnySnzOa), gallium zinc tin oxide (GaxZnySnzOa), zirconium zinc tin oxide (ZrxZnySnzOa), indium gallium silicon oxide (InGaSiO), and gallium phosphide (GaP). Claim 6. The apparatus of claim 1, wherein the second material includes at least one of zinc tin oxide (ZTO), indium zinc oxide (IZO), zinc oxide (ZnO.sub.x), indium gallium zinc oxide (IGZO), indium gallium silicon oxide (IGSO), indium oxide (InO.sub.x, In.sub.2O.sub.3), tin oxide (SnO.sub.2), titanium oxide (TiO.sub.x), zinc oxide nitride (Zn.sub.xO.sub.yN.sub.z), magnesium zinc oxide (Mg.sub.xZn.sub.yO.sub.z), indium zinc oxide (In.sub.xZn.sub.yO.sub.z), indium gallium zinc oxide (In.sub.xGa.sub.yZn.sub.zO.sub.a), zirconium indium zinc oxide (Zr.sub.xIn.sub.yZn.sub.zO.sub.a), hafnium indium zinc oxide (Hf.sub.xIn.sub.yZn.sub.zO.sub.a), tin indium zinc oxide (Sn.sub.xIn.sub.yZn.sub.zO.sub.a), aluminum tin indium zinc oxide (Al.sub.xSn.sub.yIn.sub.zZn.sub.aO.sub.d), silicon indium zinc oxide (Si.sub.xIn.sub.yZn.sub.zO.sub.a), zinc tin oxide (Zn.sub.xSn.sub.yO.sub.z), aluminum zinc tin oxide (Al.sub.xZn.sub.ySn.sub.zO.sub.a), gallium zinc tin oxide (Ga.sub.xZn.sub.ySn.sub.zO.sub.a), zirconium zinc tin oxide (Zr.sub.xZn.sub.ySn.sub.zO.sub.a), indium gallium silicon oxide (InGaSiO), and gallium phosphide (GaP). Claim 8. An apparatus comprising: a first conductive region; a second conductive region separated from the first conductive region; a third conductive region separated from the first and second conductive regions; a memory cell coupled to the first, second, and third conductive regions, the memory cell including: a first material between the first and second conductive regions and coupled to the first and second conductive regions; a second material located between the second and third conductive regions and contacting the third conductive region; and a memory element coupled to the second material and separated from the first material and first and second conductive regions. Claim 13. An apparatus comprising: a first data line; a second data line; a third data line; and a memory cell coupled to the first, second, and third data lines, the memory cell including: a first transistor including a first region contacting the first and second data lines, and a charge storage structure electrically separated from the first region; and a second transistor including a second region electrically separated from the first region, the second region contacting the charge storage structure and contacting the third data line; a first conductive line including a portion adjacent the first region; and a second conductive line including a portion adjacent the second region. Claim 10. The apparatus of claim 9, wherein each of the first and second portions of the memory element includes a piece of semiconductor material. Claim 8. The apparatus of claim 7, wherein each of the first and second portions of the memory element includes a piece of semiconductor material. Claim 11. The apparatus of claim 9, wherein each of the first and second portions of the memory element includes a piece of metal. Claim 8. The apparatus of claim 7, wherein each of the first and second portions of the memory element includes a piece of semiconductor material. Claim 12. The apparatus of claim 8, further comprising: a first conductive material including a portion located on a first side of the first material; a first additional conductive material including a portion located on a second side of the first material; a second conductive material including a portion located on a first side of the second material; a second additional conductive material including a portion located on a second side of the second material. Claim 13. An apparatus comprising: a first data line; a second data line; a third data line; and a memory cell coupled to the first, second, and third data lines, the memory cell including: a first transistor including a first region contacting the first and second data lines, and a charge storage structure electrically separated from the first region; and a second transistor including a second region electrically separated from the first region, the second region contacting the charge storage structure and contacting the third data line; a first conductive line including a portion adjacent the first region; and a second conductive line including a portion adjacent the second region. Claim 13. The apparatus of claim 12, wherein each of the first and second conductive regions has a length in a first a first direction, and each of the first conductive material, first additional conductive material, second conductive material, and second additional conductive material is part of a conductive line having a length in a second direction. Claim 11. The apparatus of claim 10, wherein each of the first and second data lines has a length in a first a first direction, and each of the first conductive material, first additional conductive material, second conductive material, and second additional conductive material is part of a conductive line having a length in a second direction. Claim 14. The apparatus of claim 13, wherein the conductive line is part of an access line of the apparatus. Claim 12. The apparatus of claim 11, wherein the conductive line is part of an access line of the apparatus. Claim 15. An apparatus comprising: a first conductive region; a second conductive region; a third conductive region; and a memory cell coupled to the first, second, and third conductive regions, the memory cell including: a first transistor including a first region contacting the first and second conductive regions, and a charge storage structure electrically separated from the first region; and a second transistor including a second region electrically separated from the first region, the second region contacting the charge storage structure and contacting the third conductive region; a first conductive line including a portion adjacent the first region; and a second conductive line including a portion adjacent the second region. Claim 13. An apparatus comprising: a first data line; a second data line; a third data line; and a memory cell coupled to the first, second, and third data lines, the memory cell including: a first transistor including a first region contacting the first and second data lines, and a charge storage structure electrically separated from the first region; and a second transistor including a second region electrically separated from the first region, the second region contacting the charge storage structure and contacting the third data line; a first conductive line including a portion adjacent the first region; and a second conductive line including a portion adjacent the second region. Claim 16. The apparatus of claim 15, wherein the first and second conductive lines are coupled to each other. Claim 14. The apparatus of claim 12, wherein the first and second conductive lines are electrically coupled to each other. Claim 17. The apparatus of claim 15, wherein the second region includes a piece of oxide material, and the charge storage structure includes a piece of semiconductor material contacting the piece of oxide material. Claim 15. The apparatus of claim 12, wherein the second region includes a piece of oxide material, and the charge storage structure includes a piece of semiconductor material contacting the piece of oxide material. Claim 18. The apparatus of claim 15, wherein the second region includes a piece of oxide material, and the charge storage structure includes a piece of metal contacting the piece of oxide material. Claim 15. The apparatus of claim 12, wherein the second region includes a piece of oxide material, and the charge storage structure includes a piece of semiconductor material contacting the piece of oxide material. Claim 19. The apparatus of claim 15, wherein the first region includes a piece of semiconductor material. Claim 17. The apparatus of claim 12, wherein the first region includes a piece of semiconductor material. Claim 20. The apparatus of claim 15, wherein the first region includes a piece of metal. Claim 18. The apparatus of claim 12, wherein the first region includes a piece of metal. Allowable Subject Matter 12-151-08 AIA 07-43 12-51-08 Claim s 2-3, 9 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The following is the Examiner’s Reasons for Allowance: The prior art fails to disclose and would not have rendered obvious: Regarding claim 2: The apparatus of claim 1, further comprising: a first conductive material including a portion located on a first side of the first material; and a second conductive material including a portion located on a first side of the second material. Regarding claim 3: The apparatus of claim 2, further comprising: a first additional conductive material including a portion located on a second side of the first material; and a second additional conductive material including a portion located on a second side of the second material. Regarding claim 9: The apparatus of claim 8, wherein the memory element includes: a first portion located on a first side of the first material and a first side of the second conductive region; and a second portion located on a second side of the first material and a second side of the second conductive region. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to MOHAMMAD A. RAHMAN whose telephone number is (571) 270-0168 and email is mohammad.rahman5@uspto.gov. The examiner can normally be reached on Mon-Fri 8:00-5:00 PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Julio J. Maldonado can be reached on (571) 272-1864. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see https://ppair-my.uspto.gov/pair/PrivatePair. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /MOHAMMAD A RAHMAN/ Examiner, Art Unit 2898 Application/Control Number: 18/615,490 Page 2 Art Unit: 2898 Application/Control Number: 18/615,490 Page 3 Art Unit: 2898 Application/Control Number: 18/615,490 Page 4 Art Unit: 2898 Application/Control Number: 18/615,490 Page 5 Art Unit: 2898 Application/Control Number: 18/615,490 Page 6 Art Unit: 2898 Application/Control Number: 18/615,490 Page 7 Art Unit: 2898 Application/Control Number: 18/615,490 Page 8 Art Unit: 2898 Application/Control Number: 18/615,490 Page 9 Art Unit: 2898 Application/Control Number: 18/615,490 Page 10 Art Unit: 2898 Application/Control Number: 18/615,490 Page 11 Art Unit: 2898
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