DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant's election with traverse of Group I (claims 1-12) in the reply filed on July 7, 2026 is acknowledged. The traversal is on the ground(s) that claim 13 of Group II should be rejoined upon allowance of Group I.
The requirement is still deemed proper and is therefore made FINAL.
Drawings
The drawings are objected to as failing to comply with 37 CFR 1.84(p)(5) because they do not include the following reference sign(s) mentioned in the description:
“44” in par. 0109, 0127.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 11 rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Specifically, the claim refers to a “tubular portion” that has no clearly identified structure in the drawings as element “44” of par. 0109, 0127 does not appear.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3, 5, and 8-12 are rejected under 35 U.S.C. 103 as being unpatentable over Sharangpani et al. (2020/0194445, hereafter Sharangpani) in view of Lee et al. (2016/0163686, hereafter Lee).
Regarding claim 1, Sharangpani discloses a memory device, comprising: an alternating stack of insulating layers and electrically conductive layers (par. 0069); a memory opening vertically extending through the alternating stack (par. 0069); and a memory opening fill structure located in the memory opening and comprising, from outside to inside, a memory film containing a vertical stack of memory elements (50, Fig. 7D, par. 0114), a vertical semiconductor channel (60, Fig. 7D, par. 0116), a dielectric liner (261, Fig. 7D, par. 0134), and a silicon oxide core (262, Fig. 7D, par. 0135).
Sharangpani fails to disclose a core-side charge trapping material layer.
However, Lee teaches a core-side charge trapping material layer (150, Fig. 8A; par. 0102, 0114).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify Sharangpani with Lee by implementing a core-side charge-trapping layer in order to provide stable, high-density, non-volatile data storage with low leakage current and improved scalability to floating-gate transistors.
Regarding claim 2, Sharangpani fails to disclose the core-side charge trapping material layer comprises silicon nitride.
However, Lee teaches a core-side charge trapping material layer (150, Fig. 8A; par. 0102, 0114).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify Sharangpani with Lee by implementing a core-side charge-trapping layer in order to provide stable, high-density, non-volatile data storage with low leakage current and improved scalability to floating-gate transistors.
Further, Sharangpani teaches a charge trapping material layer comprises silicon nitride (par. 0107).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify Sharangpani by providing a charge-trapping layer comprising silicon nitride in order to allow capture and storage of charge, forming localized, non-volatile storage layer
Regarding claim 3, Sharangpani fails to disclose a memory device wherein the core-side charge trapping material layer comprises aluminum oxide.
However, Lee teaches a memory device wherein the core-side charge trapping material layer (150, Fig. 8A) comprises aluminum oxide (par. 0102).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify Sharangpani with Lee by providing a core-side charge trapping layer with aluminum oxide in order to prevent stored electrons from leaking into gate, enabling lower voltages, higher retention, and improved stability.
Regarding claim 5, Sharangpani fails to disclose a memory device wherein the core-side charge trapping material layer comprises a layer stack.
However, Lee teaches a core-side charge trapping material layer (150, Fig. 8A; par. 0102, 0114).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify Sharangpani with Lee by implementing a core-side charge-trapping layer in order to provide stable, high-density, non-volatile data storage with low leakage current and improved scalability to floating-gate transistors.
Further, Sharangpani teaches a charge trapping material layer comprises a layer stack (par. 0109).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify Sharangpani by providing a charge-trapping layer as a layer stack in order to allow electrons to tunnel easily during programming while effectively trapping and blocking them during storage.
Regarding claim 8, Sharangpani discloses a silicon oxide core (262, Fig. 7D, par. 0135).
Sharangpani fails to disclose a memory device wherein the silicon oxide core comprises an as deposited core.
However, Lee teaches a memory device wherein the core (140, Fig. 8A) comprises an as deposited core (par. 0094).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify Sharangpani with Lee by providing an as deposited core in order to enable uniform, conformal filling without exceeding thermal parameters causing damage.
Regarding claim 9, Sharangpani discloses a memory device wherein the dielectric core comprises silicon oxide (262, Fig. 7D, par. 0135).
Sharangpani fails to disclose the core is in direct contact with an inner sidewall of the core-side charge trapping material layer.
However, Lee teaches the core (140) is in direct contact with an inner sidewall of the core-side charge trapping material layer (150) (Fig. 8A).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify Sharangpani with Lee by providing a charge-trapping layer contacting the core in order to provide stable, high-density, non-volatile data storage with low leakage current and improved scalability to floating-gate transistors
Regarding claim 10, Sharangpani discloses a memory device wherein the memory film (50) comprises a layer stack (par. 0103) that comprises a tunneling dielectric layer (56) in contact with an outer sidewall of the vertical semiconductor channel (601), a charge storage layer (54) in contact with an outer sidewall of the tunneling dielectric layer, and a blocking dielectric layer (52) in contact with an outer sidewall of the charge storage layer (Fig. 7D).
Regarding claim 11, Sharangpani discloses a memory device of wherein each of the electrically conductive layers (46, Fig. 14D, par. 0173) is laterally spaced from the blocking dielectric layer (52) by a respective outer blocking dielectric layer (44) having a respective tubular portion, a respective upper horizontally-extending portion that is adjoined to an upper end of the respective tubular portion, and a respective lower horizontally-extending portion that is adjoined to a lower end of the respective tubular portion (Fig. 14D).
Regarding claim 12, Sharangpani fails to disclose a memory device wherein the memory opening fill structure further comprises a drain region that contacts an annular top surface of the core-side charge trapping material layer and an end portion of the vertical semiconductor channel.
However, Sharangpani teaches memory device wherein the memory opening fill structure further comprises a drain region (63, Fig. 7D, par. 0126) that contacts an annular top surface of a layer (261) and an end portion of the vertical semiconductor channel (602) (Fig. 7D).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify Sharangpani by providing a drain region contacting the top of a layer in order to provide the field necessary to draw channel carriers through core during operations
Further, Lee teaches the core-side charge trapping material (150, Fig. 8A).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify Sharangpani with Lee by implementing a core-side charge-trapping layer in order to provide stable, high-density, non-volatile data storage with low leakage current and improved scalability to floating-gate transistors.
Claims 4, 6, and 7 are rejected under 35 U.S.C. 103 as being unpatentable over Sharangpani in view of Lee as applied to claim 1 above, and further in view of Song et al. (2020/0185408, hereafter Song).
Regarding claim 4, Sharangpani, discussed above, fails to disclose memory device wherein the core-side charge trapping material layer comprises silicon oxynitride.
However, Lee teaches the core-side charge trapping material (150, Fig. 8A).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify Sharangpani with Lee by implementing a core-side charge-trapping layer in order to provide stable, high-density, non-volatile data storage with low leakage current and improved scalability to floating-gate transistors.
Further, Sharangpani and Lee fail to disclose a charge trapping material layer comprises silicon oxynitride.
However, Song teaches a charge trapping material layer comprises silicon oxynitride (par. 0063).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify Sharangpani and Lee with Song by providing a charge-trapping layer including silicon oxynitride in order to fine-tune energy bandgap and trap depths, offering balance between program/erase speeds, charge retention, and reduced defect stress.
Regarding claim 6, Sharangpani and Lee fail to disclose a memory device wherein the layer stack comprises a first silicon nitride layer, a second silicon nitride layer, and a silicon oxynitride layer located between the first and the second silicon nitride layers.
However, Song teaches a memory device wherein the layer stack comprises a first silicon nitride layer, a second silicon nitride layer, and a silicon oxynitride layer located between the first and the second silicon nitride layers (par. 0063).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify Sharangpani and Lee with Song by providing a charge trapping layer with a silicon nitride, silicon oxynitride, silicon nitride stack in order to create stepped energy band profile, optimizing charge capture while smoothing the internal field, enhancing speed, stability, and endurance.
Regarding claim 7, Sharangpani fails to disclose a memory device wherein the dielectric liner comprises a silicon oxide liner in contact with the core-side charge trapping material layer and an inner sidewall of the vertical semiconductor channel.
However, in a different embodiment, Sharangpani teaches memory device wherein the dielectric liner (161, Fig. 5H) comprises a silicon oxide liner (par. 0117) and contacts an inner sidewall of the vertical semiconductor channel (602, Fig. 5H).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify Sharangpani by providing a liner with silicon oxide contacting the semiconductor channel because its energy band offset creates a stable potential barrier that allows controlled electron tunneling under high electron fields curing program/erase operations while preventing unwanted leakage under low fields.
Further, Lee teaches a core-side charge trapping material layer (150, Fig. 8A; par. 0102, 0114).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify Sharangpani with Lee by implementing a core-side charge-trapping layer in order to provide stable, high-density, non-volatile data storage with low leakage current and improved scalability to floating-gate transistors.
Finally, Song teaches a silicon oxide (212, Fig. 1C-1, par. 0062) liner in contact with the charge trapping material layer (210, Fig. 1C-1).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify Sharangpani and Lee with Song by providing a silicon oxide liner in contact with a charge-trapping layer in order to separate the charge-trapping layer from channel, enabling precise control over carrier injection while preventing charge leakage.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHARLES M BRECHT whose telephone number is (571)272-9634. The examiner can normally be reached Mon-Fri: 7:30am - 5pm.
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/C.M.B./Examiner, Art Unit 2817
/MARLON T FLETCHER/Supervisory Primary Examiner, Art Unit 2817
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