DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Drawings
Figure 1 should be designated by a legend such as --Prior Art-- because only that which is old is illustrated. See MPEP § 608.02(g). Corrected drawings in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. The replacement sheet(s) should be labeled “Replacement Sheet” in the page header (as per 37 CFR 1.84(c)) so as not to obstruct any portion of the drawing figures. If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Election/Restrictions
Applicant’s election without traverse of Invention I, directed to claims 1-9 and 15-20 in the reply filed on 07/15/2026 is acknowledged.
Claims 10-14 withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected device, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 07/15/2026.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-3 and 6-9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chang et al. (US 20220102163 A1), hereinafter referred to as Chang163, in view of Nallan (US 20020132488 A1) hereinafter referred to as Nallan488.
Regarding claim 1: Chang163 teaches a substrate processing method for etching a thin film formed on a substrate (“Further described is metal nitride etching system for etching a metal nitride film disposed on a substrate”, para. [0025]) at an atomic layer level (“thereby oxidizing a surface layer of the metal nitride layer, thus forming a metal oxide surface layer overlying an unaffected metal nitride layer”, [para. 0005]), the substrate processing method comprising: a surface modification step of modifying a surface of the thin film by supplying a first gas including oxygen (O) to a processing space of a chamber in which the substrate is placed (“a reaction chamber configured to hold and process a substrate, the substrate comprising a metal nitride layer; a gaseous oxidizing agent source comprising a gaseous oxidizing agent selected from the list consisting of O.sub.2, O.sub.3, H.sub.2O, and H.sub.2O.sub.2, the gaseous oxidizing agent source being configured to provide the gaseous oxidizing agent to the reaction chamber in an oxidizing agent pulse;”, para. [0025]); a first purge step of removing the first gas remaining in the processing space by supplying a purge gas to the processing space (See Fig. 10, oxidizing agent purge step 1125, see para. [0131]); an etching step of etching the modified thin film by supplying a gas to the processing space (See Fig. 10, provide a gaseous etchant to the etching chamber step 1130, see para. [0131]; and a second purge step of removing the gas remaining in the processing space by supplying the purge gas to the processing space (See Fig. 10, etchant purge step 1135, see para. [0131]).
Chang163 teaches that the etchant gas may comprise a halogen such as chlorine or fluorine (See paras. [0012-0016]. However, Chang163 does not explicitly teach CHF.sub.3 as a suitable etching gas.
Nallan488 teaches CHF.sub.3 as an etching gas for tantalum nitride (“If the organic fluorine-comprising gas also contains hydrogen (i.e., has the chemical formula C.sub.xH.sub.yF.sub.z, for example, CHF.sub.3 or CH.sub.2F.sub.2), the amount of sidewall passivation will be increased. In this case, the relative amount of the inorganic fluorine-comprising gas to the C.sub.xH.sub.yF.sub.z gas should be increased in order to provide the optimum balance between etch rate and sidewall passivation.”, para. [0014]).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention, that the chosen etch gas for the method disclosed in Chang163 would be based on the materials of the substrate. A person of ordinary skill in the art would be motivated to look to the prior art to see which etching gases where being used in conjunction with the chosen materials, such as tantalum nitride, and could conclude that the element of the purge gas CHF.sub.3 disclosed in Nallan488 could be substituted into the method of Chang163, replacing the halogen and fluorine containing etching gas with CHF.sub.3, to yield predictable results.
Regarding claim 2: In addition to the reasoning used to reject claim 1, the method of Chang163 teaches a cycle including the surface modification step to the second purge step is repeated at least 1 time (See Fig. 10, dashed arrow shows that the process steps 1120—1135 may be repeated, see para. [0131], “are repeated thus resulting in a cyclical process comprising a plurality of etching and deposition steps which are optionally separated by purges.”).
Regarding claim 3: In addition to the reasoning used to reject claim 1, the method of Chang163 teaches that the thin film is a tantalum nitride film. (“In some embodiments, the metal nitride layer comprises a metal nitride selected from the list consisting of hafnium nitride, titanium nitride, vanadium nitride, tantalum nitride, zirconium nitride, yttrium nitride, niobium nitride, copper nitride, molybdenum nitride, and tungsten nitride.”, para. [0007])
Regarding claim 6: In addition to the reasoning used to reject method of claim 1, Chang163 teaches that the first gas includes at least one of O.sub.2 and O.sub.3. (“a gaseous oxidizing agent source comprising a gaseous oxidizing agent selected from the list consisting of O.sub.2, O.sub.3, H.sub.2O, and H.sub.2O.sub.2, the gaseous oxidizing agent source being configured to provide the gaseous oxidizing agent to the reaction chamber in an oxidizing agent pulse;”, para. [0025]);
Regarding claim 7: In addition to the reasoning used to reject claim 1, Chang163 teaches that the surface modification step and the etching step are performed in a state in which a plasma is generated in the processing space. (“In some embodiments, the metal nitride etching system further comprises a plasma source, the plasma source being configured for exciting the gaseous oxidizing agent and/or the gaseous etchant, thus forming an excited gaseous oxidizing agent and/or an excited gaseous etchant.”, para. [0027]).
Regarding claim 8: In addition to the reasoning used to reject claim 1, Chang163 teaches that the surface modification step to the second purge step is performed in a state in which the substrate is heated to a predetermined temperature. (“In some embodiments, the reactor chamber is maintained, at least while executing the method, at a temperature of less than 450° C., or at a temperature of at least 50° C. to at most 450° C”, para. [0102]).
Regarding claim 9: In addition to the reasoning used to reject claim 8, Chang 163 teaches a range that overlaps with the claimed temperature is range of 100°C to 150°C (“In some embodiments, the reactor chamber is maintained, at least while executing the method, at a temperature of less than 450° C., or at a temperature of at least 50° C. to at most 450° C”, para. [0102]). MPEP 2144.05 I states: “In the case where the claimed ranges overlap or lie inside ranges disclosed by the prior art a prima facie case of obviousness exists.”. The examiner also notes that an etch rate determined by the temperature is well-known in the art (See citation of pertinent prior art).
Claim(s) 4-5 and 15-19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chang et al. (US 20220102163 A1), hereinafter referred to as Chang163, in view of Nallan (US 20020132488 A1) hereinafter referred to as Nallan488 and further in view of Chen et al. (US 20230386830 A1) hereinafter referred to as Chen830.
Regarding claim 4: The method of claim 3 is obvious in view of the teachings of Chang163 and Nallan488, however they do not teach that the substrate includes at least one of a silicon oxide film and a silicon nitride film.
Chen830 teaches etching methods for a 3D NAND device containing silicon oxide and silicon nitride films (“For example, in some structures, alternating layers of silicon oxide and silicon may be used, or alternating layers of silicon oxide and silicon nitride,”, para. [0023]) and also suggests a need to etch metal lining layers including tantalum nitride (“If a liner material is utilized when forming the stacked layers, such as an aluminum oxide, hafnium oxide, titanium nitride, tantalum nitride, or hafnium nitride liner formed between silicon oxide and molybdenum, the liner may also need to be removed.”, para. [0023]).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention, that the etching method disclosed by Chang163 using the etching gas disclosed in Nallan488, could be applied to a variety of semiconductor devices, a 3D NAND being just one that contains a silicon oxide or silicon nitride film, for example, to etch a liner layer of tantalum nitride. The etching methods taught by Chen830 are also substantially the same as those disclosed by Chang163 and Nallan488, exposing it to a plasma of halide etching gas to etch the metal layer, therefore the claimed invention is merely the combination of known prior art elements with predictable results.
Regarding claim 5: In addition to the reasoning used to reject claim 4, Chen830 teaches the substrate includes a stacked film in which the silicon oxide film and the silicon nitride film are alternately stacked (“For example, in some structures, alternating layers of silicon oxide and silicon may be used, or alternating layers of silicon oxide and silicon nitride,”, para. [0023]), wherein the tantalum nitride film is formed in an opening formed through the stacked film. (“If a liner material is utilized when forming the stacked layers, such as an aluminum oxide, hafnium oxide, titanium nitride, tantalum nitride, or hafnium nitride liner formed between silicon oxide and molybdenum, the liner may also need to be removed.”, para. [0023]).
Regarding claim 15: Chang163 teaches A substrate processing method for etching a thin film formed on a substrate (“Further described is metal nitride etching system for etching a metal nitride film disposed on a substrate”, para. [0025]) at an atomic layer level (“thereby oxidizing a surface layer of the metal nitride layer, thus forming a metal oxide surface layer overlying an unaffected metal nitride layer”, [para. 0005]), the substrate processing method comprising: a surface modification step of modifying a surface of the thin film by supplying a first gas including oxygen (O) to a processing space of a chamber ((“a reaction chamber configured to hold and process a substrate, the substrate comprising a metal nitride layer; a gaseous oxidizing agent source comprising a gaseous oxidizing agent selected from the list consisting of O.sub.2, O.sub.3, H.sub.2O, and H.sub.2O.sub.2, the gaseous oxidizing agent source being configured to provide the gaseous oxidizing agent to the reaction chamber in an oxidizing agent pulse;”, para. [0025]); a first purge step of removing the first gas remaining in the processing space by supplying a purge gas to the processing space (See Fig. 10, oxidizing agent purge step 1125, see para. [0131]); an etching step of etching the modified thin film by supplying a gas to the processing space (See Fig. 10, provide a gaseous etchant to the etching chamber step 1130, see para. [0131]); and a second purge step of removing the gas remaining in the processing space by supplying the purge gas to the processing space (See Fig. 10, etchant purge step 1135, see para. [0131]), wherein the first gas includes at least one of O.sub.2 and O.sub.3 (“a gaseous oxidizing agent source comprising a gaseous oxidizing agent selected from the list consisting of O.sub.2, O.sub.3, H.sub.2O, and H.sub.2O.sub.2, the gaseous oxidizing agent source being configured to provide the gaseous oxidizing agent to the reaction chamber in an oxidizing agent pulse;”, para. [0025]), and one cycle defined from the surface modification step to the second purge step is repeated at least 1 time (See Fig. 10, dashed arrow shows that the process steps 1120—1135 may be repeated, see para. [0131], “are repeated thus resulting in a cyclical process comprising a plurality of etching and deposition steps which are optionally separated by purges.”) and is performed while maintaining the substrate at a temperature range that overlaps with the claimed temperature range of 100°C to 150°C (“In some embodiments, the reactor chamber is maintained, at least while executing the method, at a temperature of less than 450° C., or at a temperature of at least 50° C. to at most 450° C”, para. [0102]). MPEP 2144.05 I states: “In the case where the claimed ranges overlap or lie inside ranges disclosed by the prior art a prima facie case of obviousness exists.” The examiner also notes that an etch rate determined by the temperature is well-known in the art (See citation of pertinent prior art).
Chang163 teaches that the etchant gas may comprise a halogen such as chlorine or fluorine (See paras. [0012-0016]. However, Chang163 does not explicitly teach CHF.sub.3 as a suitable etching gas. Chang163 does not explicitly teach the method is for manufacturing 3D NAND devices.
Nallan488 teaches CHF.sub.3 as an etching gas for tantalum nitride (“If the organic fluorine-comprising gas also contains hydrogen (i.e., has the chemical formula C.sub.xH.sub.yF.sub.z, for example, CHF.sub.3 or CH.sub.2F.sub.2), the amount of sidewall passivation will be increased. In this case, the relative amount of the inorganic fluorine-comprising gas to the C.sub.xH.sub.yF.sub.z gas should be increased in order to provide the optimum balance between etch rate and sidewall passivation.”, para. [0014]).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention, that the chosen etch gas for the method disclosed in Chang163 would be based on the materials of the substrate. A person of ordinary skill in the art would be motivated to look to the prior art to see which etching gases where being used in conjunction with the chosen materials, such as tantalum nitride, and could conclude that the element of the purge gas CHF.sub.3 disclosed in Nallan488 could be substituted into the method of Chang163, replacing the halogen and fluorine containing etching gas with CHF.sub.3, to yield predictable results.
The examiner notes that the claim language “for manufacturing 3D NAND devices” is intended use and does not impose any additional structural limitations or method step limitations on the claim. Regardless, Chen830 teaches etching methods for a 3D NAND device containing silicon oxide and silicon nitride films (“For example, in some structures, alternating layers of silicon oxide and silicon may be used, or alternating layers of silicon oxide and silicon nitride,”, para. [0023]) and also suggests a need to etch metal lining layers including tantalum nitride (“If a liner material is utilized when forming the stacked layers, such as an aluminum oxide, hafnium oxide, titanium nitride, tantalum nitride, or hafnium nitride liner formed between silicon oxide and molybdenum, the liner may also need to be removed.”, para. [0023]).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention, that the etching method disclosed by Chang163 using the etching gas disclosed in Nallan488, could be applied to a variety of semiconductor devices, a 3D NAND being just one of them, for example, to etch a liner layer of tantalum nitride. The etching methods taught by Chen830 are also substantially the same as those disclosed by Chang163 and Nallan488, etching a metal layer by exposing it to a plasma of halide etching gas, therefore the claimed invention is merely the combination of known prior art elements with predictable results.
Regarding claim 16: In addition to the reasoning used to reject claim 15, Chang163 teaches that the thin film is a tantalum nitride film. (“In some embodiments, the metal nitride layer comprises a metal nitride selected from the list consisting of hafnium nitride, titanium nitride, vanadium nitride, tantalum nitride, zirconium nitride, yttrium nitride, niobium nitride, copper nitride, molybdenum nitride, and tungsten nitride.”, para. [0007]).
Regarding claim 17: In addition to the reasoning used to reject claim 16, Chang163 does not teach that the substrate includes at least one of a silicon oxide film and a silicon nitride film.
Chen830 teaches etching methods for a 3D NAND device containing silicon oxide and silicon nitride films (“For example, in some structures, alternating layers of silicon oxide and silicon may be used, or alternating layers of silicon oxide and silicon nitride,”, para. [0023]) and also suggests a need to etch metal lining layers including tantalum nitride (“If a liner material is utilized when forming the stacked layers, such as an aluminum oxide, hafnium oxide, titanium nitride, tantalum nitride, or hafnium nitride liner formed between silicon oxide and molybdenum, the liner may also need to be removed.”, para. [0023]).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention, that the etching method disclosed by Chang163 using the etching gas disclosed in Nallan488, could be applied to a variety of semiconductor devices, a 3D NAND being just one that contains a silicon oxide or silicon nitride film, for example, to etch a liner layer of tantalum nitride. The etching methods taught by Chen830 are also substantially the same as those disclosed by Chang163 and Nallan488, etching a metal layer by exposing it to a plasma of halide etching gas, therefore the claimed invention is merely the combination of known prior art elements with predictable results.
Regarding claim 18: In addition to the reasoning used to reject claim 17, Chang163 does not teach that the substrate includes a stacked film in which the silicon oxide film and the silicon nitride film are alternately stacked vertically, wherein the tantalum nitride film is formed in an opening formed through the stacked film.
Chen830 teaches etching methods for a 3D NAND device containing silicon oxide and silicon nitride films (“For example, in some structures, alternating layers of silicon oxide and silicon may be used, or alternating layers of silicon oxide and silicon nitride,”, para. [0023]) and also suggests a need to etch metal lining layers including tantalum nitride (“If a liner material is utilized when forming the stacked layers, such as an aluminum oxide, hafnium oxide, titanium nitride, tantalum nitride, or hafnium nitride liner formed between silicon oxide and molybdenum, the liner may also need to be removed.”, para. [0023]).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention, that the etching method disclosed by Chang163 using the etching gas disclosed in Nallan488, could be applied to a variety of semiconductor devices, a 3D NAND being just one that contains a silicon oxide or silicon nitride film, for example, to etch a liner layer of tantalum nitride. The etching methods taught by Chen830 are also substantially the same as those disclosed by Chang163 and Nallan488, etching a metal layer by exposing it to a plasma of halide etching gas, therefore the claimed invention is merely the combination of known prior art elements with predictable results.
Regarding claim 19: In addition to the reasoning used to reject claim 17, Chang163 does not teach that the substrate includes: a stacked film in which the silicon oxide film and the silicon nitride film are alternately stacked vertically; a slit-shaped first opening formed by etching the stacked film vertically; and a plurality of second openings formed to extend horizontally from the slit-shaped first opening by selectively etching the silicon nitride film exposed in the slit-shaped first opening, wherein the tantalum nitride film is formed on surfaces of the slit-shaped first opening and the second openings.
Chen830 teaches etching methods for a 3D NAND device containing silicon oxide and silicon nitride films (“For example, in some structures, alternating layers of silicon oxide and silicon may be used, or alternating layers of silicon oxide and silicon nitride,”, para. [0023]) and also suggests a need to etch metal lining layers including tantalum nitride (“If a liner material is utilized when forming the stacked layers, such as an aluminum oxide, hafnium oxide, titanium nitride, tantalum nitride, or hafnium nitride liner formed between silicon oxide and molybdenum, the liner may also need to be removed.”, para. [0023]). A slit-shaped first opening formed by etching the stacked film vertically (“These stacked layers may be etched into trenches or contact holes. Additionally, one of these two alternating materials, or at least a portion thereof, may be etched selectively from the trenches to form memory cells.”, para. [0023]); and a plurality of second openings formed to extend horizontally from the slit-shaped first opening by selectively etching the silicon nitride film exposed in the slit-shaped first opening (“The processed structure 500 may further include one or more barrier materials or liner materials, such as gate metal barriers and gate dielectric, which may collectively or individually be referred to as a second liner. The gate metal barriers may include oxide, nitride, or oxygen-and-nitrogen barriers, such as oxide or nitride barriers 545 (e.g., aluminum oxide, hafnium oxide, titanium nitride, tantalum nitride, hafnium nitride, etc.) as shown in FIG. 5A. The oxide or nitride barriers, again referred to as a second liner, may be disposed adjacent to the molybdenum-containing metal regions and/or the molybdenum-containing first liner.”, para. [0046]).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention, that the etching method disclosed by Chang163 using the etching gas disclosed in Nallan488, could be applied to a variety of semiconductor devices, a 3D NAND being just one that contains a silicon oxide or silicon nitride film, for example, to etch a liner layer of tantalum nitride. The additional limitations of claim 19, such as the vertical opening with lateral recesses are generic to many 3D NAND devices and well-known in the art. The etching methods taught by Chen830 are also substantially the same as those disclosed by Chang163 and Nallan488, etching a metal layer by exposing it to a plasma of halide etching gas, therefore the claimed invention is merely the combination of known prior art elements with predictable results.
Claim(s) 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chang et al. (US 20220102163 A1), hereinafter referred to as Chang163, in view of Nallan (US 20020132488 A1) hereinafter referred to as Nallan488 and Chen et al. (US 20230386830 A1) hereinafter referred to as Chen830 and Or-Bach et al. (US 20200013791 A1), hereinafter referred to as Or-Bach791.
Regarding claim 20: In addition to the reasoning used to reject claim 19, Chang163 does not teach a tunneling oxide is formed along the surfaces of the slit-shaped first opening and the second openings, a nitride film trap is formed on the tunneling oxide, a gate insulating film is formed on the nitride film trap, and the tantalum nitride film is formed on the gate insulating film.
Chen830 teaches etching methods for a 3D NAND device including forming the gate layers for memory cells “The processed structure 500 may further include one or more barrier materials or liner materials, such as gate metal barriers and gate dielectric, which may collectively or individually be referred to as a second liner. The gate metal barriers may include oxide, nitride, or oxygen-and-nitrogen barriers, such as oxide or nitride barriers 545 (e.g., aluminum oxide, hafnium oxide, titanium nitride, tantalum nitride, hafnium nitride, etc.) as shown in FIG. 5A. The oxide or nitride barriers, again referred to as a second liner, may be disposed adjacent to the molybdenum-containing metal regions and/or the molybdenum-containing first liner. The gate dielectric may include aluminum oxide gate dielectric, such as gate dielectric 550 (e.g., aluminum oxide) as shown in FIG. 5A. The oxide or nitride barriers 545 may be a metal-containing oxide or nitride material. It is contemplated that the processed structure 500 may include only one of the oxide or nitride barriers 545 and the gate dielectric 550.”, para. [0046]).
Chen830 does not explicitly teach the oxide-nitride-oxide (O/N/O) structure for forming a charge trapping layer.
Or-Bach 791 discloses the O/N/O structure for use in a 3D NAND device (“Most of the discussion in PCT/US2016/052726 and PCT/US2017/052359, incorporated herein by reference, is in respect to 3D NOR memory utilizing single crystal channel. Yet, these techniques could in many cases be used to improve other 3D memories such as 3D-NAND. FIG. 1A illustrates a prior art 3D NAND structure utilizing monotonic deposited macaroni shaped channel 1004 and monotonic deposited charge trap layer 1002 that is continuous along the structure. The charge trap layer could comprise tunneling oxide on the channel side, silicon nitride as a charge trapping layer, and control oxide or blocking oxide on the gate side, this structure is commonly called O/N/O. The tunneling oxide can be a simple silicon dioxide or barrier engineered oxide comprising, for example, a stack of silicon dioxide, silicon nitride, and another silicon dioxide.”, para. [0079]).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the method of depositing the O/N/O layers into the trench of a 3D NAND device. This is simply combining well-known prior art elements to yield predictable results. Combinations of the obvious method steps of the etching process and the obvious steps of forming the 3D NAND device are also obvious because a person of ordinary skill in the art would recognize that this combination yields predictable results. Furthermore, the method of etching a metal containing film and the method of forming the 3D NAND device are performing the same functions as they would separately.
Citation of Pertinent Prior Art
The prior art made of record and not relied upon is considered relevant to the Applicant’s Disclosure:
Bajaj et al. (US 20190311909 A1) teaches a method for oxidizing metal containing films and removing a layer of various thickness down to the sub-angstrom level, as well as an overlapping temperature range for the etching method of the claimed invention. Ochrlein et al. (US 10790157 B1) teaches CHF.sub.3 as an etching gas for tantalum pentoxide, which is the oxidized form of tantalum nitride in an atomic layer etching process.
Conclusion
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/ROBERT L STEWART/Examiner, Art Unit 2898
/JESSICA S MANNO/SPE, Art Unit 2898
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