Prosecution Insights
Last updated: October 02, 2026
Application No. 18/615,901

METHOD FOR FABRICATING MASK, AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE USING THE SAME

Non-Final OA §103§112
Filed
Mar 25, 2024
Priority
Jun 02, 2023 — RE 10-2023-0071893
Examiner
TRAYWICK, ANDREW PRESTON
Art Unit
4100
Tech Center
4100
Assignee
Samsung Electronics Co., Ltd.
OA Round
1 (Non-Final)
72%
Grant Probability
Favorable
1-2
OA Rounds
7m
Est. Remaining
99%
With Interview

Examiner Intelligence

Grants 72% — above average
72%
Career Allowance Rate
91 granted / 127 resolved
+11.7% vs TC avg
Strong +27% interview lift
Without
With
+27.3%
Interview Lift
resolved cases with interview
Typical timeline
3y 1m
Avg Prosecution
32 currently pending
Career history
166
Total Applications
across all art units

Statute-Specific Performance

§103
61.5%
+21.5% vs TC avg
§102
18.3%
-21.7% vs TC avg
§112
12.5%
-27.5% vs TC avg
Black line = Tech Center average estimate • Based on career data from 127 resolved cases

Office Action

§103 §112
Detailed Action Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Priority Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55. Information Disclosure Statement The information disclosure statement (IDS) submitted on 03/25/2024 and 08/18/2026 are being considered by the examiner. Claim Objections Claim 1 is objected to because of the following informalities: Claim 1 recites “performing optical proximity correction on the second target pattern to generating a mask pattern therefrom;” (examiner’s emphasis where bolded). It appears this may be a typographical error where “to generate” is intended. Appropriate correction is required. Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. Claims 19 and 20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Regarding Claim 19-20, the instant claim recites “receiving a first straight edge and a second straight edge extending in a horizontal direction, and a step edge connecting the first straight edge and the second straight edge to each other”. It is not clear from this wording if both edges are to extend in a horizontal direction or if only the second straight edge is extending in a horizontal direction. For the purposes of examination over prior art, either interpretation will be considered. Claim 20 is rejected by nature of dependency from claim 19. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. Claim(s) 1, 2 and 19-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kang et al (US 20220179323, filed 10/8/2021). As a matter of claim interpretation – the instant claim 1 refers to a first target pattern that “includes” first straight edges. “Includes” is considered to be synonymous with “comprises” and thus the first target pattern does not exclude original/first curved/curvilinear features so long as the first target pattern also has straight edges. See MPEP 2111.03. Regarding Claims 1-2 and 19-20, Kang disclsoses a method of forming a semiconductor device wherein an optical proximity correction operation is performed on a layout and a photoresist pattern is formed on a substrate using a photomask that is manufactured with the layout corrected by the OPC process (Abstract). Kang does not disclose a particular experimental embodiment meeting the sum total of the claim limitations. These limitations are met by the general disclosure of Kang. The OPC operation includes sectioning the layout into a low-level patch and a high-level patch, performing a first OPC operation on the low-level patch, the first OPC operation including generating a first boundary correction pattern of a curvilinear shape on a boundary between the low-level patch and the high level patch, performing a second OPC operation on the high-level patch, the second OPC operation including a second boundary correction pattern of a curvilinear shape on the boundary, and conforming the first boundary correction pattern and the second boundary correction pattern to each other to generate a conformed boundary correction pattern of a curvilinear shape (Abstract). Figure 4 and 5-11 (see [0064]-[0076]) lays out that the section is laid out in the patches (S31), target patterns are then generated (S32, first target pattern as claimed), the target patterns are then OPC corrected on the low-level patch to generate low level correction patterns (S33, second target pattern as claimed) and the high level patch target patterns are also corrected to generate high level correction patterns (S34, alternatively, second target pattern as claimed). After, a step S35 generates the boundary correction pattern by conforming the low level correction patterns with the high level patterns (S35). The conforming process is described from [0077]-[0085] and Figs 12-17, where the conforming process comprises an OPC simulation process ([0085]) – the second target pattern(s) goes through an OPC process during the conforming. Figures 4 and 5-7 detail the generation of design patterns DP1 and DP2 on patches PAT1 and PAT2, where design target patterns DTP1 and DTP2 are generated from a corresponding design pattern. Figures 4 and 8-10 detail the formation of the correction patterns COP2_LL and COP2_HL for the low and high level patterns. Figures 4 and 11 detail the single correction pattern COP2 generated by conforming the two COP2_LL and COP2_HL patterns. Figs 7 ( where dashed lines correspond to the claimed first target pattern) and 9 (corresponding to the second target pattern) are depicted below: PNG media_image1.png 618 670 media_image1.png Greyscale PNG media_image2.png 636 758 media_image2.png Greyscale Herein the corners of the first target patterns DTP1 (squares) and DTP2 (central rectangle) are converted to curves to generate curvilinear shapes, where DTP2 includes both straight edges and curved edges. These edges include horizontal edges in a horizontal direction (claim 2). Further, in regards to claim 19, the Manhattan pattern (MOP) created in relation to Figs 12, 16, and 17 further comprises horizontal straight edges that are each other parallel and connected to a vertical step edge having external and internal corners (See below): PNG media_image3.png 636 536 media_image3.png Greyscale The corrected pattern (second target) COP2 comprises the changing of the corner parts of the vertical step edges on each side into curved edges, wherein an OPC process is used to generate the second pattern COP2 ([0068]). The resultant top and bottom straight edges correspond to the first and second straight edges of the first target pattern MOP. After the mask is manufactured, a photoresist pattern is formed on a substrate using the manufactured photomask ([0088]-[0096]. Kang ascribes high precision and improve characteristics to the masks and devices made therefrom as modified and treated per the OPC methods of the disclosure at [0003] and [0006]-[0008]. A person having ordinary skill in the art would have found it obvious to arrive at the claimed invention prior to the effective filing date from the disclosure of Kang by using the OPC methods to process mask target patterns in order to arrive at masks with improved precision. Claim(s) 1-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chuang et al (KR 20150114378 A1) and Hu et al (WO 2021/244820 A1, published 12/09/2021). Regarding Claim 1-9 and 19-20, Chuang teaches a method for manufacturing a semiconductor device comprising an optical proximity (OPC) process, wherein the manufacturing comprising the formation of a pattern of first dummy gates and second dummy gates on a substrate, forming a patterning mask over the first and second dummy gates - where the mask covers a third segment of the first dummy gate and a fourth segment of the second dummy gate ([0005]). After, the first and second segments of the first and second dummy gates are replaced. Forming the patterning mask is performed using an OPC technique ([0007]. The reference’s claim 1 teaches: Receiving a first layout design for a semiconductor device, the first layout design including a plurality of gate lines and an active area overlapping the plurality of gate lines, the active area including at least one angular corner A step of generating a second layout design which includes the correction active area having a correction corner which the first layout design for the semiconductor device is modified or revised through an optical proximity correction process and outward protrudes A step of manufacturing the semiconductor device based on the second layout design. Manufacturing the device as per the last step comprises the formation of Figures 11a-11c and 11d-11f detail a set of OPC methods to generating a mask from mask patterns (first target patterns), wherein the first mask has straight edges: PNG media_image4.png 390 368 media_image4.png Greyscale PNG media_image5.png 358 330 media_image5.png Greyscale PNG media_image6.png 378 390 media_image6.png Greyscale Wherein the semiconductor device 500 comprises an active region 510, an isolation region or trench 520, and a plurality of gate lines 530. A corner 540-541 is also present. At 11b, a photoresist layer 550 is formed to define the active region (to define the target pattern) 510, where the region has a rounded corner 560-561. 11c defines the dimensions of the corner D1 relative to the remainder of the distance D, where D is the intended distance of D1 ([0070]-[0076]). An optical proximity correction process is used to generate a modified design, wherein the process includes moving edges of the main feature and adding auxiliary features to the main feature, such as scattering bars, serifs, or hammerheads. The active region 510 may be considered the main feature and may be resized. PNG media_image7.png 354 308 media_image7.png Greyscale PNG media_image8.png 350 316 media_image8.png Greyscale PNG media_image9.png 342 316 media_image9.png Greyscale A further target pattern is generated from the original, having an active region comprising a step region 580 and an undercut 581 as per Fig 11d. This step region defines a corner portion, where the corner portion ahs a step shape including an outer corner and an inner corner adjacent thereto (claim 8). In the fabrication step 11e, the photoresist pattern formed conforms more closely to the second pattern by is not precisely cornered/straight-edged due to photolithographic effects ([0079]). In 11f, the resultant semiconductor device defines the active region 570a having a more substantially similar shape to that of 590 as patterned ([0077]-[0082], and further to that of active region 510 as in Fig. 11a. The additional curvature at the corners are advantageous in practice because the additional curvature reduces stress-induced cracking that can result from sharp angles, such as 90 degree angles at corners ([0081]). Different types of OPC processes may be used to achieve the shape profile of the active region 11f. Chuang does not disclose a second target pattern wherein the second target pattern has curved edges. This limitation is met by Hu. Hu describes systems, products, and methods for generating pattern masks for improving patterning methods and resultant devices (Abstract). The disclosure of Hu is directed to fabricating masks and improving the design thereof by obtaining mask points of a design of a mask feature (a first target feature in a pattern to be printed on a substrate) and then adjusting locations of the mask points to increase a process window and generate a modified design (a second target pattern) ([0011] and [0039]). In the disclosure of Hu, mask points are generated initially for a target feature from a target pattern and associated to control points thereof. The mask points and the control points associated therewith are adjusted to generate a curvilinear pattern. In some embodiments, multiple mask and control points are moved to optimized the cost function at one or more control points and thus improve overall lithography performance by allowing for finer and more accurate control of the mask design. The control points of Hu are used to defined the straight and curved edges of the mask ([0040]-[0041]), such as in Figures 6A and 6B, where the smaller, more numerous, and more densely packed/spaced points delineate the curvilinear structures and the larger, less numerous, and less densely packed/spaced points may delineate straight components (claim 3-7). PNG media_image10.png 414 344 media_image10.png Greyscale Chuang contemplates the modification of a mask target pattern so as to further improve the output of the mask. Applying the curved OPC method of Hu such as that demonstrated in Fig 6B to the stepped target pattern of Chuang to generate a curved second target pattern having a rounded step corner (rounding Chuang’s Corner portion 580 to form a curve protruding outward along the external corners and depressed inwardly at the internal corners (claim 9 and 20, where this curve connects the straight edges proximate the step-curve)), then applying further OPC processing to further optimize the cost functions of the points thereon would result in an optimized mask that would combine the advantages of a rounded mask feature (where rounding reduces stress-induced cracking that can result from sharp angles such as 90 degree angles at corners) and those of the optimization process to improve overall lithography performance by allowing for finer and more accurate control of the mask design. A person having ordinary skill in the art would have found it obvious to arrive at the claimed invention prior to the effective filing date from the combination of the disclosures of Chuang and Hu – applying an OPC correction method to build in curves to the mask design of Chuang in order to reduce cracking in angular regions of the mask and improve the overall lithographic performance by refining control of the mask design. Regarding Claim 10-13, Chuang teaches a method for manufacturing a semiconductor device comprising an optical proximity (OPC) process, wherein the manufacturing comprising the formation of a pattern of first dummy gates and second dummy gates on a substrate, forming a patterning mask over the first and second dummy gates - where the mask covers a third segment of the first dummy gate and a fourth segment of the second dummy gate ([0005]). After, the first and second segments of the first and second dummy gates are replaced. Forming the patterning mask is performed using an OPC technique ([0007]. The reference’s claim 1 teaches: Receiving a first layout design for a semiconductor device, the first layout design including a plurality of gate lines and an active area overlapping the plurality of gate lines, the active area including at least one angular corner A step of generating a second layout design which includes the correction active area having a correction corner which the first layout design for the semiconductor device is modified or revised through an optical proximity correction process and outward protrudes A step of manufacturing the semiconductor device based on the second layout design. Manufacturing the device as per the last step comprises the formation of Figures 11a-11c and 11d-11f detail a set of OPC methods to generating a mask from mask patterns (first target patterns), wherein the first mask has straight edges: PNG media_image4.png 390 368 media_image4.png Greyscale PNG media_image5.png 358 330 media_image5.png Greyscale PNG media_image6.png 378 390 media_image6.png Greyscale Wherein the semiconductor device 500 comprises an active region 510, an isolation region or trench 520, and a plurality of gate lines 530. A corner 540-541 is also present. At 11b, a photoresist layer 550 is formed to define the active region (to define the target pattern) 510, where the region has a rounded corner 560-561. 11c defines the dimensions of the corner D1 relative to the remainder of the distance D, where D is the intended distance of D1 ([0070]-[0076]). An optical proximity correction process is used to generate a modified design, wherein the process includes moving edges of the main feature and adding auxiliary features to the main feature, such as scattering bars, serifs, or hammerheads. The active region 510 may be considered the main feature and may be resized. PNG media_image7.png 354 308 media_image7.png Greyscale PNG media_image8.png 350 316 media_image8.png Greyscale PNG media_image9.png 342 316 media_image9.png Greyscale A further target pattern is generated from the original, having an active region comprising a step region 580 and an undercut 581 as per Fig 11d. This step region defines a corner portion, where the corner portion has a step shape including an outer corner and an inner corner adjacent thereto. In the fabrication step 11e, the photoresist pattern formed conforms more closely to the second pattern by is not precisely cornered/straight-edged due to photolithographic effects ([0079]). In 11f, the resultant semiconductor device defines the active region 570a having a more substantially similar shape to that of 590 as patterned ([0077]-[0082], and further to that of active region 510 as in Fig. 11a. The additional curvature at the corners are advantageous in practice because the additional curvature reduces stress-induced cracking that can result from sharp angles, such as 90 degree angles at corners ([0081]). Different types of OPC processes may be used to achieve the shape profile of the active region 11f. Chuang does not disclose a second target pattern wherein the second target pattern has curved edges. This limitation is met by Hu. Hu describes systems, products, and methods for generating pattern masks for improving patterning methods and resultant devices (Abstract). The disclosure of Hu is directed to fabricating masks and improving the design thereof by obtaining mask points of a design of a mask feature (a first target feature in a pattern to be printed on a substrate) and then adjusting locations of the mask points to increase a process window and generate a modified design (a second target pattern) ([0011] and [0039]). In the disclosure of Hu, mask points are generated initially for a target feature from a target pattern and associated to control points thereof. The mask points and the control points associated therewith are adjusted to generate a curvilinear pattern. In some embodiments, multiple mask and control points are moved to optimized the cost function at one or more control points and thus improve overall lithography performance by allowing for finer and more accurate control of the mask design. The control points of Hu are used to defined the straight and curved edges of the mask ([0040]-[0041]), such as in Figures 6A and 6B, where the smaller, more numerous, and more densely packed/spaced points delineate the curvilinear structures and the larger, less numerous, and less densely packed/spaced points may delineate straight components (claim 11-13). PNG media_image10.png 414 344 media_image10.png Greyscale Chuang contemplates the modification of a mask target pattern so as to further improve the output of the mask. Applying the curved OPC method of Hu such as that demonstrated in Fig 6B to the stepped target pattern of Chuang to generate a curved second target pattern having a rounded step corner (rounding Chuang’s Corner portion 580 to form a curve protruding outward along the external corners and depressed inwardly at the internal corners, then applying further OPC processing to further optimize the cost functions of the points thereon would result in an optimized mask that would combine the advantages of a rounded mask feature (where rounding reduces stress-induced cracking that can result from sharp angles such as 90 degree angles at corners) and those of the optimization process to improve overall lithography performance by allowing for finer and more accurate control of the mask design. A person having ordinary skill in the art would have found it obvious to arrive at the claimed invention prior to the effective filing date from the combination of the disclosures of Chuang and Hu – applying an OPC correction method to build in curves to the mask design of Chuang in order to reduce cracking in angular regions of the mask and improve the overall lithographic performance by refining control of the mask design. Regarding Claims 14,15, and 17, Chuang and Hu meet the limitations of the claims as discussed above regarding claim 10. However, Chuang does not explicitly disclose an embodiment wherein the straight edges of the stepped mask of 11d have a curved component. Chuang does disclose that curved components impart greater resistance to stress fractures that may occur at angled components. Chuang teaches a mask target pattern as per 11d: PNG media_image7.png 354 308 media_image7.png Greyscale This limitation is met by Hu, where Hu teaches an OPC that may generate curved surfaces or polygonal surfaces – or surfaces with both features (See Fig 17 and [00128]-[00133]). The regions 580 and 581 in 11d as above define overhang step and undercut step regions, where the overhang step region 581 comprises a bottom horizontal edge proximate to a lower vertical edge and an upper vertical edge. The upper vertical edge is proximate to an upper horizontal edge that meets at a corner. Curving the upper vertical edge between the two horizontal edges of the overhang results in a curve that has the first half-portion curving upwards ( a first direction) from the bottom horizontal edge and a second-half portion curving downwards from the upper horizontal edge, wherein the direction of the curve changes at an inflection point between the two horizontal edges. This step-curve configuration extends out in an elongate manner horizontally from the greater area 570 and has a width in a vertical direction (claim 17). A person having ordinary skill in the art would have found it obvious to arrive at the claimed invention prior to the effective filing date from the combination of the disclosures of Chuang and Hu – applying an OPC correction method to build in curves to the mask design of Chuang in order to reduce cracking in angular regions of the mask and improve the overall lithographic performance by refining control of the mask design. Regarding Claim 16, Chuang and Hu meet the limitations of the claims as discussed above regarding claim 10. However, Chuang does not explicitly disclose an embodiment wherein the straight edges of the stepped mask of 11d have a curved component. Chuang does disclose that curved components impart greater resistance to stress fractures that may occur at angled components. Chuang teaches a mask target pattern as per 11d: PNG media_image7.png 354 308 media_image7.png Greyscale This limitation is met by Hu, where Hu teaches an OPC that may generate curved surfaces or polygonal surfaces – or surfaces with both features (See Fig 17 and [00128]-[00133]). The regions 580 and 581 in 11d as above define overhang step and undercut step regions, where the overhang step region 581 comprises a bottom horizontal edge proximate to a lower vertical edge and an upper vertical edge. The upper vertical edge is proximate to an upper horizontal edge that meets at a corner. Curving the upper vertical edge and bottom horizontal edge between the upper horizontal and lower vertical edges of the overhang results in a curve that lies sequentially between the horizontal edge and the vertical edge. Further, this curved overhang would extend outward in an elongate manner from the broader region 570, where the width of the curve would vary in vertical width on at least a first and a second portion by nature of a curve’s geometry (claim 18). A person having ordinary skill in the art would have found it obvious to arrive at the claimed invention prior to the effective filing date from the combination of the disclosures of Chuang and Hu – applying an OPC correction method to build in curves to the mask design of Chuang in order to reduce cracking in angular regions of the mask and improve the overall lithographic performance by refining control of the mask design. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to ANDREW PRESTON TRAYWICK whose telephone number is (571)272-2982. The examiner can normally be reached Monday - Friday 8-5. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Sally Merkling can be reached at 571-272-6297. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /A.P.T./Examiner, Art Unit 1737 /SALLY A MERKLING/SPE, Art Unit 1738
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Prosecution Timeline

Mar 25, 2024
Application Filed
Sep 17, 2026
Non-Final Rejection mailed — §103, §112 (current)

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Prosecution Projections

1-2
Expected OA Rounds
72%
Grant Probability
99%
With Interview (+27.3%)
3y 1m (~7m remaining)
Median Time to Grant
Low
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