Prosecution Insights
Last updated: October 02, 2026
Application No. 18/615,912

PIXEL PACKAGE

Final Rejection §103
Filed
Mar 25, 2024
Priority
Mar 31, 2023 — TW 112112399
Examiner
STEVENSON, ANDRE C
Art Unit
Tech Center
Assignee
Epistar Corporation
OA Round
2 (Final)
90%
Grant Probability
Favorable
3-4
OA Rounds
0m
Est. Remaining
97%
With Interview

Examiner Intelligence

Grants 90% — above average
90%
Career Allowance Rate
785 granted / 877 resolved
+29.5% vs TC avg
Moderate +7% lift
Without
With
+7.2%
Interview Lift
resolved cases with interview
Typical timeline
2y 3m
Avg Prosecution
31 currently pending
Career history
903
Total Applications
across all art units

Statute-Specific Performance

§101
0.4%
-39.6% vs TC avg
§103
77.7%
+37.7% vs TC avg
§102
12.6%
-27.4% vs TC avg
§112
2.3%
-37.7% vs TC avg
Black line = Tech Center average estimate • Based on career data from 877 resolved cases

Office Action

§103
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Specification The specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification. Response to Arguments Applicant's arguments filed 07/30/26 have been fully considered but they are not persuasive. Applicant argues, “Sorg does not teach or suggest the recited first conductive structure having a first portion located between an upper first light-emitting diode and the first light- emitting surface of a lower third light-emitting diode, with a second portion located under that first portion and exposed from the transparent layered structure” and “Yamamoto does not cure this deficiency.” The Examiner has considered the Applicant’s arguments, but respectfully disagrees. The Examiner directs the Applicant the to the provided Examiner’s markup, figure #Ex1, (as provided from Sorg,. 2014/0367708, fig. #1), where it be seen that light emitting diodes item #108a,b&c have overlapping features and possess spacing between the structures. Furthermore, as also shown in the previous Non-Final and repeated the in this action, Yamamoto teaches, (as can be also viewed in fig. #2, column #5, line51-58), light emitting diodes that have a separation between their horizontal positions. Applicant argues that, ”Claim 1 further recites that the "first light-emitting surface" is a surface of the "third light-emitting diode," and that the first and second light-emitting diodes are arranged side by side over that first light-emitting surface. However, Sorg in view of Yamamoto fails to teach or suggest claim 1.” The Examiner has considered the Applicant’s argument but respectfully disagrees. The Examiner takes the position that claim #1 fails to state that “"first light-emitting surface" is a surface of the "third light-emitting diode,". If the Applicant believes that there is a portion of the claim language that clearly shows presents of the argument, the Examiner request that it be clear so that matter may be considered. Applicant argues that, “The Office Action's stated motivation of "improving light reflectance" does not provide an articulated reason with rational underpinning to make the specific structural modification required by claim 1, because Yamamoto's reflectance teaching is tied to drawn-out portions on a diode chip supporting an LED chip, not to routing a conductive structure between two light-emitting diodes in a transparent stacked pixel package”. The Examiner has considered the Applicant’s argument but respectfully disagrees. The Examiner takes the position that it has been well established that to be useful in an obviousness combination, a secondary reference should be used for what it teaches and need not be bodily substituted into the primary reference structure. "Question in a rejection for obviousness on a combination of references is what secondary reference would teach one skilled in the art and not whether its structure could be bodily substituted in basic reference structure." In re Richman 165 USPQ 509 (CCPA 1970). For the reasons shown above, the Examiner takes the position that the rejection was proper and maintains the Examiner’s position. For this reason, this action is made Final. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. Claim #1, 2, 7, 8, 14, 19, 20 are rejected under 35 U.S.C. 103 as being unpatentable over Sorg et al., (U.S. Pub. No, 2014/0367708), hereinafter referred to as "Sorg" and in view of Yamamoto (U.S. Pat. No. 9,153,545), hereinafter referred to as "Yamamoto". Sorg shows, with respect to claim #1, pixel package, comprising: a first light-emitting diode (Below; fig. #Ex1, item 108a); a second light-emitting diode (Below; fig. #Ex1, item 108b); a third light-emitting diode (Below; fig. #Ex1, item 108c), comprising a first light-emitting surface (Below; fig. #Ex1, item TS) and a first bottom surface (Below; fig. #Ex1, item BS) opposite to the first light-emitting surface, and the first light-emitting diode (Below; fig. #Ex1, item 108a) arranged side by side with the second light-emitting diode (Below; fig. #Ex1, item 108b) over the first light-emitting surface (paragraph 0041); a transparent layered structure (Below; fig. #1, item 114), encapsulating and separating the first light-emitting diode, the second light-emitting diode, and the third light-emitting diode (paragraph 0041) wherein, in a plan view, the third light-emitting diode is respectively overlapped with the first light-emitting diode and the second light-emitting diode. [AltContent: arrow][AltContent: textbox (Top Surface; TS)][AltContent: arrow][AltContent: arrow] [AltContent: textbox (Bottom Surface; BS)][AltContent: textbox (Ex1)][AltContent: arrow][AltContent: arrow][AltContent: connector][AltContent: arrow][AltContent: textbox (a)][AltContent: textbox (b)][AltContent: textbox (108c)] PNG media_image1.png 381 515 media_image1.png Greyscale Sorg substantially shows the claimed invention as shown in the rejection of claim #1 above. Sorg fails to show, with respect to claim #1, a pixel package comprising a first conductive structure, comprising a first portion and a second portion, the first portion located between the first light-emitting diode and the first light-emitting surface, and the second portion located under the first portion and exposed from the transparent layered structure. Yamamoto teaches, with respect to claim #1, a package comprising a first conductive structure, comprising a first portion (fig. #Ex2 , item FP) and a second (fig. #Ex2 , item SP) portion, the first portion located between the first light-emitting diode (Below; fig. #Ex2 , item FP with items #19 and 20) and the first light-emitting surface, and the second portion (Below; fig. #Ex2 , item PC) located under the first portion and exposed from the transparent layered (Below; fig. #Ex2 , item 66a&b) (column #5, line 21-28) structure (column #6, line 53-64). [AltContent: textbox (First Portion; FP)][AltContent: connector][AltContent: connector][AltContent: connector][AltContent: textbox (Ex2)][AltContent: arrow][AltContent: rect][AltContent: textbox (Pultruding Components; PC)][AltContent: textbox (Second Portion; SP)] PNG media_image2.png 516 632 media_image2.png Greyscale It would have been obvious to one having ordinary skill in the art at the time the invention was made, with respect to claim #1, to modified the invention of Sorg as modified by the invention of Yamamoto, which teaches, a pixel package comprising a first conductive structure, comprising a first portion and a second portion, the first portion located between the first light-emitting diode and the first light-emitting surface, and the second portion located under the first portion and exposed from the transparent layered structure, to incorporate a structural condition wherein the light reflectance can be improved, as taught by Yamamoto. Sorg substantially shows the claimed invention as shown in the rejection of claim #1 above. Sorg fails to show, with respect to claim #2, a pixel package wherein the first conductive structure is connected to a first electrode of the first light-emitting diode, a second electrode of the second light-emitting diode, and a first electrode of the third light-emitting diode. Yamamoto teaches, with respect to claim #2, a package comprising wherein the first conductive structure is connected to a first electrode of the first light-emitting diode, a second electrode of the second light-emitting diode, and a first electrode of the third light-emitting diode (column #9, line 65-67 column #10, line 1-9; column #11, line 39-54). It would have been obvious to one having ordinary skill in the art at the time the invention was made, with respect to claim #2, to modified the invention of Sorg as modified by the invention of Yamamoto, which teaches, a package comprising wherein the first conductive structure is connected to a first electrode of the first light-emitting diode, a second electrode of the second light-emitting diode, and a first electrode of the third light-emitting diode, to incorporate a structural condition wherein the light reflectance can be improved, as taught by Yamamoto. Sorg fails to show, with respect to claim #7, a pixel package a package wherein the first light-emitting diode, the second light-emitting diode, and the third light-emitting diode emit different dominant wavelengths. Yamamoto teaches, with respect to claim #7, a package wherein the first light-emitting diode, the second light-emitting diode, and the third light-emitting diode emit different dominant wavelengths (column #11, line 43-54). It would have been obvious to one having ordinary skill in the art at the time the invention was made, with respect to claim #7, to modified the invention of Sorg as modified by the invention of Yamamoto, which teaches, a package comprising a package wherein the first light-emitting diode, the second light-emitting diode, and the third light-emitting diode emit different dominant wavelengths, to incorporate a structural condition wherein a variety of colors may be provided, as taught by Yamamoto. Sorg and modified by Yamamoto substantially shows the claimed invention as shown in the rejection of claim #7 above. Sorg fails to show, with respect to claim #8, a pixel package wherein the first light-emitting diode emits a blue light, the second light-emitting diode emits a green light, and the third light-emitting diode emits a red light. Yamamoto teaches, with respect to claim #8, a package wherein the first light-emitting diode emits a blue light, the second light-emitting diode emits a green light, and the third light-emitting diode emits a red light (column #11, line 43-54). It would have been obvious to one having ordinary skill in the art at the time the invention was made, with respect to claim #8, to modified the invention of Sorg as modified by the invention of Yamamoto, which teaches, a package wherein the first light-emitting diode emits a blue light, the second light-emitting diode emits a green light, and the third light-emitting diode emits a red light, to incorporate a structural condition wherein a variety of colors may be provided, as taught by Yamamoto. Sorg shows, with respect to claim #14, a pixel package wherein the transparent layered structure is composed of a photoimageable dielectric material (paragraph 0041). Sorg fails to show, with respect to claim #19, a pixel package wherein the first portion and the second portion are extending along different directions. Yamamoto teaches, with respect to claim #19, a package wherein the first portion (Below; fig. #Ex2 , item FP and item 33) and the second portion (Below; fig. #Ex2 , item SP and item 41) are extending along different directions (column #6, line 40-47 column #7, line 29-37; column #9, line 38-45). It would have been obvious to one having ordinary skill in the art at the time the invention was made, with respect to claim #19, to modified the invention of Sorg as modified by the invention of Yamamoto, which teaches, a package comprising wherein the first portion and the second portion are extending along different directions, to incorporate a structural condition wherein flexibility of the positions for forming the n-side via and the p-side via can be spread by properly changing the patterns of the drawn-out portions, as taught by Yamamoto. Sorg shows, with respect to claim #20, wherein pixel package comprises a planar light-emitting surface (paragraph 0012-0013). // Claim #17, 18 are rejected under 35 U.S.C. 103 as being unpatentable over Sorg et al., (U.S. Pub. No, 2014/0367708), hereinafter referred to as "Sorg" as modified by Yamamoto (U.S. Pat. No. 9,153,545), hereinafter referred to as "Yamamoto" as shown in the rejection of claim #1 above and in further view of BAUMHEINRICH (U.S. Pub. No. 2022/0102583), hereinafter referred to as "Baumheinrich". Sorg as modified by Yamamoto, substantially shows the claimed invention as shown in the rejection of claim #1 above. Sorg as modified by Yamamoto, fails to show, with respect to claim #17 a pixel package further comprising a first conductive pad, a second conductive pad, a third conductive pad, and a fourth conductive pad electrically connected to the first light-emitting diode, the second light-emitting diode, the third light-emitting diode, and wherein one of the first conductive pad, a second conductive pad, a third conductive pad, and a fourth conductive pad comprises a shape different from the other conductive pads. Baumheinrich teaches, with respect to claim #17 a pixel package further comprising a first conductive pad, a second conductive pad, a third conductive pad, and a fourth conductive pad electrically connected to the first light-emitting diode, the second light-emitting diode, the third light-emitting diode, and wherein one of the first conductive pad, a second conductive pad, a third conductive pad, and a fourth conductive pad comprises a shape different from the other conductive pads (fig. #198, 199, item 1-14a and 15a-15c) (paragraph 1884-1885, 1887). It would have been obvious to one having ordinary skill in the art at the time the invention was made, with respect to claim #17, to modified the invention of Sorg as modified by Yamamoto as modified by the invention of Baumheinrich, which teaches, a pixel package further comprising a first conductive pad, a second conductive pad, a third conductive pad, and a fourth conductive pad electrically connected to the first light-emitting diode, the second light-emitting diode, the third light-emitting diode, and wherein one of the first conductive pad, a second conductive pad, a third conductive pad, and a fourth conductive pad comprises a shape different from the other conductive pads, to incorporate a structural condition that accommodates the conductor/electrode size parameters, as taught by Baumheinrich. Sorg as modified by Yamamoto, fails to show, with respect to claim #18 a pixel package wherein the first conductive pad is connected to the first conductive structure, the second conductive pad is connected to the second conductive structure, the third conductive pad is connected to the third conductive structure, and the fourth conductive pad is connected to the fourth conductive structure, and one of the first conductive pad, a second conductive pad, a third conductive pad, and a fourth conductive pad comprises a polarity different from the other conductive pads. Baumheinrich teaches, with respect to claim #18 wherein the first conductive pad is connected to the first conductive structure, the second conductive pad is connected to the second conductive structure, the third conductive pad is connected to the third conductive structure, and the fourth conductive pad is connected to the fourth conductive structure, and one of the first conductive pad, a second conductive pad, a third conductive pad (fig. #198, 199, item 1-14a and 15a-15c) (paragraph 1884-1885, 1887), and a fourth conductive pad comprises a polarity different from the other conductive pads (paragraph 0520). It would have been obvious to one having ordinary skill in the art at the time the invention was made, with respect to claim #18, to modified the invention of Sorg as modified by Yamamoto as modified by the invention of Baumheinrich, which teaches, wherein the first conductive pad is connected to the first conductive structure, the second conductive pad is connected to the second conductive structure, the third conductive pad is connected to the third conductive structure, and the fourth conductive pad is connected to the fourth conductive structure, and one of the first conductive pad, a second conductive pad, a third conductive pad, and a fourth conductive pad comprises a polarity different from the other conductive pads, to incorporate a structural condition that accommodates the conductor/electrode size parameters, as taught by Baumheinrich. Allowable Subject Matter Claim #3-6, 9-13, 15, 16 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The following is an examiner’s statement of indicating allowable subject matter: While the prior art teaches a first light-emitting diode; a second light-emitting diode; a third light-emitting diode, comprising a first light-emitting surface and a first bottom surface opposite to the first light-emitting surface, and the first light-emitting diode arranged side by side with the second light-emitting diode over the first light-emitting surface; a transparent layered structure, encapsulating and separating the first light-emitting diode, the second light-emitting diode, and the third light-emitting diode; and a first conductive structure, comprising a first portion and a second portion, the first portion located between the first light-emitting diode and the first light-emitting surface, and the second portion located under the first portion and exposed from the transparent layered structure; wherein, in a plan view, the third light-emitting diode is respectively overlapped with the first light-emitting diode and the second light-emitting diode, (Sorg et al., 2014/0367708; Yamamoto, 9,153,545), it fails to teach either collectively or alone, with respect to claim #3, a pixel package comprising a third conductive structure, located between the second light-emitting diode and the first light-emitting surface, and connected to the second electrode of the second light-emitting diode; and a fourth conductive structure, located under the first bottom surface, and connected to a second electrode of the third light-emitting diode. Also, the prior art fails to teach either collectively or alone, with respect to claim #9, a pixel package wherein the third light-emitting diode comprises a first long side extending along a first direction, the first light-emitting diode comprises a second long side extending along a second direction, the second light-emitting diode comprises a third long side extending along a third direction, and the first direction is different from the second direction EXAMINATION NOTE The rejections above rely on the references for all the teachings expressed in the text of the references and/or one of ordinary skill in the art would have reasonably understood or implied from the texts of the references. To emphasize certain aspects of the prior art, only specific portions of the texts have been pointed out. Each reference as a whole should be reviewed in responding to the rejection, since other sections of the same reference and/or various combinations of the cited references may be relied on in future rejections in view of amendments. Conclusion THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to Andre’ Stevenson whose telephone number is (571) 272 1683 (Email Address, Andre.Stevenson@USPTO.GOV). The examiner can normally be reached on Monday through Friday from 7:30 am to 4:30 pm. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Zandra Smith can be reached on 571-272 2429. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /Andre’ Stevenson Sr./ Art Unit 2899 09/03/2026 /ZANDRA V SMITH/Supervisory Patent Examiner, Art Unit 2899
Read full office action

Prosecution Timeline

Mar 25, 2024
Application Filed
May 05, 2026
Non-Final Rejection mailed — §103
Jul 30, 2026
Response Filed
Sep 08, 2026
Final Rejection mailed — §103 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12751227
ETCHING METHOD, PLASMA PROCESSING APPARATUS, SUBSTRATE PROCESSING SYSTEM, AND PROGRAM
4y 2m to grant Granted Sep 29, 2026
Patent 12740408
POWER MODULE, POWER SUPPLY CIRCUIT, AND CHIP
2y 7m to grant Granted Sep 15, 2026
Patent 12740169
SEMICONDUCTOR CHIP AND MANUFACTURING METHOD THEREFOR, SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREFOR, AND ELECTRONIC DEVICE
2y 12m to grant Granted Sep 15, 2026
Patent 12740164
LIGHT DETECTION DEVICE AND ELECTRONIC DEVICE
2y 12m to grant Granted Sep 15, 2026
Patent 12727452
SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
3y 2m to grant Granted Sep 01, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

Strategy Recommendation AI-generated — please review before filing

Get a prosecution strategy drawn from examiner precedents, rejection analysis, and claim mapping.
Typically takes 5-10 seconds — AI-generated, attorney review required before filing

Prosecution Projections

3-4
Expected OA Rounds
90%
Grant Probability
97%
With Interview (+7.2%)
2y 3m (~0m remaining)
Median Time to Grant
Moderate
PTA Risk
Based on 877 resolved cases by this examiner. Grant probability derived from career allowance rate.

Sign in with your work email

Enter your email to receive a magic link. No password needed.

Personal email addresses (Gmail, Yahoo, etc.) are not accepted.

Free tier: 3 strategy analyses per month