Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Election/Restrictions
Claims #15-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b), as being drawn to a nonelected invention, there being no allowable generic or linking claim. Applicant timely traversed the restriction (election) requirement in the reply filed on 05/19/26.
Applicant argues that, Applicant notes that claim 1 of Group I is almost completely generic to independent claim 15 of Group II, except for the active silicon bridge having a first portion and a second portion, the first portion disposed between the substrate and the logic device, the second portion disposed between the substrate and the memory stack being narrower than Group II. However, a search of the positional requirement of having the first portion being disposed between the substrate and the logic device recited in the claims of Group I is still generic to the physical interface layer disposed below the logic device as recited by the claims of Group I. Thus, the independent claims Groups I and II.
The Examiner has considered the Applicants arguments, but respectfully disagrees. As shown in the restriction request issue on 04/27/26, Groups I and II represent different package structures; see previous restriction requirement for specific details. The Examiner further directs the Applicant to MPEP 35 U.S.C. 121, where a quote in the preceding section states that the Director may require restriction if two or more "independent and distinct" inventions that are claimed in one application. Furthermore, in 37 CFR 1.141, the statement is made that two or more "independent and distinct inventions" may not be claimed in one application. Because the Examiner has demonstrated in the previous restriction that Groups I and II have different structures that are not mutually shared, the Examiner takes the position that they represent different inventive entities; i.e. and therefore should be restricted. For these reasons, the Examiner takes the position that the restriction was proper and maintains his position.
Claims #1-14 will be examined.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 06/27/24, 10/21/24, 01/16/25 was filed in a timely manner; thus, the submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) #1-8, is/are rejected under 35 U.S.C. 102(a)(2) as being unpatentable by CHEAH et al., (U.S. Pub. No, 2024/0071934), hereinafter referred to as "Cheah".
Cheah shows, with respect to claim #1, a chip package comprising: a substrate (fig. #2, item 220) (paragraph 0028); a logic device (Below; fig. #Ex1 , item LG1) disposed over the substrate (paragraph 0002, 0013, 0029), the logic device comprising one or more compute dies (fig.#2, item 211) (paragraph 0022, 0029); a memory stack (HBM; fig. #1a, item 110, 111) disposed over the substrate adjacent the logic device (paragraph 0025); and an active silicon bridge (fig. #1, item 102, 103; also seen, fig. #2, item 202, 203, Below; fig. #Ex1 , item BG1) having a first portion and a second portion (paragraph 0019-0020, 0029), the first portion (Below; fig. #Ex1, item A1) disposed between the substrate (Below; fig. #Ex1 , item 220) and the logic device (Below; fig. #Ex1 , item LG1) (paragraph 0019-0020), the second portion (Below; fig. #Ex1, item B1) disposed between the substrate (Below; fig. #Ex1 , item 220) and the memory stack (Below; fig. #Ex1 , item 211).
[AltContent: textbox (3b)][AltContent: textbox (220)][AltContent: arrow][AltContent: textbox (Bridge; BG1)][AltContent: arrow][AltContent: textbox (Logic Device ;LG1)][AltContent: connector][AltContent: connector][AltContent: connector][AltContent: arrow][AltContent: textbox (B1)][AltContent: textbox (A1)][AltContent: arrow][AltContent: arrow][AltContent: textbox (Ex1)]
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Cheah shows, with respect to claim #2, a chip package comprising: wherein the one or more compute dies of the logic device further comprises: at least a first compute die and a second compute die (paragraph 0013, 0019).
Cheah shows, with respect to claim #3, a chip package comprising: further comprising: a redistribution layer electrically coupling circuitry of the logic device with circuitry of the active silicon bridge (paragraph 0019).
Cheah shows, with respect to claim #4, a chip package further comprising: mold compound disposed between the redistribution layer and the substrate, the active silicon bridge having portions of the mold compound disposed on opposite sides of the active silicon bridge (paragraph 0010, 0035, 0038, 0072).
Cheah shows, with respect to claim #5, a chip package further comprising: an interposer disposed between the redistribution layer and the substrate (paragraph 0019), the interposer comprising a cavity (fig. #3a, item 317) in which the active silicon bridge resides (paragraph 0034).
Cheah shows, with respect to claim #6, a chip package wherein the active silicon bridge further comprises: an interposer (fig. #1, item 103: with TVS’s 103b and 107) disposed between the redistribution layer (fig. #1, item 103a) and the substrate (fig. #1, item 120) (paragraph 0019, 0021).
Cheah shows, with respect to claim #7, a chip package wherein the active silicon bridge further comprises: a physical interface layer configured to communicate with the logic device; and memory controller circuitry coupled to the physical interface layer (paragraph 0024).
Cheah shows, with respect to claim #8, a chip package wherein the memory controller circuitry further comprises: off-package memory controller circuitry; and on-package memory controller circuitry (paragraph 0024)
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) #13 is/are rejected under 35 U.S.C. 102(a)(2) as anticipated by or, in the alternative, under 35 U.S.C. 103 as obvious over CHEAH et al., (U.S. Pub. No, 2024/0071934), hereinafter referred to as "Cheah"
Cheah shows, with respect to claim #13, a chip package wherein the logic device (above; fig. #Ex1 , item LG1) further comprises (paragraph 0002, 0013, 0029): an IC interposer die (fig. #1, item 103: with TVS’s 103b and 107) coupled to both the first and second compute dies (fig. #2, item 211) without routing signals through the substrate (paragraph 0022, 0029); and cache memory circuity (fig. #1, item 110, 111) disposed in the IC interposer die and coupled to both the first and second compute dies without routing signals through the substrate (HBM; paragraph 0025).
The Examiner notes that Cheah does not explicitly state that a cache memory circuity is disposed. However, the Examiner notes that Cheah employs a HBM device. The Examiner takes the position that the implementation of HBM devices as cache devices is well known; The Examiner notes that Cheah does not explicitly state that a cache memory circuity is disposed. However, the Examiner notes that Cheah employs a HBM device. The Examiner takes the position that the implementation of HBM devices as cache devices is well known; as evidenced by the citation in Google:
HBM as Cache - HBM is a 3D-stacked DRAM technology designed for high bandwidth and low latency, often placed close to the processor to alleviate memory bottlenecks . In certain systems, HBM can operate in cache mode, where it functions as a level 4 cache for DDR memory. In this mode, applications automatically benefit from HBM’s high-speed access without explicit memory management, although cache misses may introduce slightly higher latency compared to direct memory access. This allows HBM to accelerate workloads with high data reuse that fits within its capacity.
Therefore, the Examiner takes the position that it would have been obvious to one of ordinary skill in the art, at the time of conception of the claimed invention, with respect to claim #13, to use HBM structure as a cache, since it has been shown that HBM functions as cache with additional advantages of accelerating workloads with high data reuse that fits within its capacity
EXAMINATION NOTE
The rejections above rely on the references for all the teachings expressed in the text of the references and/or one of ordinary skill in the art would have reasonably understood or implied from the texts of the references. To emphasize certain aspects of the prior art, only specific portions of the texts have been pointed out. Each reference as a whole should be reviewed in responding to the rejection, since other sections of the same reference and/or various combinations of the cited references may be relied on in future rejections in view of amendments.
Allowable Subject Matter
Claims #9-12, 14 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is an examiner’s statement of reasons for allowance: While the prior art teaches a chip package comprising: a substrate; a logic device disposed over the substrate, the logic device comprising one or more compute dies; a memory stack disposed over the substrate adjacent the logic device; and an active silicon bridge having a first portion and a second portion, the first portion disposed between the substrate and the logic device, the second portion disposed between the substrate and the memory stack, (CHEAH et al., 2024/0071934; TONG, 2023/0154825), it fails to teach either collectively or alone, with respect to claim #9, a chip package further comprising: an electrically floating metal layer disposed on a side of the active silicon bridge opposite the logic device. Also, with respect to claim #14, the prior art fails to teach, either collectively or alone, a chip package an IC interposer die coupled to both the first and second compute dies without routing signals through the substrate; a network on a chip (NOC) circuitry disposed in the IC interposer die; peripheral component interconnect express (PCle) circuity disposed in the IC interposer die; memory physical layer (PHY) circuitry configured to communicate with the memory stack disposed directly above the active silicon bridge; die to die PHY configured to communicate with at least one of the first and second compute dies; and I/O PHY configured to communicate with a device remote from the chip package.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Andre’ Stevenson whose telephone number is (571) 272 1683 (Email Address, Andre.Stevenson@USPTO.GOV). The examiner can normally be reached on Monday through Friday from 7:30 am to 4:30 pm. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Zandra Smith can be reached on 571-272 2429. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/Andre’ Stevenson Sr./
Art Unit 2899
06/25/2026
/Brent A. Fairbanks/ Supervisory Patent Examiner, Art Unit 2899
Prosecution Insights