DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the tail current transistors Mb1 and Mb2 must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
New corrected drawings in compliance with 37 CFR 1.121(d) are required in this application because the element numbers of the transistors in Figure 6 are unreadable and it is difficult to ascertain the distinctions between the various transistors. Applicant is advised to employ the services of a competent patent draftsperson outside the Office, as the U.S. Patent and Trademark Office no longer prepares new drawings. The corrected drawings are required in reply to the Office action to avoid abandonment of the application. The requirement for corrected drawings will not be held in abeyance.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 7 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 7 recites the limitation "the first load capacitor” and “the second load capacitor" in lines 1 and 2 respectively. There is insufficient antecedent basis for this limitation in the claim.
The following is a quotation of 35 U.S.C. 112(d):
(d) REFERENCE IN DEPENDENT FORMS.—Subject to subsection (e), a claim in dependent form shall contain a reference to a claim previously set forth and then specify a further limitation of the subject matter claimed. A claim in dependent form shall be construed to incorporate by reference all the limitations of the claim to which it refers.
The following is a quotation of pre-AIA 35 U.S.C. 112, fourth paragraph:
Subject to the following paragraph [i.e., the fifth paragraph of pre-AIA 35 U.S.C. 112], a claim in dependent form shall contain a reference to a claim previously set forth and then specify a further limitation of the subject matter claimed. A claim in dependent form shall be construed to incorporate by reference all the limitations of the claim to which it refers.
Claim 9 is rejected under 35 U.S.C. 112(d) or pre-AIA 35 U.S.C. 112, 4th paragraph, as being of improper dependent form for failing to further limit the subject matter of the claim upon which it depends, or for failing to include all the limitations of the claim upon which it depends.
Claim 9 does not contain any limitation that further limits Claim 1. When reading the preamble in the context of the entire claim, the recitation “A wireline communication system” is not limiting because the body of the claim describes a complete invention and the language recited solely in the preamble does not provide any distinct definition of any of the claimed invention' s limitations. Thus, the preamble of the claim(s) is not considered a limitation and is of no significance to claim construction. See Pitney Bowes, Inc. v. Hewlett-Packard Co., 182 F.3d 1298, 1305, 51 USPQ2d 1161, 1165 (Fed. Cir. 1999). See MPEP § 2111.02.
Applicant may cancel the claim(s), amend the claim(s) to place the claim(s) in proper dependent form, rewrite the claim(s) in independent form, or present a sufficient showing that the dependent claim(s) complies with the statutory requirements.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 6, and 8-10 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Bulzacchelli et al. (US 2013/0207722).
In regard to Claim 1:
Bulzacchelli discloses, in Figure 5, an equalizer circuit (50) comprising:
a main stage (22) comprising a first differential amplifier stage circuit having a first differential pair of transistors (M4, M5), wherein source terminals of the transistors (M4, M5) are linked to a drain of a tail current transistor (I4, ¶ 0045), configured to operate independently to amplify signals in a low-frequency range and change a DC gain (¶ 0029) of the main stage (¶ 0034-0035);
an auxiliary stage (21) comprising a first differential amplifier stage circuit having a second differential pair of transistors (M2, M3), wherein source terminals of the transistors (M2, M3), are linked to a drain of another tail current transistor (I2, ¶ 0045), configured to operate independently to change AC gain peaking (¶ 0003) of the auxiliary stage (21);
wherein the main stage (22) is electrically coupled to the auxiliary stage (21) via a pair of coupling capacitors of predefined value (CC1A, CC1B), the pair of coupling capacitors (CC1A, CC1B) comprises a first coupling capacitor (C) (CC1A) coupled between a drain terminal of the main stage (22) transistor (M5) and a drain terminal of the auxiliary stage (21) transistor (M3, ¶ 0037);
a second coupling capacitor (C) (CC1B) coupled between a drain terminal of the main stage (22) transistor (M4) and a drain terminal of the auxiliary stage (21) transistor (M2), and wherein the change in the DC gain of the main stage (22) has no effect on the change in the AC gain peaking of the auxiliary stage (21), or vice versa (¶ 0034).
In regard to Claim 6:
Bulzacchelli discloses, in Figure 5, the equalizer circuit as claimed in claim 1, wherein the circuit overall gain is configured to increase or decrease at high frequencies based on a fine tuning of relative biasing of the main (22) and auxiliary stages (21), load resistors values (R1, R1B), and the coupling capacitors (C) values (CC1A, CC1B). (¶ 0042)
In regard to Claim 8:
Bulzacchelli discloses, in Figure 5, The equalizer circuit (100) as claimed in claim 1, wherein the transistors of the main (22) and auxiliary stages (21) comprises NMOS transistor (¶ 0039).
In regard to Claim 9:
Bulzacchelli discloses, in Figure 5, a wireline communication system (¶ 0002) comprising an equalizer (50) circuit as claimed in claim 1 (see the rejection of Claim 1 above).
In regard to Claim 10:
Bulzacchelli discloses, in Figure 5, a method of operation of equalizer (50) comprising
receiving an analog signal (Vin),
applying a variable first DC gain (¶ 0029) to the analog signal at a pre-determined frequency while attenuating the analog signals at frequencies in a low frequency range below the frequency (¶ 0022), wherein the first DC gain is provided by a main stage (22) of the equalizer (50); and
applying a variable AC Peaking gain (¶ 0003) to the analog signal at the pre-determined frequency in the low frequency range (¶ 0027), wherein the AC Peaking gain is provided by a an auxilairay stage (21) of the equalizer (50);
wherein the variation in the DC gain of the main stage (22) has no effect on the variation in the AC gain peaking of the auxiliary stage (21), or vice versa (¶ 0034).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 2 is/are rejected under 35 U.S.C. 103 as being unpatentable over Bulzacchelli et al. (US 2013/0207722), in view of Mattia et al. (US 10,530,346).
In regard to Claim 2:
All of the claim limitations have been discussed with respect to Claim 1, except for wherein the equalizer’s DC gain is altered by manipulating or fine tuning a tail current of the main stage current transistor and an AC gain of the equalizer is finely tuned by adjusting a tail current of the auxiliary stage tail current transistor.
Mattia discloses, in Figure 1, wherein the equalizer’s DC gain is altered by manipulating or fine tuning a tail current of the main stage (22) current transistor (I4) and an AC gain of the equalizer is finely tuned by adjusting a tail current of the auxiliary stage (21) tail current transistor (I2).
It would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to use the adjustable tail current taught by Mattia with the differential amplifiers taught by Bulzacchelli, since all the claimed elements were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods with no change in their respective functions, and the combination yielded nothing more than predictable results to one of ordinary skill in the art. (KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 415-421, 82 USPQ2d 1385).
Claim(s) 3 and 11-12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Bulzacchelli et al. (US 2013/0207722).
In regard to Claim 3:
All of the claim limitations have been discussed with respect to Claim 1, except for wherein the predefined value of the pair of capacitors is less than 150 x10 farads. It would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to have the predefined value of the pair of capacitors be less than 150 x10 farads, since it has been held that discovering an optimum value of a result effective variable involves only routine skill in the art. In re Boesch, 617 F.2d 272, 205 USPQ 215 (CCPA 1980).
In regard to Claim 11:
All of the claim limitations have been discussed with respect to Claim 10, except for wherein the pre-determined frequency is at least in the range of 1-12.5 GHz. It would have been obvious to one having ordinary skill in the art at the time the invention was made to have the pre-determined frequency be at least in the range of 1-12.5 GHz, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233.
In regard to Claim 12:
All of the claim limitations have been discussed with respect to Claim 10, except for wherein the low frequency range is at least in the range of 100-500 KHz. It would have been obvious to one having ordinary skill in the art at the time the invention was made to have the low frequency range be at least in the range of 100-500 KHz, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233.
Allowable Subject Matter
Claims 4 and 5 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Kocaman et al. (US 2008/0007340) discloses a VGA circuit (50) comprising two switchable differential pairs (51,52) for adjusting signal gain of after progressively enabling or disabling pairs using an interleaved thermometer coding, where one pair is permanently enabled. The circuit also includes a load impedance component which is shared by each of differential pairs.
Geary et al. (US 10,263,815) discloses a continuous time linear equalizer, a variable gain circuit includes transistors having gate nodes respectively as a first and a second input node. A first transimpedance circuit is connected between the first input node and a first output node. A second transimpedance circuit is connected between the second input node and a second output node. A source node of each of the first transistor and the second transistor are commonly connected to one another. In the same or another equalizer, output nodes of a first frequency peaking circuit are connected to input nodes of a second frequency peaking circuit.
Mahendra et al. (US 2015/0194950) discloses a flip-flop circuit for enhancing clock rates in high speed electronic circuits, the flip-flop circuit having an input terminal, an output terminal, and a third terminal that controls the flow of signal from the input terminal to the output terminal, comprising: two latches arranged in a master-slave configuration such that the input terminal of the first latch is also the input terminal of the flip-flop and the output terminal of the second latch is also the output terminal of the flip-flop; and at least one feedback path that adds signal to the input of the flip-flop from one of the outputs of the two latches.
Wang et al. (US 2020/0091903) discloses a comparator circuitry includes an input pair circuit, a load circuit, and a compensation circuit. The input pair circuit is configured to compare a first input signal with a second input signal, in order to control a first bias current. The load circuit is coupled to the input pair circuit, and is configured to output an output signal having a first level from a first output terminal of the load circuit in response to the first bias current. The compensation circuit is coupled to the input pair circuit and the load circuit, and is configured to drain a compensation current from the first output terminal to a voltage source during the load circuit generates the output signal having a first level, in which the voltage source is configured to provide a voltage having a second level.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to John W Poos whose telephone number is (571)270-5077. The examiner can normally be reached M-Th 8-5.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jessica Han can be reached at 571-272-2078. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/JOHN W POOS/Primary Examiner, Art Unit 2843
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