Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Prior to issuing this Office Action a discussion was held with the applicant’s representative Carlos Guevara to compactly prosecute the application. However, no agreement was reached and it was agreed to issue the Office Action.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 8, 17, 20 are rejected under 35 U.S.C. 102(a)(1) and 102(a)(2) as being anticipated by Yu, US 2022/0376659 A1.
Regarding Claim 1, Yu teaches:
A learning system, comprising: a plurality of cores by which operations may be performed (Abstract: “a pool of processing units to perform one or more arithmetic operations and one or more signal selection operations, wherein each of the processing units in the pool is associated with at least one parameterized model”. The pool of processing units representative of the plurality of cores and the parameterized model representative of the learning system);
at least one processor that implements a core selection scheme whereby a subset of the plurality of cores is selected on which at least one operation is to be performed (paragraph 44: “The apparatus may further include a control block to configure and/or select, based on a first parameterized model, at least a first subset of the processing units to process the input signal”);
implements an operation selection scheme whereby a subset of the operations is selected for each core in the subset of the plurality of cores (paragraph 176: “the first subset of the processing units performs at least a first signal selection operation of the one or more signal selection operations”);
and wherein each core in the subset of the plurality cores performs the subset of the operations selected (paragraph 176: “the first subset of the processing units performs at least a first signal selection operation of the one or more signal selection operations”).
Regarding Claim 8, Yu further teaches:
The learning system of claim 1, wherein the operations include a weight update of a plurality of weights stored for a core, a transpose of the plurality of weights stored for the core, and a matrix multiplication of the plurality of weights stored for the core by at least one of a vector or a matrix (paragraphs 39, 112, 125: collectively teaching the updating of the model parameters that include the weights, data transformation of the received data that would include transposing weights, and matrix multiplication of weights).
Claim 17 is similar to Claim 1 and is rejected under the same rationale as stated above for that claim.
Regarding Claim 20, Yu further teaches:
The method of claim 17, further comprising: performing an inference using the plurality of cores (paragraph 137: “The trained parameterized model is then ready to be used for inference”);
determining weight updates for the plurality of cores;
wherein the performing, by each core in the subset of the plurality of cores, the subset of the operations for at least one iteration occurs after the performing the inference and determining the weight updates, wherein the selecting the subset of the plurality of cores, the selecting the subset of the operations, the performing the inference, the determining the weight updates, and the performing the subset of the operations at least once are within an epoch (paragraphs 156-157: discusses the learnable weights that are the weight updating);
and wherein the method further includes repeating the performing the inference, the determining the weight updates, the selecting the subset of the plurality of cores, the selecting the subset of the operations, and the performing the subset of the operations at least once for another epoch (paragraph 137: discusses the iterative procedure).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Yu, US 2022/0376659 A1, in view of Bartels, US 2018/0040149 A1.
Regarding Claim 2, with Yu teaching those limitations of the claim as previously pointed out, Yu may not have taught all of the following, however, Bartels shows:
The learning system of claim 1, wherein the operation selection scheme is a Lindenmayer selection scheme (paragraph 17: wherein a Lindenmayer selection system is described). (Emphasis added).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to use the teachings of Bartels with that of Yu for having a Lindenmayer selection scheme.
The ordinary artisan would have been motivated to modify Yu in the manner set forth above for the purposes of generation of geometric repeat patterns [Bartels: paragraph 17].
Claims 5-6, 11, 15 are rejected under 35 U.S.C. 103 as being unpatentable over Yu, US 2022/0376659 A1, in view of Meiri, US 2002/0169816 A1.
Regarding Claim 5, with Yu teaching those limitations of the claim as previously pointed out, Yu may not have taught all of the following, however, Meiri shows:
The learning system of claim 1, wherein the core selection scheme includes an initial subset of the plurality of cores selected based on random number generation (Abstract: “A particular resource is then selected by generating a random number and selecting that resource when the random number falls within the interval”. The resource being cores).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to use the teachings of Meiri with that of Yu for selecting cores based on random number generation.
The ordinary artisan would have been motivated to modify Yu in the manner set forth above for the purposes of ensuring resources/cores selected have desirable properties and have some probability of being selected [Meiri: paragraph 9].
Regarding Claim 6, Meiri further teaches:
The learning system of claim 5, wherein the random number generation is based on hardware properties of the plurality of cores (paragraphs 8, 10: “determining a score for that resource on the basis of a stochastic property of the resource and then defining an interval corresponding to the resource. The extent of that interval is selected to depend on the score for that resource. A random number, is then generated and that resource is selected if the random number falls within the interval defined for that resource”; and, “the resource is a processor”. The property can be any hardware property. Examiner’s note: see also Zhang, US 2025/0028576 A1, for example Abstract, where the hardware property of the processing unit/core such as temperature is discussed as a selection criterion).
Claim 11 is a combination of Claims 1, 5 and 6 and is rejected under the same rationale as stated above for those claims.
Claim 15 is similar to Claim 8 and is rejected under the same rationale as stated above for that claim.
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Yu, US 2022/0376659 A1, in view of Ioannou, US 2020/0356815 A1.
Regarding Claim 7, with Yu teaching those limitations of the claim as previously pointed out, Yu may not have taught all of the following, however, Ioannou shows:
The learning system of claim 1, wherein the plurality of cores is configured to operate in epochs, an epoch including the plurality of cores performing forward propagation, determination of weight updates for the plurality of cores, and each core in the subset of the plurality of cores performing the subset of the operations (paragraph 21: “the training data 112 are dynamically partitioned across workers 106 of the system 100. In some embodiments, this is achieved by shuffling S50 subsets TD1-TD8 of the training data 112 through workers 106 of the system 100. As a result, different subsets TD1-TD8 of the training data 112 are used by the workers 106 in the course of the training (e.g., over time, as training S30 proceeds). For example, each worker may operate with a different subset of the training data (e.g., which may be randomly selected) at every training epoch”. The training epoch necessarily including forward propagation and weight updates as known in the art for training a model).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to use the teachings of Ioannou with that of Yu for operating in epochs.
The ordinary artisan would have been motivated to modify Yu in the manner set forth above for the purposes of parallel training of machine learning models [Ioannou: Abstract].
Claims 9-10 are rejected under 35 U.S.C. 103 as being unpatentable over Yu, US 2022/0376659 A1, in view of Datta, US 2020/0042856 A1.
Regarding Claim 9, with Yu teaching those limitations of the claim as previously pointed out, Yu may not have taught all of the following, however, Datta shows:
The learning system of claim 1, further comprising: a plurality of junction logic modules interconnecting the plurality of cores, the plurality of junction logic modules selectively enabling the subset of the plurality of cores selected by the at least one processor (paragraph 41: “IPU 400 includes one or more network-on-chip (NoC) 405. In some embodiments, a partial sum NoC 451 interconnects the cores 403 and transports partial sums among them. In some embodiments, a separate parameter distribution NoC 452 connects cores 403 to memory 401 for distributing weights and instructions to cores”).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to use the teachings of Ioannou with that of Yu for interconnecting the plurality of cores.
The ordinary artisan would have been motivated to modify Yu in the manner set forth above for the purposes of guaranteeing access latencies [Datta: paragraph 62].
Regarding Claim 10, Datta further teaches:
The learning system of claim 1, wherein the plurality of cores include at least one of a plurality of accelerator cores, a plurality of graphics processing units, or a plurality of tiles, each of the plurality of tiles including a plurality of compute engines, each of the plurality of compute engines having a compute-in-memory (CIM) hardware module, the CIM hardware module including a plurality of storage cells storing a plurality of elements for a matrix and being configured to perform in parallel a plurality of vector-matrix multiplication operations for the plurality of elements (paragraph 39: “IPU 400 includes a plurality of cores 403. Each core 403 includes a neural computation unit 433, which is loaded with a neural network model from model memory 401. Each core also include a local activation memory 432. Input activations are provided from local activation memory 432 in advance of each computation step”. The cores serving as accelerator cores).
Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Yu, US 2022/0376659 A1, in view of Meiri, US 2002/0169816 A1, and further in view of Ioannou, US 2020/0356815 A1.
Claim 14 is similar to Claim 7 and is rejected under the same rationale as stated above for that claim.
Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over Yu, US 2022/0376659 A1, in view of Meiri, US 2002/0169816 A1, and further in view of Datta, US 2020/0042856 A1.
Claim 16 is a combination of Claims 9 and 10 and is rejected under the same rationale as stated above for those claims.
Claims 3-4, 12-13, 18-19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Examiner's Note:
The Examiner cites particular pages, sections, columns, line numbers, and/or paragraphs in the references as applied to the claims above for the convenience of the applicant. Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested that, in preparing responses, the applicant fully consider the references in its entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the examiner and the additional related prior arts made of record that are considered pertinent to applicant's disclosure to further show the general state of the art. The Examiner's interpretations in parenthesis are provided with the cited references to assist the applicants to better understand how the examiner interprets the prior art to read on the claims. Such comments are entirely consistent with the intent and spirit of compact prosecution.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. See PTO-892 for the relevant prior art where for example Zhang, US 2025/0028576 A1, teaches scheduling execution of machine learning model operations on a multiprocessor computing device.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DAVE MISIR whose telephone number is (571)272-5243. The examiner can normally be reached M-R 8-5 pm, F some hours.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Abdullah Al Kawsar can be reached at 5712703169. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/DAVE MISIR/Primary Examiner, Art Unit 2127
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