Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election of claims 1-11 in the reply filed on August 31, 2026 is acknowledged. Because applicant did not distinctly and specifically point out the supposed errors in the restriction requirement, the election has been treated as an election without traverse (MPEP § 818.01(a)).
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-7 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Byun et al. (US 2023/0081960).
Regarding claim 1, Byun discloses a semiconductor device, comprising:
a substrate (100) [Fig. 2];
a source structure (210/710) disposed on the substrate [Fig. 2];
a semiconductor structure (300) disposed above the source structure [Fig. 2];
a gate structure (410/420) disposed above the source structure and surrounding the semiconductor structure (300) [Figs. 2 and 5A]; and
a doped semiconductor layer (810) disposed between the source structure and the semiconductor structure [Fig. 2 and paragraph 0069].
Regarding claim 2, Byun discloses wherein an electrical resistivity of the doped semiconductor layer (810: e.g. doped silicon) [paragraph 0069] is lower than an electrical resistivity of the semiconductor structure (300: e.g. silicon) [paragraph 0051].
Regarding claim 3, Byun discloses wherein the source structure (210/710) comprises:
a conductive layer (210) [Fig. 2 and paragraph 0049]; and
a semiconductor layer (710) disposed between the conductive layer and the gate structure [Fig. 2 and paragraph 0048],
wherein the doped semiconductor layer (810) is located between the semiconductor layer (710) and the semiconductor structure (300) [Fig. 2].
Regarding claim 4, Byun discloses wherein an electrical resistivity of the doped semiconductor layer (810: e.g. doped silicon) [paragraph 0069] is lower than an electrical resistivity of the semiconductor layer (710: e.g. graphene) [paragraphs 0048 and 0058].
Regarding claim 5, Byun discloses wherein a dopant ion concentration in the doped semiconductor layer (810: e.g. doped silicon) [paragraph 0069] is higher than a dopant ion concentration in the semiconductor layer (710: e.g. graphene) [paragraphs 0048 and 0058].
Regarding claim 6, Byun discloses wherein the semiconductor structure comprises:
a gate dielectric layer (510) disposed above the source structure [Fig. 2 and paragraph 0048], wherein the gate dielectric layer (510/520) surrounds the doped semiconductor layer (at least a portion 810 located beneath channel 300) [Fig. 2 and 5A]; and
a channel layer (300) disposed on the gate dielectric layer, wherein the channel layer surrounds the doped semiconductor layer (at least a portion 810 located beneath channel 300) [Fig. 2 and 5A].
Regarding claim 7, Byun discloses wherein a dopant ion concentration in the doped semiconductor layer (810: e.g. doped silicon) [paragraph 0069] is higher than a dopant ion concentration in the channel layer (300: e.g. silicon) [paragraph 0051].
Claims 1-2, 6-7 and 10 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Sun et al. (US 2019/0305085).
Regarding claim 1,Sun discloses a semiconductor device, comprising:
a substrate (305) [Fig. 3];
a source structure (360) disposed on the substrate [Fig.3];
a semiconductor structure (320) disposed above the source structure [Fig. 3];
a gate structure (350) disposed above the source structure and surrounding the semiconductor structure (300) [Fig. 3]; and
a doped semiconductor layer (310) disposed between the source structure and the semiconductor structure [Fig. 3].
Regarding claim 2, Sun discloses wherein an electrical resistivity of the doped semiconductor layer (310: e.g. “More Doping”) is lower than an electrical resistivity of the semiconductor structure (320) [Fig. 3 and paragraph 0043].
Regarding claim 6, Sun discloses wherein the semiconductor structure comprises:
a gate dielectric layer (340) disposed above the source structure [Fig. 3], wherein the gate dielectric layer (340) surrounds the doped semiconductor layer (top portion, i.e. “More Doping” [Fig. 3 and paragraphs 0021 and 0043]; and
a channel layer (320) disposed on the gate dielectric layer, wherein the channel layer surrounds the doped semiconductor layer [Fig. 3 and paragraphs 0021 and 0043].
Regarding claim 7, Sun discloses wherein a dopant ion concentration in the doped semiconductor layer (310: e.g. “More Doping”) is higher than a dopant ion concentration in the channel layer (120) [Fig. 3 and paragraph 0043].
Regarding claim 10, Sun discloses wherein an upper surface (“More Doping”) of the doped semiconductor layer (310) is higher than a lower surface of the gate structure (350) [Fig. 3].
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 9 and 11 are rejected under 35 U.S.C. 103 as being unpatentable over Byun et al. (US 2023/0081960) in view of Balakrishnan et al. (US 9640667).
Regarding claim 9, Byun does not teach a barrier pattern.
Balakrishnan teaches a barrier pattern (144) disposed above the source structure (112), wherein the barrier pattern (144) surrounds the semiconductor structure (130), and at least a part of the barrier pattern (144) is located between the gate structure (150) and the semiconductor structure (130) [Fig. 1A and col. 5, lines 3-19].
Therefore, one of ordinary skill in the art, before the effective filing date of the claimed invention, would have been motivated to modify Byun by including a barrier pattern as taught by Balakrishnan because it helps to improve the electrical performance [col. 1, lines 14-28 and col. 5, lines 9-11].
Regarding claim 11, Byun discloses wherein the doped semiconductor layer comprises an n-type doped amorphous silicon layer (810: e.g. doped silicon) [paragraph 0069]. In regard to the limitation about the silicon being amorphous, the court has held that it is within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use as a matter of obvious design choice. In re Leshin, 125 USPQ 416 (CCPA 1960); Sinclair & Carroll Co. v. Interchemical Corp., 325 U.S. 327, 65 USPQ 297 (1945).
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claim 1 is provisionally rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-3 and 5-10 of copending Application No. 18/595332 (published as US 2025/0248070) in view of Byun et al. (US 2023/0081960). For example,
Regarding claim 1, claim 1 of copending Application No. 18/595332 discloses all the recited limitations except for the doped semiconductor layer.
Byun teaches a doped semiconductor layer (810) disposed between the source structure and the semiconductor structure [Fig. 2 and paragraph 0069].
Therefore, one of ordinary skill in the art, before the effective filing date of the claimed invention, would have been motivated to modify the copending Application No. 18/595332 by including the doped semiconductor layer as taught by Byun because it helps to improve process stability [paragraph 0063-064].
This is a provisional nonstatutory double patenting rejection.
Allowable Subject Matter
Claim 8 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JOSE R DIAZ whose telephone number is (571)272-1727. The examiner can normally be reached Monday-Friday.
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/Jose R Diaz/Primary Examiner, Art Unit 2815
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