DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d). The certified copy has been filed in parent Application No. JAPAN 2022-187418, filed on 11/24/2022.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 09/11/2025 and 04/02/2024. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Drawings
Figure 5 (paragraph 0012, which disclosed as Conventional circuit) should be designated by a legend such as --Prior Art-- because only that which is old is illustrated. See MPEP § 608.02(g). Corrected drawings in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. The replacement sheet(s) should be labeled “Replacement Sheet” in the page header (as per 37 CFR 1.84(c)) so as not to obstruct any portion of the drawing figures. If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 2, 5, 12 & 15 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claims 2 & 12 recites the limitation "the four-terminal" in line 5. There is insufficient antecedent basis for this limitation in the claim.
Claims 5 & 15 is rejected due to their dependency.
Clarification is needed.
For the purpose of the examining, the examiner will read “the four-terminal” as ---the one four-terminal---.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 3, 6-8, 11, 13 & 16 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Saito (JP 2017157797 A, of record).
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Regarding claim 1:
Saito discloses in annotated Fig. 1, a class D amplification circuit comprising:
a PWM circuit (PWM);
a drive circuit (circuits 11 & 13) connected to the PWM circuit; and
a low-pass filter circuit (circuit 15) connected to the drive circuit;
wherein the low-pass filter circuit includes an inductor (L1), a first capacitor (C1), and a second capacitor (C2); the first capacitor and the second capacitor each include a dielectric body (see abstract, dielectric layers) and electrodes with the dielectric body therebetween;
the low-pass filter circuit includes an input terminal (terminal T1), a first potential terminal (annotated T2), a second potential terminal (annotated T3), and an output terminal (17); the input terminal ( terminal T1) is connected to the drive circuit (circuits 11 and 13); the first potential terminal (T2) is connected to a first potential (VDD); the second potential terminal (T2) is connected to a second potential (ground) that is lower than the first potential; the output terminal (17) is connected to a load circuit (speaker 19);
one external electrode (annotated Ext1, any a connection point between T2 and C1) of the first capacitor (C1) is connected to the first potential terminal (VDD); one external electrode (annotated Ext2, any connection point between T3 and C2) of the second capacitor (C2) is connected to the second potential terminal (ground terminal); another external electrode (Ext1a) of the first capacitor (C1) and another external electrode (Ext2a) of the second capacitor (C2) are connected to the output terminal (17);
one external electrode (Lx1) of the inductor (L1) is connected to the input terminal (T1); and another external electrode (Lx2) of the inductor is connected to the output terminal (17).
Regarding claim 3:
Saito discloses in annotated Fig. 1, wherein the load circuit includes a speaker (speaker 19).
Regarding claim 6:
Saito discloses in annotated Fig. 1 and Figs. 2A, 2B and 2C and related text “ceramic”, wherein the first capacitor (C1) and the second capacitor (C2) are a multilayer ceramic capacitor or a film capacitor.
Regarding claim 7:
Saito discloses in annotated Fig. 1, wherein the first capacitor (C1) and the second capacitor (C2) define a lumped-constant circuit (capacitors C1 & C2).
Regarding claim 8:
Saito discloses in annotated Fig. 1,wherein the first capacitor (C1) and the second capacitor (C2) reduce influence from variation in an input voltage on an output signal (capacitors C1 and C2 arrange in the same manner as shown in Fig. 1 of the applicant).).
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Regarding claim 11:
Saito discloses in annotated Fig. 5, a class D amplification circuit comprising:
a PWM circuit (PWM);
a first drive circuit (DR1) connected to the PWM circuit;
a second drive circuit (DR2) connected to the PWM circuit; and
a differential-signal filter circuit (annotated DiffFLT) connected to the first drive circuit (DR1) and the second drive circuit; wherein the differential-signal filter circuit includes a first inductor (L1a) , a second inductor (L2a), a first capacitor (C1a), and a second capacitor (C2a); the first capacitor (C1a) and the second capacitor (C2a) each include a dielectric body (see Figs. 6A, 6B and 6C, see abstract dielectric) and electrodes with the dielectric body therebetween;
the differential-signal filter circuit (DiffFLT) includes a first input terminal (IP1), a second input terminal (IP2), a first output terminal (T3a), a second output terminal (T4a), and a reference potential terminal (ground terminal); the first input terminal (IP1) is connected to the first drive circuit (DR1); the second input terminal (IP2) is connected to the second drive circuit (DR2);
the reference potential terminal (ground terminal) is connected to a reference potential (ground); the first output terminal (T3a) and the second output terminal (T4a) are connected to a load circuit (load 19a);
one external electrode (Ext1) of the first capacitor (C1a) is connected to the first output terminal (T3a);
one external electrode (Ext4) of the second capacitor (C2a) is connected to the second output terminal (T4a);
another external electrode (Ext2) of the first capacitor (C1a) and another external electrode (Ext3) of the second capacitor (C2a) are connected to the reference potential terminal (ground terminal);
one external electrode (Ext5) of the first inductor (L1a) is connected to the first input terminal (T1a);
another external electrode (Ext6) of the first inductor L1a) is connected to the first drive circuit (DR1);
one external electrode (Ext7) of the second inductor (L2a) is connected to the second input terminal (IP2); and another external electrode (Ext8) of the second inductor (L2a) is connected to the second drive circuit (DR2).
Regarding claim 13:
Saito discloses in annotated Fig. 5, wherein the load circuit includes a speaker (speaker 19a).
Regarding claim 16:
Saito discloses in annotated Fig. 5 and Figs. 6A, 6B and 6C, wherein the first capacitor (C1) and the second capacitor (C2) are a multilayer ceramic capacitor (Figs. 6A, 6B and 6C) or a film capacitor.
Regarding claim 17:
Saito discloses in annotated Fig. 5 and Figs. 6A, 6B and 6C, wherein the first capacitor (C1a) and the second capacitor (C2a) define a lumped-constant circuit (capacitor C1a and C2a).
Regarding claim 18:
Saito discloses in annotated Fig. 5, wherein the first capacitor (C1a) and the second capacitor (C2a) reduce influence from variation in an input voltage on an output signal (capacitors C1a & C2a as arrange in the same manner as shown in Fig. 15 of the applicant).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 4, 9-10, 14 & 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over Saito.
Regarding claims 4, 9-10, 14 & 19-20:
Saito discloses the structure and arrange of first and second capacitor as shown in Fig. 9 and the limitations as applied in claim 1 except for a difference between a capacitance of the first capacitor and a capacitance of the second capacitor is within about ±50%; and a capacitance ratio between the first capacitor and the second capacitor is about ±50%; and a capacitance ratio between the first capacitor and the second capacitor is about ±10%. It would have been obvious to one having ordinary skill in the art at the time the invention was made to set or select a difference between a capacitance of the first capacitor and a capacitance of the second capacitor is within about ±50%; and a capacitance ratio between the first capacitor and the second capacitor is about ±50%; and a capacitance ratio between the first capacitor and the second capacitor is about ±10%, since it has been held that discovering an optimum value of a result effective variable involves only routine skill in the art. In re Boesch, 617 F.2d 272, 205 USPQ 215 (CCPA 1980).
Allowable Subject Matter
Claims 2, 5, 12 & 15 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, and if rewritten in independent form including all of the limitations of the base claim and any intervening claims as set forth in this Office action.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US 20070139103 A1: Fig. 1 of Roeckner et al. discloses an amplifier circuit comprising PWM Adjust 116 connected to driver controls 132 and 134 and wherein circuit 160 which include inductor 162 and capacitor 64, connected to driver 132 via transistor 140 or 136; and circuit 170 connected to driver 134 via transistor 146 or transistor 150.
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/KHIEM D NGUYEN/Examiner, Art Unit 2843
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