DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed. For example, a more descriptive title could be, “Semiconductor Device With Multi Gate Structure Having Different Number of Sheet Patterns”.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 4 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 4 is indefinite because it is not clear how the same distance could be different from itself. For the purpose of examination, claim 1 is interpreted as follows:
The semiconductor device of claim 1,
wherein a distance from an upper surface of the lower pattern to a lower surface of the first gate capping pattern is different from a distance from the upper surface of the lower pattern to the lower surface of the second gate capping pattern.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-6 and 18-20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Ohtou et al. (US 2021/0296317 A1; hereinafter, “Ohtou”).
Regarding claims 1-6 and 18-20
re claim 1, Ohtou discloses (in Fig. 18) a semiconductor device comprising:
a lower pattern 200/905/910 that extends in a first direction (x-direction in Fig. 18);
a first channel pattern 810 [0065]on the lower pattern, and includes a plurality of first sheet patterns 510 [0026] spaced apart in a second direction (z-direction in Fig. 18) that is different from the first direction (x-direction);
a second channel pattern 810’ [0065]on the lower pattern, includes a plurality of second sheet patterns 510 spaced apart in the second direction (z-direction), and is spaced apart from the first channel pattern in the first direction (x-direction);
a first gate structure 1310 [0055] which extends around the first sheet pattern 810 in a plane including the first direction and the second direction (i.e., in a plane of the page on which Fig. 18 is shown), and includes a first gate electrode and a first gate insulating film 1305 ([0055-0056] and see Fig. 14 in addition to Fig. 18);
a second gate structure 1310 which extends around the second sheet pattern 810’ in the plane including the first direction and the second direction, and includes a second gate electrode 1310 and a second gate insulating film 1305;
a first gate capping pattern 1320 ([0062] that is directly above 810) on the first gate structure 810; and
a second gate capping pattern 1320 (that is directly above 810’ in Fig. 18) on the second gate structure 810’,
wherein a number of first sheet patterns 510 (in stack 810) is different from a number of second sheet patterns 510 (in stack 810’), and
wherein a thickness of the first gate capping pattern 1320 (directly above 810) is different from a thickness of the second gate capping pattern 1320 (directly above 810’) in the second direction (z-direction in Fig. 18);
re claim 2, the semiconductor device of claim 1,
wherein the number of the first sheet patterns 510 (in stack 810 in Fig. 18) is greater than the number of the second sheet patterns 510 (in stack 810’ in Fig. 18), and the thickness of the first gate capping pattern 1320 (directly above 810 in Fig. 18) is less than the thickness of the second gate capping pattern 1320 (directly above 810’ in Fig. 18);
re claim 3, the semiconductor device of claim 2,
wherein a distance from an upper surface of the lower pattern 200/905/910 (Fig. 18) to an upper surface of the first gate capping pattern 1320 is same as a distance from the upper surface of the lower pattern 200/905/910 to an upper surface of the second gate capping pattern 1320;
re claim 4(as interpreted), the semiconductor device of claim 1,
wherein a distance from an upper surface of the lower pattern 200/905/910 (Fig. 18) to a lower surface of the first gate capping pattern 1320 (directly above 810 in Fig. 18) is different from a distance from the upper surface of the lower pattern to the lower surface of the second gate capping pattern 1320 (directly above 810’ in Fig. 18);
re claim 5, the semiconductor device of claim 1,
wherein the thickness of the first gate capping pattern 1320 (directly above 810 in Fig. 18) in a portion overlapping the first channel pattern in the second direction (z-direction) is different from the thickness of the second gate capping pattern 1320 (directly above 810’ in Fig. 18) in a portion overlapping the second channel pattern in the second direction (z-direction);
re claim 6, the semiconductor device of claim 1, further comprising:
a source/drain pattern 1000 (Fig. 10 and [0045]) on the lower pattern and electrically connected to the first channel pattern and the second channel pattern, wherein the source/drain pattern is in contact with each of the first sheet patterns and each of the second sheet patterns (e.g., see Fig. 9-10, wherein stacks 810 contact S/D 1000);
re claim 18, Ohtou discloses (in Fig. 18) a semiconductor device comprising:
a lower pattern 200/905/210;
a first channel pattern 810 on the lower pattern, and includes a plurality of first sheet patterns 510;
a second channel pattern 810’ on the lower pattern and includes a plurality of second sheet patterns 510, wherein a number of the second sheet patterns included in the second channel pattern is less than a number of the first sheet patterns included in the first channel pattern;
a source/drain pattern 1000 (Fig. 10) on the lower pattern and electrically connected to the first channel pattern and the second channel pattern;
a first gate electrode 1310 (above 810 in Fig. 18) which extends around the first sheet pattern in a cross-sectional view;
a second gate electrode 1310 (above 810’ in Fig. 18) which extends around the second sheet pattern in the cross-sectional view;
a first gate capping pattern 1320 (above 810 in Fig. 18) on the first gate electrode; and
a second gate capping pattern 1320 (above 810’ in Fig. 18) on the second gate electrode,
wherein in the cross-sectional view (as viewed in Fig. 18), a distance from an upper surface of the lower pattern 200/905/910 to an upper surface of the first gate electrode 1310 (above 810 in Fig 18) is greater than a distance from the upper surface of the lower pattern to an upper surface of the second gate electrode 1310 (next to 810’ in Fig. 18);
re claim 19, the semiconductor device of claim 18,
wherein an upper surface of the first gate capping pattern 1320 (above 810 in Fig. 18) is on a same plane as an upper surface of the second gate capping pattern 1320 (above 810’ in Fig. 18); and
re claim 20, the semiconductor device of claim 18,
wherein an upper surface of the source/drain pattern 1000 (Fig. 10 has an inclined surface in the cross-sectional view (i.e., in Fig. 10 cross-sectional view, pattern 1000 has an inclined upper surface).
Therefore, Ohtou anticipates claims 1-6 and 18-20.
Allowable Subject Matter
Claims 12-17 are allowed.
Claims 7-11 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Claim 7 is allowed primarily because the prior art of record cannot anticipate or render obvious the limitations in this claim (when combined with claims 1 and 6);
Claim 8 is allowed primarily because the prior art of record cannot anticipate or render obvious the limitations in this claim (when combined with claims 1 and 6);
Claims 9-11 are allowed primarily because the prior art of record cannot anticipate or render obvious the limitations in claim 9 (when combined with claim 1) and claims 10-11 depend from claim 9; and
Claims 12-17 are allowed primarily because the prior art of record cannot anticipate or render obvious the following limitations, in combination as recited in independent claim 12: wherein a distance from an upper surface of the lower pattern to an upper surface of the first portion of the first gate electrode is different from a distance from the upper surface of the lower portion to an upper surface of the first portion of the second gate electrode.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to LEX H MALSAWMA whose telephone number is (571)272-1903. The examiner can normally be reached M-F (4-12 Hours, between 5:30AM-10PM).
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/LEX H MALSAWMA/Primary Examiner, Art Unit 2892
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