DETAILED ACTION
The present application is being examined under the pre-AIA first to invent provisions.
Applicant’s response dated 11/10/2025 has been received and entered. Claims 2-5 are remaining pending in the application.
Drawings
The drawings stand objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the circuit arrangement of the flip flop including “a gate of the fourth transistor is electrically connected to the gate of the second transistor” combined with “the other of the source and the drain of the sixth transistor is electrically connected to a first signal line” must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
It is noted that although Applicant’s fig. 4B does show the limitation of “the other of the source and the drain of the sixth transistor (106) is electrically connected to a first signal line (121)”, Applicant’s fig. 4C does not show the whole flip-flop circuit including the limitations of “a gate of the fourth transistor is electrically connected to the gate of the second transistor” and “the other of the source and the drain of the sixth transistor is electrically connected to a first signal line” as claimed. In other words, Applicant’s fig. 4B or fig. 4C alone does not show all claimed limitations and fails to comply with 37 CFR 1.121(d).
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 2-5 stand rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Claims 2-5 recite the combination of the limitation of “a gate of the fourth transistor is electrically connected to the gate of the second transistor” and “the other of the source and the drain of the sixth transistor is electrically connected to a first signal line” that is not disclosed in the original specification. The added the such limitation may change the scope of the invention, and it would add a new matter as well.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 2-5 stand rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claims 2-5, it is confusing and unclear how “a gate of the fourth transistor is electrically connected to the gate of the second transistor” can be combined with “the other of the source and the drain of the sixth transistor is electrically connected to a first signal line” im the same flip-flop circuit as claimed. According to the drawings, the limitation of “a gate of the fourth transistor is electrically connected to the gate of the second transistor” does show in figure 4C and the limitation of “the other of the source and the drain of the sixth transistor is electrically connected to a first signal line” does show in figure 4B; however, there is no supporting in the original specification that those limitations can be combined/arranged in a same flip-flop circuit.
Appropriate correction the claimed language is required.
Applicant’s argument is that the specification provides support for the noted features of claims 2-5, by describing that elements in different embodiments may be combined, which would include implementing the diode-connected transistor 105 (in FIG. 4B) for the transistor 105 (in FIG. 4C). Thus, FIGS. 4B and 4C show an arrangement in which (1) a gate of the fourth transistor 402 is electrically connected to the gate of the second transistor 102 and (2) the other of the source and the drain of the sixth transistor 105 is electrically connected to a first signal line 121. The Examiner agrees that the combination of fig. 4B and 4C in some particular component(s) does meet the claimed limitations of “a gate of the fourth transistor is electrically connected to the gate of the second transistor” and “the other of the source and the drain of the sixth transistor is electrically connected to a first signal line”; however, there is not clearly supporting from the Applicant’s specification how to combine or arrange different component(s) from the different circuit (flip-flop 4B) to the flip-flop circuit 4C as claimed. Particularly, although paragraph [0098] states that the first to eighth transistors 101 to 108 are not limited to transistors as long as they have the aforementioned functions, paragraph [0098] does not state that each transistors having a same function in a different flip-flop circuit 4B or 4C can be exchanged and/or in a different way to connect in each transistors as a different flip-flop circuit as shown in each fig. 4B and 4C. In addition, paragraphs [0156]-[0157] do not clearly state what circuit arrangement, e.g., flip-flop or shift register or display device, with reference to various drawings can be freely applied or combined the circuit components/contents as shown in various drawings; as so, one skilled in the art would not be able to merely find how to combine with the circuit component(s) in the flip-flop circuit 4B and 4C to the claimed limitations.
Accordingly, the rejection of claims 2-5 stand as stated above.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DUNG T NGUYEN whose telephone number is (571)272-2297. The examiner can normally be reached 8:00 - 5:00.
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/DUNG T NGUYEN/Primary Examiner, Art Unit 2871