DETAILED ACTION
INFORMATION CONCERNING RESPONSES
Response to Amendment
This Office Action is in response to applicant’s communication filed on May 1, 2026, in response to PTO Office Action mailed on February 5, 2026. The Applicant’s remarks and amendments to the claims and/or the specification were considered with the results that follow.
In response to the last Office Action, claims 1-2, 5, 17, and 19 have been amended while claim 20 has been cancelled. As a result, claims 1-19 are now pending in this application.
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on May 1, 2026, has been entered.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d).
Response to Arguments
Applicant's arguments filed on May 1, 2026, in response to PTO Office Action mailed on February 5, 2026, have been fully considered and are persuasive. Hence, the rejection has been withdrawn. However, upon further review a new ground of rejection has been made in view of Gemmeke et al. (Publication Number US 2009/0115504 A1).
REJECTIONS BASED ON PRIOR ART
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103(a) which forms the basis for all obviousness rejections set forth in this Office action:
(a) A patent may not be obtained though the invention is not identically disclosed or described as set forth in section 102 of this title, if the differences between the subject matter sought to be patented and the prior art are such that the subject matter as a whole would have been obvious at the time the invention was made to a person having ordinary skill in the art to which said subject matter pertains. Patentability shall not be negatived by the manner in which the invention was made.
Claims 1-5 and 18-19 are rejected under 35 U.S.C. 103(a) as being unpatentable over Kang et al. (Publication Number US 2022/0147475 A1) in view of Gemmeke et al. (Publication Number US 2009/0115504 A1).
As per claim 1, Kang et al. discloses “An address extension circuit for configuring an address of a chip, wherein: a) the address extension circuit is configured to encode the address of the chip differently according to different state information of at least one address pin of the chip (an address allocator configured to designate the address of the serial communications slave based on a plurality of state bits determined depending on a connection state of the signal address determination pin; Paragraph 0010).”
However, Kang et al. does not disclose the arrangement of switches indicating a particular configuration as disclosed in the limitations “b) the state information of the address pin comprises being in a high-level state, being in a low-level state, floating, coupling with a communication input pin of the chip, and coupling with a communication output pin of the chip,” “c) the address extension circuit comprises a level acquisition circuit having a first power switch and a second power switch coupled in series, wherein a common terminal of the first and second power switches is coupled to the address pin, and the state information of the address pin is determined according to a voltage of the common terminal of the first and second power switches,” and “and d) when the first power switch is turned on, the voltage of the common terminal of the first and second power switches is at a high level, and when the second power switch is turned on, the voltage of the common terminal of the first and second power switches is at a low level, a determination is made that the address pin is floating.”
Gemmeke et al. discloses the arrangement of switches indicating a particular configuration as disclosed in the limitation “b) the state information of the address pin comprises being in a high-level state, being in a low-level state, floating, coupling with a communication input pin of the chip, and coupling with a communication output pin of the chip (transistor being marked with 1, 0, or y, with a common node marked with Z (tri-stated) or y (active); FIG. 2A-2B).”
Gemmeke et al. discloses the arrangement of switches indicating a particular configuration as disclosed in the limitation “c) the address extension circuit comprises a level acquisition circuit having a first power switch and a second power switch coupled in series, wherein a common terminal of the first and second power switches is coupled to the address pin, and the state information of the address pin is determined according to a voltage of the common terminal of the first and second power switches (see the transistor settings that can be 1, 0, or y; Paragraph 0032; FIG. 2A-2B).”
Gemmeke et al. discloses the arrangement of switches indicating a particular configuration as disclosed in the limitation “and d) when the first power switch is turned on, the voltage of the common terminal of the first and second power switches is at a high level, and when the second power switch is turned on, the voltage of the common terminal of the first and second power switches is at a low level, a determination is made that the address pin is floating (transistor being marked with 1 and 0 with the common node marked with Z (tri-stated) [FIG. 2A], or the transistor marked with y with the common node marked with y (active); FIG. 2B; Paragraph 0032).”
Before the effective filing date of the claimed invention it would have been obvious to a person of ordinary skill in the art to combine the elements of Kang et al. and Gemmeke et al. to allow for controlling leakage current and minimizing power dissipation [Paragraph 0014].
As per claim 2, Gemmeke et al. discloses “The address extension circuit of claim 1 (as disclosed by Kang et al. and Gemmeke et al. above), wherein: a) the first power switch and the second power switch coupled in series between a power supply and a ground potential terminal (transistors connected in series from a voltage source to ground; FIG. 2A-2B).” Kang et al. discloses “and b) in a detection interval, the first and second power switches are turned on in a time-sharing manner, and the state information of the address pin is determined according to a voltage of the common terminal of the first and second power switches, in order to encode the address of the chip (designating addresses; Paragraphs 0091-0094).”
As per claim 3, Kang et al. discloses “The address extension circuit of claim 2 (as disclosed by Kang et al. and Gemmeke et al. above), wherein when the first power switch and the second power switch are turned on in a time-sharing manner, the voltage of the common terminal of the first and second power switches is at a high level, a determination is made that the address pin is at a high level (where PU (connected to Vdd) is 1 while PD (connected to ground) is 0; FIG. 3 and 4).”
As per claim 4, Kang et al. discloses “The address extension circuit of claim 2 (as disclosed by Kang et al. and Gemmeke et al. above), wherein when the first power switch and the second power switch are turned on in a time-sharing manner, the voltage of the common terminal of the first and second power switches is at a low level, a determination is made that the address pin is at a low level (where PU (connected to Vdd) is 0 while PD (connected to ground) is 1; FIG. 3 and 4).”
As per claim 5, Gemmeke et al. discloses “The address extension circuit of claim 2 (as disclosed by Kang et al. and Gemmeke et al. above), wherein when the first power switch is turned on while the second power switch is off, the voltage of the common terminal of the first and second power switches is at a high level (transistor being marked with 1 and 0 with the common node marked with Z (tri-stated) [FIG. 2A], or the transistor marked with y with the common node marked with y (active); FIG. 2B; Paragraph 0032), and when the second power switch is turned on while the first power switch is off, the voltage of the common terminal of the first and second power switches is at a low level, a determination is made that the address pin is floating (transistor being marked with 1 and 0 with the common node marked with Z (tri-stated) [FIG. 2A], or the transistor marked with y with the common node marked with y (active); FIG. 2B; Paragraph 0032).”
As per claim 18, Kang et al. discloses “The address extension circuit of claim 1 (as disclosed by Kang et al. and Gemmeke et al. above), wherein the state information of the address pin comprises at least three of being in a high-level state (where ‘PU On’ and ‘PD Off’ is 1; FIG. 4), being in a low-level state (where ‘PU Off’ and ‘PD On’ is 1; FIG. 1), floating (where ‘PU Off’ and ‘PD Off’ is 1; FIG. 4), coupling with the communication input pin, and coupling with the communication output pin (see connections to the state determination unit 102 in relationship to the PU and PD switches; FIG. 1).”
As per claim 19, Kang et al. discloses “A communication interface chip, comprising the address extension circuit of claim 1 (as disclosed by Kang et al. and Gemmeke et al. above), and being configured in an integrated circuit (suitable results may be achieved if the described techniques are performed in a…circuit; Paragraph 0121).”
Claims 6-9, 11-12, 14-15, and 17 are rejected under 35 U.S.C. 103(a) as being unpatentable over Kang et al. (Publication Number US 2022/0147475 A1) and Gemmeke et al. (Publication Number US 2009/0115504 A1) in view of Floyd (Patent Number US 4,628,480).
As per claim 6, Kang et al. and Gemmeke et al. disclose “The address extension circuit of claim 2 (as disclosed by Kang et al. and Gemmeke et al. above).” While Kang et al. discloses determining state of the pins [see connections to the state determination unit 102 in relationship to the PU and PD switches; FIG. 1 and 4], Kang et al. and Gemmeke et al. do not disclose the time-sharing aspect as disclosed in the limitation “wherein when the first power switch and the second power switch are turned on in a time-sharing manner, the voltage of the common terminal of the first and second power switches has both a high level and a low level in turn-on periods of the first and second power switches, a determination is made that the address pin is coupled with the communication input pin or the communication output pin.”
Floyd discloses the time-sharing aspect as disclosed in the limitation “wherein when the first power switch and the second power switch are turned on in a time-sharing manner, the voltage of the common terminal of the first and second power switches has both a high level and a low level in turn-on periods of the first and second power switches, a determination is made that the address pin is coupled with the communication input pin or the communication output pin (note that the state of the pins has been disclosed by Kang et al. in [FIG. 1 and 4], Floyd is directed to the time-sharing aspect on the same actual signal pins; Column 17, lines 11-31).”
Kang et al. and Floyd are analogous art in that they in the field of signaling as they pertain to addressing.
Before the effective filing date of the claimed invention it would have been obvious to a person of ordinary skill in the art to combine the elements of Kang et al. and Gemmeke et al. with elements of Floyd to allow the use of pins for other functions in contrast to prior art systems [Column 1, lines 29-47].
As per claim 7, Kang et al. and Gemmeke et al. disclose “The address extension circuit of claim 2 (as disclosed by Kang et al. and Gemmeke et al. above).” While Kang et al. discloses determining state of the pins [see connections to the state determination unit 102 in relationship to the PU and PD switches; FIG. 1 and 4], Kang et al. and Gemmeke et al. do not disclose signal inversion as disclosed in the limitation “the address extension circuit further comprises: a) a gating circuit configured to transmit a first signal representing level information of the address pin generated by the level acquisition circuit and an inverted signal of the first signal to a level information processing circuit in a time-sharing manner” and “and b) the level information processing circuit being configured to latch the first signal representing the level information of the address pin and the inverted signal of the first signal to obtain a plurality of state indication signals, wherein the plurality of state indication signals represent the state information of the address pin.”
Floyd discloses signal inversion as disclosed in the limitation “the address extension circuit further comprises: a) a gating circuit configured to transmit a first signal representing level information of the address pin generated by the level acquisition circuit and an inverted signal of the first signal to a level information processing circuit in a time-sharing manner (Column 18, lines 32-47).” Floyd discloses signal inversion as disclosed in the limitation “and b) the level information processing circuit being configured to latch the first signal representing the level information of the address pin and the inverted signal of the first signal to obtain a plurality of state indication signals, wherein the plurality of state indication signals represent the state information of the address pin (Column 18, lines 32-47).”
Kang et al. and Floyd are analogous art in that they in the field of signaling as they pertain to addressing.
Before the effective filing date of the claimed invention it would have been obvious to a person of ordinary skill in the art to combine the elements of Kang et al. and Gemmeke et al. with elements of Floyd to allow the use of pins for other functions in contrast to prior art systems [Column 1, lines 29-47].
As per claim 8, Kang et al. discloses “The address extension circuit of claim 7 (as disclosed by Kang et al., Gemmeke et al., and Floyd above), wherein the level acquisition circuit further comprises a comparison circuit for comparing the voltage of the common terminal of the first and second power switches (PU and PD; FIG. 5-8) against a first reference voltage (VDD; FIG. 5-8), in order to obtain the first signal representing the level information of the address pin (FIG. 4).”
As per claim 9, Kang et al. discloses “The address extension circuit of claim 7 (as disclosed by Kang et al., Gemmeke et al., and Floyd above), wherein: a) when the first power switch is turned on, the gating circuit transmits the first signal representing the level information of the address pin to the level information processing circuit to generate a first state indication signal (see connections to the state determination unit 102 in relationship to the PU and PD switches; FIG. 1 and 4).” Kang et al. discloses “and b) when the second power switch is turned on, the gating circuit transmits the first signal representing the level information of the address pin to the level information processing circuit to generate a second state indication signal, and the gating circuit transmits the inverted signal of the first signal to the level information processing circuit to generate a third state indication signal (see connections to the state determination unit 102 in relationship to the PU and PD switches; FIG. 1).”
As per claim 11, Kang et al. discloses “The address extension circuit of claim 9 (as disclosed by Kang et al., Gemmeke et al., and Floyd above), wherein: a) during a turn-on period of the first power switch, when the first signal has a high level, the first state indication signal is maintained at a high level during the detection interval (see connections to the state determination unit 102 in relationship to the PU and PD switches; FIG. 1 and 4).” Kang et al. discloses “and b) during a turn-on period of the second power switch, when the first signal has a high level, the second state indication signal is maintained at a high level during the detection interval, and when the first signal has a low level, the third state indication signal is maintained at a high level during the detection interval (see connections to the state determination unit 102 in relationship to the PU and PD switches; FIG. 1 and 4).”
As per claim 12, Kang et al. discloses “The address extension circuit of claim 11 (as disclosed by Kang et al., Gemmeke et al., and Floyd above), wherein: a) when the first state indication signal is at a high level, the second state indication signal is at a high level, and the third state indication signal is at a low level, this indicates that the address pin is at a high level (example is the third row with the third address TCOM; FIG. 4).” Kang et al. discloses “b) when the first state indication signal is at a low level, the second state indication signal is at a low level, and the third state indication signal is at a high level, this indicates that the address pin is at a low level (see example of the fourth address where only one signal is high; FIG. 4).” Kang et al. discloses “c) when the first state indication signal is at a high level, the second state indication signal is at a low level, and the third state indication signal is at a high level, this indicates that the address pin is floating (see example of the third row where two signals are high and one signal is low. There are also other signals variations including one where all signals are low; FIG. 4).” Kang et al. discloses “and d) when the first state indication signal is at a high level, the second state indication signal is at a high level, and the third state indication signal is at a high level, this indicates that the address pin is coupled with the communication input pin or the communication output pin (example is the first row with the first address TCOM; FIG. 4).”
As per claim 14, Kang et al. discloses “The address extension circuit of claim 7 (as disclosed by Kang et al., Gemmeke et al., and Floyd above), wherein the address extension circuit further includes an encoding circuit configured to encode the address of the chip according to the plurality of state indication signals (through a state determination unit 102 that sends address selections signals ASEL1 and ASEL2 to the serial communication slave; FIG. 1 and 4).”
As per claim 15, Kang et al. discloses “The address extension circuit of claim 14 (as disclosed by Kang et al., Gemmeke et al., and Floyd above), wherein the encoding circuit is configured to: a) when the first state indication signal is at a high level, the second state indication signal is at a high level, and the third state indication signal is at a low level, the address of the chip is encoded as a first address (example is the third row with the third address TCOM; FIG. 4).” Kang et al. discloses “b) when the first state indication signal is at a low level, the second state indication signal is at a low level, and the third state indication signal is at a high level, the address of the chip is encoded as a second address (see example of the fourth address where only one signal is high; FIG. 4).” Kang et al. discloses “c) when the first state indication signal is at a high level, the second state indication signal is at a low level, and the third state indication signal is at a high level, the address of the chip is encoded as a third address (see example of the third row where two signals are high and one signal is low. There are also other signals variations including one where all signals are low; FIG. 4).” Kang et al. discloses “and d) when the first state indication signal is at a high level, the second state indication signal is at a high level, and the third state indication signal is at a high level, the address of the chip is encoded as a fourth address (example is the first row with the first address TCOM; FIG. 4).”
As per claim 17, Kang et al. and Gemmeke et al. disclose “The address extension circuit of claim 16 (as disclosed by Kang et al. and Gemmeke et al. above).” However, Kang et al. and Gemmeke et al. do not disclose the PWM signal as disclosed in the limitation “wherein: a) during the detection interval, the communication input pin or the communication output pin outputs a pulse-width module (PWM) signal, and both the first control signal and the second control signal have at least one active interval” and “and b) during the active intervals of the first control signal and the second control signal, at least one pulse edge transition of the PWM signal occurs.”
Floyd discloses the PWM signal as disclosed in the limitation “wherein: a) during the detection interval, the communication input pin or the communication output pin outputs a PWM signal, and both the first control signal and the second control signal have at least one active interval (in the form of a pulse generating circuitry where each bit is of a certain period; Column 5, lines 13-49).” Floyd discloses “and b) during the active intervals of the first control signal and the second control signal, at least one pulse edge transition of the PWM signal occurs (in the form of a pulse generating circuitry where each bit is of a certain period; Column 5, lines 13-49).”
Kang et al. and Floyd are analogous art in that they in the field of signaling as they pertain to addressing.
Before the effective filing date of the claimed invention it would have been obvious to a person of ordinary skill in the art to combine the elements of Kang et al. and Gemmeke et al. with elements of Floyd to allow the use of pins for other functions in contrast to prior art systems [Column 1, lines 29-47].
Claims 10, 13, and 16 are rejected under 35 U.S.C. 103(a) as being unpatentable over Kang et al. (Publication Number US 2022/0147475 A1), Gemmeke et al. (Publication Number US 2009/0115504 A1), and Floyd (Patent Number US 4,628,480) in view of Vandersteegen (Publication Number US 2016/0261426 A1).
As per claim 10, Kang et al., Gemmeke et al., and Floyd disclose “The address extension circuit of claim 7 (as disclosed by Kang et al., Gemmeke et al., and Floyd above).” However, Kang et al., Gemmeke et al., and Floyd do not disclose more than two switches as disclosed in the limitation “wherein: a) the level information processing circuit comprises a first RS latch, a second RS latch, and a third RS latch,” “b) when the first power switch is turned on, the gating circuit transmits the first signal to a set terminal of the first RS latch, and an output terminal of the first RS latch generates a first state indication signal,” and “and c) when the second power switch is turned on, the gating circuit transmits the first signal to a set terminal of the second RS latch, an output terminal of the second RS latch generates a second state indication signal, the gating circuit transmits the inverted signal of the first signal to a set terminal of the third RS latch, and an output terminal of the third RS latch generates a third state indication signal.”
Vandersteegen discloses more than two switches as disclosed in the limitation “wherein: a) the level information processing circuit comprises a first RS latch, a second RS latch, and a third RS latch (switching means 11 and 13, with one instance connected nearest to Vref and a second instance connected to GND; FIG. 3; Paragraphs 0061, 0063-0064, and 0066).”
Vandersteegen discloses more than two switches as disclosed in the limitation “b) when the first power switch is turned on, the gating circuit transmits the first signal to a set terminal of the first RS latch, and an output terminal of the first RS latch generates a first state indication signal (switching means 11 and 13, with one instance connected nearest to Vref and a second instance connected to GND; FIG. 3; Paragraphs 0061, 0063-0064, and 0066).”
Vandersteegen discloses more than two switches as disclosed in the limitation “and c) when the second power switch is turned on, the gating circuit transmits the first signal to a set terminal of the second RS latch, an output terminal of the second RS latch generates a second state indication signal, the gating circuit transmits the inverted signal of the first signal to a set terminal of the third RS latch (Floyd discloses the inversion in [Column 18, lines 32-47]), and an output terminal of the third RS latch generates a third state indication signal (switching means 11 and 13, with one instance connected nearest to Vref and a second instance connected to GND; FIG. 3; Paragraphs 0061, 0063-0064, and 0066).”
Before the effective filing date of the claimed invention it would have been obvious to a person of ordinary skill in the art to combine the elements of Kang et al., Gemmeke et al., and Floyd with Vandersteegen to differentiate substantially identical ICs connected to the same data bus [Paragraph 0003] while avoiding the disadvantage of requiring one more additional wires [Paragraph 0005].
As per claim 13, Vandersteegen discloses “The address extension circuit of claim 10 (as disclosed by Kang et al., Gemmeke et al., Floyd, and Vandersteegen above), wherein the gate circuit comprises: a) a third power switch having a first terminal coupled to an output terminal of the level acquisition circuit and a second terminal coupled to the set terminal of the first RS latch (switching means 11 and 13, with one instance connected nearest to Vref and a second instance connected to GND; FIG. 3; Paragraphs 0061, 0063-0064, and 0066).” Vandersteegen discloses “b) a fourth power switch having a first terminal coupled to the output terminal of the level acquisition circuit and a second terminal coupled to the set terminal of the second RS latch (switching means 11 and 13, with one instance connected nearest to Vref and a second instance connected to GND; FIG. 3; Paragraphs 0061, 0063-0064, and 0066).” Vandersteegen discloses “c) a fifth power switch having a first terminal coupled to the output terminal of the level acquisition circuit through a first inverter and a second terminal coupled to the set terminal of the third RS latch (switching means 11 and 13, with one instance connected nearest to Vref and a second instance connected to GND; FIG. 3; Paragraphs 0061, 0063-0064, and 0066).” Vandersteegen discloses “and d) wherein switching states of the third power switch and the first power switch are the same, and switching states of the fourth power switch, the fifth power switch and the second power switch are the same (switching means 11 and 13, with one instance connected nearest to Vref and a second instance connected to GND; FIG. 3; Paragraphs 0061, 0063-0064, and 0066).”
As per claim 16, Vandersteegen discloses “The address extension circuit of claim 13 (as disclosed by Kang et al., Gemmeke et al., Floyd, and Vandersteegen above), further comprising a control circuit for generating a first control signal and a second control signal, wherein the first control signal is configured to control the first power switch and the third power switch, the second control signal is configured to control the second power switch, the fourth power switch and the fifth power switch, and active intervals of the first control signal and the second control signal do not overlap (switching means 11 and 13, with one instance connected nearest to Vref and a second instance connected to GND; FIG. 3; Paragraphs 0061, 0063-0064, and 0066).”
RELEVENT ART CITED BY THE EXAMINER
The following prior art made of record and relied upon is citied to establish the level of skill in the applicant’s art and those arts considered reasonably pertinent to applicant’s disclosure. See MPEP 707.05(c).
The following references teach data transfer as they pertain to switch arrangements affecting the state of a pin:
U.S. PATENT NUMBERS:
2010/0219845 A1 – [Paragraph 0006]
2018/0366966 A1 – [Paragraph 0033]
2021/0135670 A1 – [FIG. 1; Paragraph 0025]
CONCLUDING REMARKS
Conclusion
The examiner requests, in response to this Office action, support be shown for language added to any original claims on amendment and any new claims. That is, indicate support for newly added claim language by specifically pointing to page(s) and line no(s) in the specification and/or drawing figure(s). This will assist the examiner in prosecuting the application.
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/H.W.Y/Examiner, Art Unit 2181 July 2, 2026
/IDRISS N ALROBAYE/Supervisory Patent Examiner, Art Unit 2181
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