Prosecution Insights
Prosecution Insights
Technology areas: Computing & Software • Semiconductors, Circuits & Optics
10 pending office actions • 6 art units • 10 examiners • 0 of 10 (0%) have an AI response strategy ready • 24 patents granted in the last 365 days
Silergy Semiconductor Technology (Hangzhou) Ltd. has 10 pending office actions in the Semiconductors, Circuits & Optics technology area. These 10 actions are distributed among 10 distinct examiners, meaning every pending matter is being reviewed by a different individual. This distribution of 10 distinct examiners for 10 pending office actions requires the company to manage ten separate examiner relationships simultaneously. Practitioners must be prepared to navigate these different perspectives across the Semiconductors, Circuits & Optics portfolio.
The workload is spread across 6 distinct art units, showing a significant range of technical sub-specialties within the semiconductor and optics field. Harry Raymond Behm is the busiest examiner for the portfolio, currently managing 1 pending office action. This 1 action is part of the total 10 pending office actions currently facing the organization. The presence of 6 distinct art units indicates that the company's research falls into many different specialized administrative categories within the USPTO.
The involvement of 10 distinct examiners and 6 distinct art units creates a diverse prosecution landscape. The company must ensure that its responses are consistent across 6 different administrative groups while addressing the specific feedback of 10 different examiners. This complexity underscores the need for a coordinated approach to the 10 pending office actions. Practitioners should focus on the specific requirements of each of the 6 distinct art units while addressing the 1 pending office action under Harry Raymond Behm and the other nine matters individually.
Based on the USPTO statutory response window for each pending office action. 6 of the docket's apps have a known mailing date; the rest are excluded from the tile counts.
Every pending office action with a known statutory deadline, placed on a days-until-due axis. Dots left of Today are overdue; the further right, the more runway. Cases that share a deadline window stack vertically. 6 of the docket's apps have a known mailing date.
Difficulty is derived from the rejection statutes on the most recent pending office action. §101-driven and multi-statute cases are graded Hard; §112-only and obviousness-type double-patenting cases are graded Easy; everything else is Medium. "Unknown" means we have not yet parsed a statute for that office action.
| Bucket | Cases |
|---|---|
| §103 only | 4 (40%) |
| Multi-statute (no §101) | 6 (60%) |
How the docket's pending cases split across USPTO tech-center bands.
Manual office-action response work runs about 10 hours per case. The time-saved bands below show what IP Author's prosecution pipeline typically delivers — a conservative 20% on the low end, 35% in the middle, 50% on the high end.
| Examiner | Apps on this docket | Allow rate | Interview lift |
|---|---|---|---|
| BEHM, HARRY RAYMOND | 1 | 79.6% | +7.4% |
| PEREZ, BRYAN REYNALDO | 1 | 83.8% | +13.9% |
| HOQUE, MOHAMMAD M | 1 | 85.2% | +9.5% |
| BARTELS, CHRISTOPHER A. | 1 | 67.9% | +11.8% |
| RAMASWAMY, ARUN | 1 | 84.7% | +12.3% |
| ESIABA, NKECHINYERE OTUOMASIRICH | 1 | 57.9% | +47.1% |
| YU, HENRY W | 1 | 69.6% | +28.3% |
| BAIG, ANEESA RIAZ | 1 | 93.8% | +7.9% |
| NGUYEN, DUY T V | 1 | 78.9% | +16.7% |
| TRAN, NGUYEN | 1 | 83.6% | +7.5% |
Cases in front of an examiner with an allow rate of 80%+ where the difficulty is Easy or Medium. The top 2 ordered by deadline are shown.
| App # | Title | Examiner | Due in |
|---|---|---|---|
| 17743646 | POWER CONVERTER | TRAN, NGUYEN | 132d overdue |
| 18141510 | STACKED PACKAGING STRUCTURE AND POWER CONVERTER | BAIG, ANEESA RIAZ | 20d |
Multi-statute / §101-driven matters, or cases in front of an examiner with an allow rate under 30%. The top 6 ordered by deadline are shown.
| App # | Title | Examiner | Due in |
|---|---|---|---|
| 17886230 | ELECTRODE STRUCTURE, SEMICONDUCTOR STRUCTURE, AND MANUFACTURING METHOD OF ELECTRODE STRUCTURE | NGUYEN, DUY T V | 29d |
| 18760314 | CAPACITOR | RAMASWAMY, ARUN | 33d |
| 18999123 | CONTROL CIRCUIT AND SWITCHING POWER SUPPLY THEREOF | BEHM, HARRY RAYMOND | — |
| 18985337 | CONTROL CIRCUIT AND SWITCHING POWER SUPPLY | PEREZ, BRYAN REYNALDO | — |
| 18892513 | CURVED-GATE TRANSISTOR STRUCTURE | HOQUE, MOHAMMAD M | — |
| 18747608 | ETCHING METHOD FOR SEMICONDUCTOR STRUCTURE COMPRISING SUBSTRATE, FIRST STRUCTURE LOCATED ON PART OF TOP SURFACE OF THE SUBSTRATE, SIDEWALLS STRUCTURE AND FIELD EFFECT TRANSISTOR | ESIABA, NKECHINYERE OTUOMASIRICH | — |
Cases in front of an examiner whose interview lift is 10 percentage points or more — i.e. interviewed cases historically resolve more favorably than non-interviewed ones. The top 6 ordered by deadline are shown.
| App # | Title | Examiner | Due in |
|---|---|---|---|
| 18616411 | COMMUNICATION INTERFACE CHIP AND ADDRESS EXTENSION CIRCUIT THEREOF | YU, HENRY W | 23d overdue |
| 18764890 | SYNCHRONIZATION SIGNAL TRANSMISSION METHOD AND SERIAL COMMUNICATION SYSTEM | BARTELS, CHRISTOPHER A. | 22d |
| 17886230 | ELECTRODE STRUCTURE, SEMICONDUCTOR STRUCTURE, AND MANUFACTURING METHOD OF ELECTRODE STRUCTURE | NGUYEN, DUY T V | 29d |
| 18760314 | CAPACITOR | RAMASWAMY, ARUN | 33d |
| 18985337 | CONTROL CIRCUIT AND SWITCHING POWER SUPPLY | PEREZ, BRYAN REYNALDO | — |
| 18747608 | ETCHING METHOD FOR SEMICONDUCTOR STRUCTURE COMPRISING SUBSTRATE, FIRST STRUCTURE LOCATED ON PART OF TOP SURFACE OF THE SUBSTRATE, SIDEWALLS STRUCTURE AND FIELD EFFECT TRANSISTOR | ESIABA, NKECHINYERE OTUOMASIRICH | — |
| Art Unit | Apps |
|---|---|
| 2184 | 1 |
| 2847 | 1 |
| 2181 | 1 |
| 2814 | 1 |
| 2818 | 1 |
| 2838 | 1 |
| App # | Title | Examiner | Art Unit | Statutes | Status | Due in | AI | Filed |
|---|---|---|---|---|---|---|---|---|
| 18999123 | CONTROL CIRCUIT AND SWITCHING POWER SUPPLY THEREOF | BEHM, HARRY RAYMOND | — | §102§103§112 | Non-Final OA | — | Pending | Dec 23, 2024 |
| 18985337 | CONTROL CIRCUIT AND SWITCHING POWER SUPPLY | PEREZ, BRYAN REYNALDO | — | §102§103 | Non-Final OA | — | Pending | Dec 18, 2024 |
| 18892513 | CURVED-GATE TRANSISTOR STRUCTURE | HOQUE, MOHAMMAD M | — | §102§103 | Non-Final OA | — | Pending | Sep 22, 2024 |
| 18764890 | SYNCHRONIZATION SIGNAL TRANSMISSION METHOD AND SERIAL COMMUNICATION SYSTEM | BARTELS, CHRISTOPHER A. | 2184 | §103 | Non-Final OA | 22d | Pending | Jul 05, 2024 |
| 18760314 | CAPACITOR | RAMASWAMY, ARUN | 2847 | §102§103 | Final Rejection | 33d | Pending | Jul 01, 2024 |
| 18747608 | ETCHING METHOD FOR SEMICONDUCTOR STRUCTURE COMPRISING SUBSTRATE, FIRST STRUCTURE LOCATED ON PART OF TOP SURFACE OF THE SUBSTRATE, SIDEWALLS STRUCTURE AND FIELD EFFECT TRANSISTOR | ESIABA, NKECHINYERE OTUOMASIRICH | — | §102§103§112 | Non-Final OA | — | Pending | Jun 19, 2024 |
| 18616411 | COMMUNICATION INTERFACE CHIP AND ADDRESS EXTENSION CIRCUIT THEREOF | YU, HENRY W | 2181 | §103 | Non-Final OA | 23d overdue | Pending | Mar 26, 2024 |
| 18141510 | STACKED PACKAGING STRUCTURE AND POWER CONVERTER | BAIG, ANEESA RIAZ | 2814 | §103 | Non-Final OA | 20d | Pending | May 01, 2023 |
| 17886230 | ELECTRODE STRUCTURE, SEMICONDUCTOR STRUCTURE, AND MANUFACTURING METHOD OF ELECTRODE STRUCTURE | NGUYEN, DUY T V | 2818 | §103§112 | Final Rejection | 29d | Pending | Aug 11, 2022 |
| 17743646 | POWER CONVERTER | TRAN, NGUYEN | 2838 | §103 | Final Rejection | 132d overdue | Pending | May 13, 2022 |
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