Prosecution Insights
Last updated: May 29, 2026

Silergy Semiconductor Technology (Hangzhou) Ltd.

11 pending office actions • 9 art units • 11 examiners • 0 of 11 (0%) have an AI response strategy ready • 25 patents granted in the last 365 days

Portfolio Summary

11
Total Pending OAs
3
Non-Final OAs
8
Final Rejections
0
Advisory / Quayle

Response Deadline Pressure

Based on the USPTO statutory response window for each pending office action. 11 of the docket's apps have a known mailing date; the rest are excluded from the tile counts.

3
Overdue
1
Due this week
5
Due this month
2
Due in next 60 days
0
Due later

Deadline Fire Line

Every pending office action with a known statutory deadline, placed on a days-until-due axis. Dots left of Today are overdue; the further right, the more runway. Cases that share a deadline window stack vertically. 11 of the docket's apps have a known mailing date.

-30dToday30d60d90d120d
Overdue (3)Due ≤ 7 days (1)Due ≤ 30 days (5)Due ≤ 60 days (2)

Case Difficulty Mix

Difficulty is derived from the rejection statutes on the most recent pending office action. §101-driven and multi-statute cases are graded Hard; §112-only and obviousness-type double-patenting cases are graded Easy; everything else is Medium. "Unknown" means we have not yet parsed a statute for that office action.

0
Hard (0%)
11
Medium (100%)
0
Easy (0%)
0
Unknown (0%)

Rejection Statute Mix

BucketCases
§103 only11 (100%)

Industry Mix

How the docket's pending cases split across USPTO tech-center bands.

0
Life Sciences
0% of docket
2
Information Tech
18% of docket
0
Communications
0% of docket
9
Semiconductors
82% of docket
0
Mechanical / Eng
0% of docket
0
Business / Other
0% of docket

Time-on-OA Estimate

Manual office-action response work runs about 10 hours per case. The time-saved bands below show what IP Author's prosecution pipeline typically delivers — a conservative 20% on the low end, 35% in the middle, 50% on the high end.

110 h
Manual time on pending OAs
22 h
Time saved (low, 20%)
38 h
Time saved (mid, 35%)
1.0 wks
FTE-weeks freed (mid)

Top Examiners on this docket

ExaminerApps on this docketAllow rateInterview lift
BARTELS, CHRISTOPHER A. 1 67.0% +11.7%
RAMASWAMY, ARUN 1 84.4% +12.6%
YU, HENRY W 1 69.0% +29.1%
MAIGA, SIDI MOHAMED 1 72.2% +16.7%
MICHAUD, NICHOLAS BRIAN 1 73.6% +30.2%
BAIG, ANEESA RIAZ 1 94.1% +7.4%
MALEK, MALIHEH 1 78.9% +3.6%
ESIABA, NKECHINYERE OTUOMASIRICH 1 77.8% +25.0%
NGUYEN, DUY T V 1 78.7% +16.8%
TRAN, NGUYEN 1 83.5% +7.6%

Quick Wins (3)

Cases in front of an examiner with an allow rate of 80%+ where the difficulty is Easy or Medium. The top 3 ordered by deadline are shown.

App #TitleExaminerDue in
17743646 POWER CONVERTER TRAN, NGUYEN 132d overdue
18141510 STACKED PACKAGING STRUCTURE AND POWER CONVERTER BAIG, ANEESA RIAZ 20d
18760314 CAPACITOR RAMASWAMY, ARUN 33d

Interview Candidates (7)

Cases in front of an examiner whose interview lift is 10 percentage points or more — i.e. interviewed cases historically resolve more favorably than non-interviewed ones. The top 7 ordered by deadline are shown.

App #TitleExaminerDue in
18616411 COMMUNICATION INTERFACE CHIP AND ADDRESS EXTENSION CIRCUIT THEREOF YU, HENRY W 23d overdue
18234701 INTEGRATED SUBSTRATE AND POWER INTEGRATED CIRCUIT MAIGA, SIDI MOHAMED 14d
18205090 SEMICONDUCTOR DEVICE STRUCTURE AND MANUFACTURING METHOD THEREOF MICHAUD, NICHOLAS BRIAN 14d
18764890 SYNCHRONIZATION SIGNAL TRANSMISSION METHOD AND SERIAL COMMUNICATION SYSTEM BARTELS, CHRISTOPHER A. 22d
17886230 ELECTRODE STRUCTURE, SEMICONDUCTOR STRUCTURE, AND MANUFACTURING METHOD OF ELECTRODE STRUCTURE NGUYEN, DUY T V 29d
18760314 CAPACITOR RAMASWAMY, ARUN 33d
18118243 SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME ESIABA, NKECHINYERE OTUOMASIRICH 33d

Top Art Units

Art UnitApps
2847 2
2818 2
2184 1
2181 1
2814 1
2813 1
2817 1
2838 1
2891 1

Pending Office Actions

App #TitleExaminerArt UnitStatutesStatusDue inAIFiled
18764890 SYNCHRONIZATION SIGNAL TRANSMISSION METHOD AND SERIAL COMMUNICATION SYSTEM BARTELS, CHRISTOPHER A. 2184 §103 Final Rejection 22d Pending Jul 05, 2024
18760314 CAPACITOR RAMASWAMY, ARUN 2847 §103 Non-Final OA 33d Pending Jul 01, 2024
18616411 COMMUNICATION INTERFACE CHIP AND ADDRESS EXTENSION CIRCUIT THEREOF YU, HENRY W 2181 §103 Final Rejection 23d overdue Pending Mar 26, 2024
18234701 INTEGRATED SUBSTRATE AND POWER INTEGRATED CIRCUIT MAIGA, SIDI MOHAMED 2847 §103 Final Rejection 14d Pending Aug 16, 2023
18205090 SEMICONDUCTOR DEVICE STRUCTURE AND MANUFACTURING METHOD THEREOF MICHAUD, NICHOLAS BRIAN 2818 §103 Final Rejection 14d Pending Jun 02, 2023
18141510 STACKED PACKAGING STRUCTURE AND POWER CONVERTER BAIG, ANEESA RIAZ 2814 §103 Final Rejection 20d Pending May 01, 2023
18131952 SEMICONDUCTOR DEVICE WITH FIELD OXIDE LAYER AND METHOD FOR MANUFACTURING THE SAME MALEK, MALIHEH 2813 §103 Final Rejection 7d Pending Apr 07, 2023
18118243 SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME ESIABA, NKECHINYERE OTUOMASIRICH 2817 §103 Non-Final OA 33d Pending Mar 07, 2023
17886230 ELECTRODE STRUCTURE, SEMICONDUCTOR STRUCTURE, AND MANUFACTURING METHOD OF ELECTRODE STRUCTURE NGUYEN, DUY T V 2818 §103 Non-Final OA 29d Pending Aug 11, 2022
17743646 POWER CONVERTER TRAN, NGUYEN 2838 §103 Final Rejection 132d overdue Pending May 13, 2022
17543948 ESD PROTECTION DEVICE WRIGHT, TUCKER J 2891 §103 Final Rejection 124d overdue Pending Dec 07, 2021

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