DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Election/Restrictions
1. Applicant’s election of Species I, Subspecies I, claims 1-17 in the reply filed on 6/29/2024 is acknowledged. Because applicant did not distinctly and specifically point out the supposed errors in the restriction requirement, the election has been treated as an election without traverse (MPEP § 818.01(a)).
Drawings
2. The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the “second upper conductive pads disposed on top surface of…fourth memory dies” (claim 16) must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Objections
3. The claims are objected because of the following reasons:
Re claim 8, line 1: delete “where” and insert –wherein--.
Appropriate correction is required.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
4. Claims 1-9 and 11-13 are rejected under 35 U.S.C. 103 as being unpatentable over Ko (US 2023/0018676) in view of Kim et al. (US 2023/0045383).
Re claim 1, Ko teaches, under BRI, Fig. 1, [0017, 0032-0041], a semiconductor package comprising:
-a buffer die (100);
-a plurality of memory dies (200A-D) stacked on the buffer die (100);
-a mold layer (vertical 340, 350) covering a portion of a top surface of the buffer die (100) and lateral surfaces of the plurality of memory dies (200A-D); and
-an inorganic layer (360) disposed on the mold layer (350),
wherein the inorganic layer (360) covers at least a portion of the lateral surface of an uppermost memory die (200D) of the plurality of memory dies (200A-D), and
wherein a top surface of the inorganic layer (360) is substantially coplanar with a top surface of the uppermost memory die (200D) of the plurality of memory dies (200A-D).
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Ko does not explicitly teach wherein the inorganic layer includes oxide or nitride.
Kim teaches the inorganic layer (118) includes oxide or nitride [0041-0042].
As taught by Kim, one of ordinary skill in the art would utilize & modify the above teaching to obtain the inorganic layer including oxide or nitride as claimed, because it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended used a matter of obvious design choice. In re Leshin, 125 USPQ 416, and it has been held that that rearranging part of an invention involves only routine skill in the art. In re Japikse, 86 USPQ 70.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Kim in combination Ko due to above reason.
Re claim 2, Ko teaches, Fig. 1, wherein the memory dies include first to fourth memory dies (200A-D) that are sequentially stacked on each other.
Re claim 3, Ko teaches, Fig. 1, wherein the buffer die (100) includes a first through via (130), wherein each of the first to third memory dies (200A-C) includes a second through via (230A, B, C).
Re claim 4, Ko teaches, Fig. 1, internal connection members (250A-D) disposed between the buffer die (100) and the first memory die (200A) and between the first to fourth memory dies (200A-D).
Re claim 5, Ko teaches, Fig. 1, [0036], an underfill layer (300, 310, 320, 330) that fills a space between the buffer die (100) and the first memory die (200A) and spaces between the first to fourth memory dies (200A-D).
Re claim 6, Ko teaches, [0037, 0041], wherein a thermal conductivity of the inorganic layer (360) (e.g., EMI shielding material) is greater than a thermal conductivity of the mold layer (340, 350) (e.g., epoxy).
Re claim 7, Ko teaches, [0037-0041], wherein a stiffness of the inorganic layer (360) (e.g., EMI shielding material) is greater than a stiffness of the mold layer (340, 350) (e.g., epoxy).
Re claim 8, Ko teaches, Fig. 1, where a lateral surface of the inorganic layer (360) is vertically aligned with a lateral surface of the mold layer (340, 350).
Re claim 9, Ko teaches, Fig. 1, wherein the top surface of the uppermost memory die (200D) of the plurality of memory dies (200A-D) is higher than top surface (of 340) of the mold layer (consider 340).
Re claim 11, Ko teaches, Fig. 1, wherein the top surface of the inorganic layer (360) is flat.
Re claim 12, in combination cited above, Kim teaches wherein the inorganic layer (118) includes SiO2 [0041].
Re claim 13, Kim teaches, Fig. 1, [0017], a plurality of external connection members (150) disposed on a lower portion of the buffer die (100).
5. Claims 10 and 14-17 are rejected under 35 U.S.C. 103 as being unpatentable over Ko as modified by Kim as applied to claim 1 above, and further in view of Lin et al. (US 9,640,475).
The teachings of Ko/Kim have been discussed above.
Re claim 10, Ko/Kim does not explicitly teach wherein a thickness of the inorganic layer is in a range of about 2 um to about 10 um.
Lin teaches “the insulating layer has a first thickness that is substantially 10 to 16 μm” (claim 6).
As taught by Lin, one of ordinary skill in the art would utilize & modify the above teaching to obtain a thickness of the inorganic layer is in a range of about 2 um to about 10 um as claimed, because thickness is known to affect device properties and would depend on the desired device density and the desired device characteristics. One of ordinary skill in the art would have been led to the recited thickness through routine experimentation to achieve desired characteristics of the formed device.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Lin in combination Ko/Kim due to above reason.
Re claim 14, Ko teaches, under BRI, Fig. 1, [0017, 0032-0041], a semiconductor package comprising:
-a buffer die (100);
-a plurality of memory dies (200A-D) stacked on the buffer die (100);
-a mold layer (340, 350) that covers a portion of a top surface of the buffer die (100) and lateral surfaces of the plurality of memory dies (200A-D); and
-an inorganic layer (360) disposed on the mold layer (340, 350),
wherein the buffer die (100) includes:
a first through via (130); and
a plurality of external connection members (150) disposed on a lower portion of the buffer die (100),
wherein the memory dies (200A-D) include first to fourth memory dies that are sequentially stacked on the buffer die (100),
wherein each of the first to third memory dies (200A-C) includes a second through via (230A-C),
wherein the inorganic layer (360) covers at least a portion of the lateral surface of the fourth memory die (200D) (from side view),
wherein a top surface of the inorganic layer (360) and a top surface of the fourth memory die (200D) are substantially coplanar with each other,
wherein a thermal conductivity of the inorganic layer (360) (e.g., EMI shielding material) is greater than a thermal conductivity of the mold layer (340, 350) (e.g., epoxy),
wherein a stiffness of the inorganic layer (360) is greater than a stiffness of the mold layer (340, 350),
wherein a lateral surface of the inorganic layer (360) and a lateral surface of the mold layer (340, 350) are vertically aligned with each other.
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Ko does not explicitly teach wherein the inorganic layer includes SiO2.
Kim teaches the inorganic layer (118) includes SiO2 [0041-0042].
As taught by Kim, one of ordinary skill in the art would utilize & modify the above teaching to obtain the inorganic layer including SiO2 as claimed, because it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended used a matter of obvious design choice. In re Leshin, 125 USPQ 416, and it has been held that that rearranging part of an invention involves only routine skill in the art. In re Japikse, 86 USPQ 70.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Kim in combination Ko due to above reason.
Ko/Kim does not explicitly teach wherein a thickness of the inorganic layer is in a range of about 2 um to about 10 um.
Lin teaches “the insulating layer has a first thickness that is substantially 10 to 16 μm” (claim 6).
As taught by Lin, one of ordinary skill in the art would utilize & modify the above teaching to obtain a thickness of the inorganic layer is in a range of about 2 um to about 10 um as claimed, because thickness is known to affect device properties and would depend on the desired device density and the desired device characteristics. One of ordinary skill in the art would have been led to the recited thickness through routine experimentation to achieve desired characteristics of the formed device.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Lin in combination Ko/Kim due to above reason.
Re claim 15, Ko teaches, Fig. 1, [0023, 0042], a plurality of internal connection members (bumps 250A-D) disposed between the buffer die (100) and the first memory die (200A) and between the first to fourth memory dies (200A-D); and an underfill layer (300, 310, 320, 330) that fills a space between the buffer die (100) and the first memory die (200A) and spaces between the first to fourth memory dies (200A-D).
Re claim 16, Ko teaches, Fig. 1 & based on plurality chips, abstract, claim 1, [0019, 0023], wherein the buffer die (100) further includes:
a plurality of first upper conductive pads (160) disposed on the top surface of the buffer die (100); and
a plurality of first lower conductive pads (on which 150 disposed on) disposed on a bottom surface of the buffer die (100),
wherein each of the first to fourth memory dies (e.g., based on plurality of chips) includes:
a plurality of second upper conductive pads (260) disposed on a top surface of the each of the first to fourth memory dies; and
a plurality of second lower conductive pads (240) disposed on a bottom surface of the each of the first to fourth memory dies,
wherein the first upper conductive pads (160) are correspondingly in contact with the second lower conductive pads (240) of the first memory die (200A),
wherein the first upper conductive pads (160) are formed of a material that is the same as a material of the second lower conductive pads (240) of the first memory die (200A) (e.g. copper),
wherein the second upper conductive pads (260) and the second lower conductive pads (240) are correspondingly in contact with each other between the first to fourth memory dies, and
wherein the second upper conductive pads (260) are formed of a material that is the same as a material of the second lower conductive pads (240) (e.g. copper).
Re claim 17, Ko teaches, Fig. 1, wherein the top surface of the inorganic layer (360) is flat.
Conclusion
6. Any inquiry concerning this communication or earlier communications from the examiner should be directed to DUY T.V. NGUYEN whose telephone number is (571)270-7431. The examiner can normally be reached Monday-Friday, 7AM-4PM, alternative Friday off.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, EVA MONTALVO can be reached at (571) 270-3829. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/DUY T NGUYEN/Primary Examiner, Art Unit 2818 7/14/26
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