DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed. For example, a more descriptive title could be, “Semiconductor Device With Inspection Wiring Surrounding an Element Region”.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-3, 8-11 and 17-20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Matoba et al. (JP 2009-239027; hereinafter, “Matoba”, which is a prior art of record listed on the IDS filed 03/26/2024).
Regarding claims 1-3, 8-11 and 17-20:
re claim 1, Matoba discloses a semiconductor device comprising:
a semiconductor chip 2 (Fig. 1) that has a first principal surface (upper surface of 15 in Fig. 3) in which an element region (region surrounded by 3 in Fig. 1) is formed and a peripheral end surface (peripheral ends/edges of chip 2 in Fig. 1) surrounding the first principal surface; and
an inspection wiring 3/8/10/13/17 (Figs. 1 and 3) that is formed along the peripheral end surface on a side of the first principal surface of the semiconductor chip and that surrounds the element region (Fig. 1),
wherein the inspection wiring includes a plurality of internal wiring portions 13 (Fig. 3(b)) that are formed at a surficial portion of the first principal surface (upper surface of 16a in Fig. 3) of the semiconductor chip and that are arrayed at a distance from each other along the peripheral end surface of the semiconductor chip 2 and an (Note: ‘a” should read “an”) extending wiring portion 3/8 (Fig. 3) that is formed on the first principal surface of the semiconductor chip and that is provided between the internal wiring portions 13 adjoining each other (Fig. 2), and wherein the internal wiring portions 13 (Note: “portion” should read “portions” for proper antecedent basis) and the extending wiring portion 3/8 are alternately arrayed along the peripheral end surface (e.g., In Figs. 1, 2 and 3, the inspection wiring comprises portions “10” that are alternately arrayed with extending portion 3/8 along the peripheral end surface, wherein portion “10” are at the same location as wiring portions 13);
re claim 2, the semiconductor device according to claim 1, further comprising an insulating layer 16a/16b/18 (Fig. 3(b)) formed at the first principle (Note: “main” must read “principle”, otherwise there would be a lack of antecedent basis) surface (upper surface of 15 in Fig. 3) of the semiconductor chip, wherein the extending wiring portion 3/8 includes a wiring layer 3/8 (Fig. 3, i.e., wiring portion 3/8 is a wiring layer) that is embedded in the insulating layer at a distance from the first principal surface in a thickness direction of the semiconductor chip and that extends along the first principal surface (Figs. 1-2) and a connection via 10b (Fig. 3(b)) that extends from the wiring layer 3/8 in the thickness direction of the semiconductor chip and that electrically connects the wiring layer 3/8 and the internal wiring portion 13 (Fig. 3(b));
re claim 3, the semiconductor device according to claim 2, wherein the insulating layer 16a/16b/18 (Fig. 3) has a laminated structure including a first insulating layer 16a and a second insulating layer 16b placed on the first insulating layer, and the wiring layer includes a plurality of first wiring layers 3 (Fig. 3(a)) that are formed on [a bottom side of] the first insulating layer 16a and that are separated from each other and a second wiring layer 8 (Fig. 3(a)) that is formed on the second insulating layer 16b and that straddles the first wiring layers 3, and the connection via includes a first connection via 10a (Fig. 3(b)) that connects the first wiring layer 3 and the internal wiring portion 13 and a second connection via 10b that connects the second wiring layer 8 and the first wiring layer 3 (i.e., “connects” does not require “directly connects”);
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re claim 8, the semiconductor device according to claim 3, wherein the first connection via 10a (see “first via connection” in Exhibit A above) is disposed at a first position (see “first portion” in Exhibit A) in a direction along the peripheral end surface, and the second connection (see “second via connection” in Exhibit A) via is disposed at a second position (see “second portion” in Exhibit A) differing from the first position in the direction along the peripheral end surface.
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re claim 9, the semiconductor device according to claim 3, wherein the internal wiring portion has a total length (see “a total length of internal wiring portion” in Exhibit B above) of not less than 50% and not more than 75% with respect to a length along a circumferential direction (see “a length along circumference” in Exhibit B) of the peripheral end surface.
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re claim 10, the semiconductor device according to claim 3, wherein the first wiring layer has a total length (see “a total length of first wiring layer” in Exhibit C above) of not less than 50% and not more than 75% with respect to the length along the circumferential direction (see “a length along circumference” in Exhibit C) of the peripheral end surface.
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re claim 11, the semiconductor device according to claim 3, wherein the second wiring layer has a total length (see “a total length of second wiring layer” in Exhibit D above) of not less than 50% and not more than 75% with respect to the length along the circumferential direction (see “a length along circumference” in Exhibit C) of the peripheral end surface.
re claim 17, the semiconductor device according to claim 1, further comprising a second inspection wiring (i.e., in Fig. 7 and [0056] of the English translation there are two wirings 3a and 3b) that is formed along the peripheral end surface on the first principal surface of the semiconductor chip, that includes an annular wiring layer surrounding the element region, and that is physically and electrically away from the inspection wiring (i.e., the two annular wirings 3a, 3b are physically and electrically away from each other, Fig. 7);
re claim 18, the semiconductor device according to claim 17, wherein the second inspection wiring (e.g., 3b in Fig. 7) is formed between the inspection wiring (e.g., 3a in Fig. 7) and the peripheral end surface (e.g., edge of 2a in Fig. 7), and surrounds the inspection wiring;
re claim 19, the semiconductor device according to claim 17, wherein the inspection wiring (e.g., 3b in Fig. 7) is formed between the second inspection wiring (e.g., 3a in Fig. 7) and the peripheral end surface (e.g., edge of 2a in Fig. 7), and surrounds the second inspection wiring; and
re claim 20, the semiconductor device according to claim 1 further comprising: a pad terminal 5 (Fig. 1 and [0039] of the English translation) formed on the first principal surface of the semiconductor chip 2; and a circuit wiring (e.g., wiring that connects “5” to “7” to “3” in Fig. 1) that electrically connects the pad terminal 5 and the inspection wiring 3.
Allowable Subject Matter
Claims 4-7 and 12-16 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Claims 4-5 are allowed because the prior art of record cannot anticipate or render obvious the limitations in claim 4 (when combined with claims 1-3), and claim 5 depends from claim 4;
Claims 6-7 are allowed because the prior art of record cannot anticipate or render obvious the limitations in claim 6 (when combined with claims 1-3), and claim 7 depends from claim 6;
Claims 12-14 are allowed because the prior art of record cannot anticipate or render obvious the limitations in claim 12 (when combined with claim 1), and claims 13-14 depend from claim 12; and
Claims 15-16 are allowed because the prior art of record cannot anticipate or render obvious the limitations in claim 15 (when combined with claim 1), and claim 16 depends from claim 15.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to LEX H MALSAWMA whose telephone number is (571)272-1903. The examiner can normally be reached M-F (4-12 Hours, between 5:30AM-10PM).
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/LEX H MALSAWMA/Primary Examiner, Art Unit 2892
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