Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Status of the Claims
Applicant’s election, without traverse, of Group I, claims 1-15 in the reply filed on June 22nd, 2026, is acknowledged. Non-elected invention of Group II, claims 16-20 have been withdrawn from consideration. Claims 1-20 are pending.
Action on merits of Group I, claims 1-15 as follows.
Information Disclosure Statement
The information disclosure statements (IDSs) submitted on March 26th, 2024, May 17th, 2024, September 05th, 2025, January 22nd, 2026 and June 02nd, 2026, have been considered by the examiner.
Drawings
The drawings filed on 03/26/2024 are acceptable.
Specification
The specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant's cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claims 1-13 are rejected under 35 U.S.C. 103 as being unpatentable over Toyama (US 2017/0179026, hereinafter as Toya ‘026) in view of Kang (US 2017/0358590, hereinafter as Kang ‘590) and further in view of Kato (US 2021/0159239, hereinafter as Kato ‘239).
Regarding Claim 1, Toya ‘026 teaches a memory device, comprising:
an alternating stack of insulating layers (Fig. 17C, (132); [0222]) and electrically conductive layers (Fig. 17C, (146); [0228]) located over a substrate (9, [0163]);
memory openings (49; [0184]) vertically extending through the alternating stack;
memory opening fill structures (55; [0203]) located in the memory openings, wherein each of the memory opening fill structures comprises a respective vertical semiconductor channel (60; [0203]) and a vertical stack of memory elements (50; [0203]).
Thus, Toya ‘026 is shown to teach all the features of the claim with the exception of explicitly the limitations: “a contact via structure contacting a reference electrically conductive layer that is one of the electrically conductive layers; and at least one silicon oxide liner laterally surrounding a cylindrical portion of the contact via structure and contacting a laterally protruding portion of the contact via structure.
Kang ‘590 teaches a contact via structure (MCT; [00356]) contacting a reference electrically conductive layer that is one of the electrically conductive layers (220; [0035]); and at least one silicon oxide liner (324; [0055]) laterally surrounding a cylindrical portion of the contact via structure.
Thus, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify Toya ‘026 by having a contact via structure contacting a reference electrically conductive layer that is one of the electrically conductive layers; and at least one silicon oxide liner laterally surrounding a cylindrical portion of the contact via structure for the purpose of improving integration and excellent electrical characteristics (see para. [0003]) as suggested by Kang ‘590.
Thus, Toya ‘026 and Kang ‘590 are shown to teach all the features of the claim with the exception of explicitly the limitations: “at least one silicon oxide liner contacting a laterally protruding portion of the contact via structure”.
Kato ‘239 teaches at least one silicon oxide liner (Fig. 5, (28); [0122]) contacting a laterally protruding portion of the contact via structure (CC; [0086]).
Thus, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify Toya ‘026 and Kang ‘590 by having at least one silicon oxide liner contacting a laterally protruding portion of the contact via structure in order to provide a semiconductor storage device capable of improving operation reliability (see para. [0041]) as suggested by Kato ‘239.
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Fig. 17C (Toya ‘026)
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Fig. 2N (Kang ‘590)
Regarding Claim 2, Kang ‘590 teaches the cylindrical portion of the contact via structure (MCT) has a top surface located above a horizontal plane including a topmost surface of the alternating stack (220/140) and a bottom surface located at or below a horizontal plane including a bottommost surface of the alternating stack (220/140); and the laterally protruding portion of the contact via structure comprises a flange portion having an annular top surface, an annular bottom surface, and a vertical cylindrical surface that contacts a vertical cylindrical sidewall of the reference electrically conductive layer (see Fig. 2N).
Regarding Claim 3, Kang ‘590 teaches a vertical stack of annular insulating fins laterally surrounding the cylindrical portion of the contact via structure and underlying the flange portion (see Fig. 12).
Regarding Claim 4, Kato ‘239 teaches the vertical stack of annular insulating fins (23; [0080]) is located at levels of a subset of the electrically conductive layers (25; [0080]) that underlies the reference electrically conductive layer (see Fig. 5).
Regarding Claim 5, Kato ‘239 teaches the at least one silicon oxide liner comprises a first silicon oxide liner; and the first silicon oxide liner comprises a first cylindrical silicon oxide portion interposed between the contact via structure (CC) and the vertical stack of annular insulating fins (23) (see Fig. 5).
Regarding Claim 6, Kato ‘239 teaches a first annular silicon oxide plate portion contacting the annular bottom surface of the flange portion of the contact via structure (CC) (see Fig. 5).
Regarding Claim 7, Kato ‘239 teaches the outer cylindrical sidewalls of the vertical stack of annular insulating fins (23).
Toya ‘026, Kang ‘590 and Kato ‘239 are shown to teach all the features of the claim with the exception of explicitly the limitations: “are located within a vertically-extending cylindrical plane including an outer cylindrical sidewall of the first annular silicon oxide plate portion”.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have the outer cylindrical sidewalls of the vertical stack of annular insulating fins that can be arranged in any order, thus the outer cylindrical sidewalls of the vertical stack of annular insulating fins are located within a vertically-extending cylindrical plane including an outer cylindrical sidewall of the first annular silicon oxide plate portion involves only routine skill in the art. In re Einstein, 8 USPQ 167. A person of ordinary skills in the art is motivated to have the outer cylindrical sidewalls of the vertical stack of annular insulating fins are located within a vertically-extending cylindrical plane including an outer cylindrical sidewall of the first annular silicon oxide plate portion when this improves the performance of the memory device.
Regarding Claim 8, Kato ‘239 teaches a bottom plate portion adjoined to a bottom periphery of the first cylindrical silicon oxide portion and located underneath a horizontal plane including a bottom surface of a bottommost electrically conductive layer within the alternating stack (see Fig. 6).
Regarding Claim 9, Kang ‘590 teaches a substrate dielectric liner (194; [0033] and [0099]) comprising an oxide of a semiconductor material in the substrate (e.g. a silicon oxynitride layer; [0033]) and contacting a bottom surface of the bottom plate portion (see Fig. 7L).
Regarding Claim 10, Kato ‘239 teaches a dielectric material portion (27; [0081]) overlying the flange portion of the contact via structure and laterally surrounding the cylindrical portion of the contact via structure, wherein a top surface of the dielectric material portion is located below a horizontal plane including the top surface of the contact via structure (see Fig. 32).
Regarding Claim 11, Kato ‘239 teaches a second silicon oxide liner (32; [0085]) interposed between the contact via structure (CC) and the dielectric material portion (27) and having a same material composition and a same thickness as the first silicon oxide liner (see Fig. 32).
Further, it has been held to be within the general skill of a worker in the art to select a material of the second silicon oxide liner is a same material composition and a same thickness as the first silicon oxide liner on the basis of it suitability for the intended use as a matter of obvious design choice. In re Leshin, 125 USPQ 416. A person of ordinary skills in the art is motivated to select a material of the second silicon oxide liner is a same material composition and a same thickness as the first silicon oxide liner when this improves the performance of the memory device.
Regarding Claim 12, Kato ‘239 teaches a second cylindrical silicon oxide portion (32) laterally surrounding and contacting a segment of a cylindrical portion of the contact via structure (CC) that overlies the flange portion; and an annular silicon oxide plate portion that contacts the annular top surface of the flange portion of the contact via structure (see Fig. 32).
Regarding Claim 13, Kato ‘239 teaches the second silicon oxide liner (32) is disjoined from the first silicon oxide liner (see Fig. 32); and a vertical distance between the second silicon oxide liner and the first silicon oxide liner equals a thickness of the flange portion of the contact via structure (CC) (see Fig. 32).
Claims 14-15 are rejected under 35 U.S.C. 103 as being unpatentable over Toya ‘026, Kang ‘590 and Kato ‘239 as applied to claim 2 above, and further in view of Baraskar (US 2020/0258896, hereinafter as Bara ‘896).
Regarding Claim 14, Kato ‘239 teaches the flange portion (CC) has a first thickness; and the reference electrically conductive layer (25) has a second thickness that is greater than the first thickness (see Fig. 32).
Toya ‘026, Kang ‘590 and Kato ‘239 are shown to teach all the features of the claim with the exception of explicitly the limitations: “the reference electrically conductive layer is embedded within a backside blocking dielectric layer;”.
Bara ‘896 teaches the reference electrically conductive layer (Fig. 11A, (46); [0103]) is embedded within a backside blocking dielectric layer (44; [0098]).
Thus, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify Toya ‘026, Kang ‘590 and Kato ‘239 by having the reference electrically conductive layer is embedded within a backside blocking dielectric layer in order to function as a control gate dielectric for the control gates to be subsequently formed in the backside recesses (see para. [0093]) as suggested by Bara ‘896.
Regarding Claim 15, Bara ‘896 teaches the reference electrically conductive layer (Fig. 11A, (46); [0103]) is embedded within a backside blocking dielectric layer (44; [0098]).
Kato ‘239 teaches the flange portion (CC) has a first thickness; and the reference electrically conductive layer (25) comprises a distal portion that is distal from the flange portion and has a second thickness that is greater than the first thickness, and further comprises a proximal portion that contacts the flange portion and has a third thickness.
Toya ‘026, Kang ‘590 and Kato ‘239 are shown to teach all the features of the claim with the exception of explicitly the limitations: “a third thickness that is less than the first thickness”.
However, it has been held to be within the general skill of a worker in the art to select a third thickness that is less than the first thickness on the basis of it suitability for the intended use as a matter of obvious design choice. In re Leshin, 125 USPQ 416. In Gardner v. TEC Systems, Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984), the Federal Circuit held that, where the only difference between the prior art and the claims was a recitation of relative dimensions of the claimed device and a device having the claimed relative dimensions would not perform differently than the prior art device, the claimed device was not patentably distinct from the prior art device.
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A person of ordinary skills in the art is motivated to select a third thickness that is less than the first thickness when this improves the performance of the memory device.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. The following patents are cited to further show the state of the art with respect to semiconductor devices:
Matovu et al. (US 10,269,625 B1)
Oshiki et al. (US 2018/0197874 A1)
Cui (US 9,853,038 B1)
For applicant’s benefit portions of the cited reference(s) have been cited to aid in the review of the rejection(s). While every attempt has been made to be thorough and consistent within the rejection it is noted that the PRIOR ART MUST BE CONSIDERED IN ITS ENTIRETY, INCLUDING DISCLOSURES THAT TEACH AWAY FROM THE CLAIMS. See MPEP 2141.02 VI.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DZUNG T TRAN whose telephone number is (571) 270-3911. The examiner can normally be reached on M-F 8 AM-5PM.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Sue Purvis can be reached on (571) 272-1236. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/DZUNG TRAN/
Primary Examiner, Art Unit 2893
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