Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Acknowledgment is made of applicant’s claim for domestic priority based on provisional application 63/456,093 filed on March 31st, 2023.
Information Disclosure Statement
The information disclosure statements (IDS) were submitted on 12/13/2024, 10/22/2025, and 7/15/2026. This submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statements are being considered by the examiner.
Specification
The disclosure is objected to because of the following informalities:
In paragraph 0009, line 8, “Tayer” should read “The layer”.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 2-4, 6-7, 11-14, 16, and 19-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 2 recites the term “about” which is a relative term and renders the claim indefinite. See MPEP 2173.05(b)(I). The term “about” is not defined by the claim, the specification does not provide a standard for ascertaining the requisite degree, and one of ordinary skill in the art would not be reasonably apprised of the scope of the invention. The term “about” encompasses a variety of different temperature values and is not a quantifiable term that is agreed upon. For examination purposes, the term “about” of claim 2 will be interpreted broadly to encompass prior art disclosing temperature(s) reasonably close to the claimed temperature.
Claim 3 recites the term “about” which is a relative term and renders the claim indefinite. See MPEP 2173.05(b)(I). The term “about” is not defined by the claim, the specification does not provide a standard for ascertaining the requisite degree, and one of ordinary skill in the art would not be reasonably apprised of the scope of the invention. The term “about” encompasses a variety of different temperature values and is not a quantifiable term that is agreed upon. For examination purposes, the term “about” of claim 3 will be interpreted broadly to encompass art disclosing temperature(s) reasonably close to the claimed temperature.
Claim 4 is rejected as being dependent on, and failing to cure the deficiencies of, rejected claim 3.
Claim 6 recites the term “about” which is a relative term and renders the claim indefinite. See MPEP 2173.05(b)(I). The term “about” is not defined by the claim, the specification does not provide a standard for ascertaining the requisite degree, and one of ordinary skill in the art would not be reasonably apprised of the scope of the invention. The term “about” encompasses a variety of different roughness values and is not a quantifiable term that is agreed upon. For examination purposes, the term “about” of claim 6 will be interpreted broadly to encompass art disclosing roughness(es) reasonably close to the claimed roughness.
Claim 7 recites the term “about” which is a relative term and renders the claim indefinite. See MPEP 2173.05(b)(I). The term “about” is not defined by the claim, the specification does not provide a standard for ascertaining the requisite degree, and one of ordinary skill in the art would not be reasonably apprised of the scope of the invention. The term “about” encompasses a variety of different roughness values and is not a quantifiable term that is agreed upon. For examination purposes, the term “about” of claim 7 will be interpreted broadly to encompass art disclosing roughness(es) reasonably close to the claimed roughness.
Claim 11 recites the term “about” which is a relative term and renders the claim indefinite. See MPEP 2173.05(b)(I). The term “about” is not defined by the claim, the specification does not provide a standard for ascertaining the requisite degree, and one of ordinary skill in the art would not be reasonably apprised of the scope of the invention. The term “about” encompasses a variety of different thickness values and is not a quantifiable term that is agreed upon. For examination purposes, the term “about” of claim 11 will be interpreted broadly to encompass art disclosing thickness(es) reasonably close to the claimed thickness.
Claim 12 recites the term “about” which is a relative term and renders the claim indefinite. See MPEP 2173.05(b)(I). The term “about” is not defined by the claim, the specification does not provide a standard for ascertaining the requisite degree, and one of ordinary skill in the art would not be reasonably apprised of the scope of the invention. The term “about” encompasses a variety of different temperature values and is not a quantifiable term that is agreed upon. For examination purposes, the term “about” of claim 12 will be interpreted broadly to encompass art disclosing temperature(s) reasonably close to the claimed temperature.
Claim 13 recites the term “about” which is a relative term and renders the claim indefinite. See MPEP 2173.05(b)(I). The term “about” is not defined by the claim, the specification does not provide a standard for ascertaining the requisite degree, and one of ordinary skill in the art would not be reasonably apprised of the scope of the invention. The term “about” encompasses a variety of different temperature values and is not a quantifiable term that is agreed upon. For examination purposes, the term “about” of claim 13 will be interpreted broadly to encompass art disclosing temperature(s) reasonably close to the claimed temperature.
Claim 14 recites the term “about” which is a relative term and renders the claim indefinite. See MPEP 2173.05(b)(I). The term “about” is not defined by the claim, the specification does not provide a standard for ascertaining the requisite degree, and one of ordinary skill in the art would not be reasonably apprised of the scope of the invention. The term “about” encompasses a variety of different temperature values and is not a quantifiable term that is agreed upon. For examination purposes, the term “about” of claim 14 will be interpreted broadly to encompass art disclosing temperature(s) reasonably close to the claimed temperature.
Claim 16 recites the term “about” which is a relative term and renders the claim indefinite. See MPEP 2173.05(b)(I). The term “about” is not defined by the claim, the specification does not provide a standard for ascertaining the requisite degree, and one of ordinary skill in the art would not be reasonably apprised of the scope of the invention. The term “about” encompasses a variety of different roughness values and is not a quantifiable term that is agreed upon. For examination purposes, the term “about” of claim 16 will be interpreted broadly to encompass art disclosing roughness(es) reasonably close to the claimed roughness.
Claim 19 recites the term “about” which is a relative term and renders the claim indefinite. See MPEP 2173.05(b)(I). The term “about” is not defined by the claim, the specification does not provide a standard for ascertaining the requisite degree, and one of ordinary skill in the art would not be reasonably apprised of the scope of the invention. The term “about” encompasses a variety of different temperature values and is not a quantifiable term that is agreed upon. For examination purposes, the term “about” of claim 19 will be interpreted broadly to encompass art disclosing temperature(s) reasonably close to the claimed temperature.
Claim 20 recites the term “about” which is a relative term and renders the claim indefinite. See MPEP 2173.05(b)(I). The term “about” is not defined by the claim, the specification does not provide a standard for ascertaining the requisite degree, and one of ordinary skill in the art would not be reasonably apprised of the scope of the invention. The term “about” encompasses a variety of different roughness values and is not a quantifiable term that is agreed upon. For examination purposes, the term “about” of claim 20 will be interpreted broadly to encompass art disclosing roughness(es) reasonably close to the claimed roughness.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1 is rejected under 35 U.S.C. 102(a)(1) as being anticipated by Wang et al, US 20210005455 A1 (Wang).
Regarding claim 1; Wang teaches a semiconductor processing method (Fig. 1A: fabrication sequence 100) comprising:
forming a layer of silicon nitride on a semiconductor substrate (Fig. 1A: dielectric material 105 disposed on substrate 103),
wherein the layer of silicon nitride is characterized by a first roughness (a first roughness is implied by reducing the roughness);
performing a post-deposition treatment on the layer of silicon nitride (Fig. 1A; Para. 31: "The atoms 113 may be preferentially implanted to an intended (e.g., selected) depth and/or an intended density"; Para. 34: "The atoms 113 shown and described as being implanted at point 101-5 are illustrated at point 101-6 as having an increased density (represented by increased stippling) in the hard mask material 106 portions of the pillars 115 than the densities of the atoms implanted into the lower RI material 109 and dielectric material 105 portions.");
and reducing a roughness of the layer of silicon nitride such that the layer of silicon nitride is characterized by a second roughness less than the first roughness (Para. 29: "As described herein, the atoms may be implanted to reduce a probability of the unintended bend of, or roughness on, the pillar").
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Rejection note: italicized claim limitation indicate claim limitations that are not explicitly disclosed by the primary reference but are disclosed by the secondary reference(s).
Claims 6 and 7 are rejected under 35 U.S.C. 103 as being unpatentable over Wang et al, US 20210005455 A1 (Wang) in view of Haverkamp et al, US 20110236594 A1 (Haverkamp).
Regarding claim 6; as best understood based on the 35 U.S.C. 112(b) issue identified above, Wang teaches all the limitations of the semiconductor processing method of claim 1.
Wang fails to teach specific values for “the first roughness”. Thus, Wang fails to teach the claimed roughness configuration “wherein the first roughness is greater than or about 0.50 nm”.
However, Haverkamp teaches wherein the first roughness is greater than or about 0.50 nm (Para. 55: “For reference, the roughness of a 1000 .ANG. silicon nitride film deposited on a bare silicon substrate is 5.1 .ANG. Ra.”). This roughness reasonably corresponds with the first roughness of Wang because it is a characteristic measured in the same way, (i.e., before “performing a post-deposition treatment on the layer of silicon nitride”).
Wang and Haverkamp are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify Wang by having the first roughness greater than or about 0.50 nm as disclosed in Haverkamp due to the nature of forming a layer of silicon nitride. Furthermore, according to MPEP § 2144.05 (II-A), differences in dimensions will not support the patentability of subject matter encompassed by the prior art unless there is evidence indicating such dimension is critical. “[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955)”.
Regarding claim 7; as best understood based on the 35 U.S.C. 112(b) issue identified above, Wang teaches all the limitations of the semiconductor processing method of claim 1.
Wang fails to teach specific values for “the second roughness”. Thus, Wang fails to teach the claimed roughness configuration “wherein the second roughness is less than or about 0.30 nm”.
Haverkamp teaches the first roughness is 5.1 angstroms (Para. 55: “For reference, the roughness of a 1000 .ANG. silicon nitride film deposited on a bare silicon substrate is 5.1 .ANG. Ra.”), and this roughness reasonably corresponds to the first roughness of Wang because it is a characteristic measured in the same way, (i.e., before “performing a post-deposition treatment on the layer of silicon nitride”). Accordingly, the second roughness (of Wang) must necessarily be less than the first roughness (of Haverkamp) because this first roughness is still subject to the same technique as before (i.e., the “post-deposition treatment” of Wang, cited in the claim 1 rejection). This resultant “second roughness” would therefore be less than 5.1 angstroms; and this roughness is reasonably close to the claimed configuration “wherein the second roughness is less than or about 0.30 nm” because it includes values within the same order of magnitude. According to MPEP § 2144.05 (I), “a prima facie case of obviousness exists where the claimed ranges or amounts do not overlap with the prior art but are merely close. Titanium Metals Corp. of America v. Banner, 778 F.2d 775, 783, 227 USPQ 773, 779 (Fed. Cir. 1985).” Therefore, it would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify Wang to have a second roughness less than or about 0.30 nm as disclosed in Haverkamp in order to improve performance.
Claims 2-5, 8-10, 14-18, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Wang et al, US 20210005455 A1 (Wang), in view of Raley et al, US 20220037152 A1 (Raley).
Regarding claim 2; as best understood based on the 35 U.S.C. 112(b) issue identified above, Wang teaches all the limitations of the semiconductor processing method of claim 1.
Wang fails to teach wherein the semiconductor substrate is maintained at a temperature below or about 550 °C during the semiconductor processing method.
However, Raley teaches wherein the semiconductor substrate is maintained at a temperature below or about 550 °C during the semiconductor processing method step of claim 1 “of performing a post-deposition treatment on the layer of silicon nitride” (Fig. 6: 620; Para. 31: "In one exemplary embodiment, the hydrogen (H.sub.2) plasma may be performed with process conditions of 0 W to 500 W source power, 20 W to 200 W bias power, 5 mT to 50 mT pressure, '110° C. to 100° C. (and more preferably 40° C.) electrostatic chuck temperature,").
Wang and Raley are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify Wang to have the semiconductor substrate is maintained at a temperature below or about 550 °C during the semiconductor processing method in order to control damage. Furthermore, according to MPEP § 2144.05 (II-A), differences in temperature will not support the patentability of subject matter encompassed by the prior art unless there is evidence indicating such dimension is critical. “[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955)”.
Regarding claim 3; as best understood based on the 35 U.S.C. 112(b) issue identified above, Wang teaches all the limitations of the semiconductor processing method of claim 1, wherein: the post-deposition treatment comprises an ion implantation process (Fig. 1A: Para. 31: "The atoms 113 may be preferentially implanted to an intended (e.g., selected) depth and/or an intended density"; Para. 34: "The atoms 113 shown and described as being implanted at point 101-5 are illustrated at point 101-6 as having an increased density (represented by increased stippling) in the hard mask material 106 portions of the pillars 115 than the densities of the atoms implanted into the lower RI material 109 and dielectric material 105 portions.").
Wang fails to teach wherein the ion implantation process is performed at a temperature of greater than or about -100 °C.
However, Raley teaches the ion implantation process is performed at a temperature of greater than or about -100 °C. (Fig. 6: 620; Para. 31: "In one exemplary embodiment, the hydrogen (H.sub.2) plasma may be performed with process conditions of 0 W to 500 W source power, 20 W to 200 W bias power, 5 mT to 50 mT pressure, '110° C. to 100° C. (and more preferably 40° C.) electrostatic chuck temperature,").
It would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify Wang by having the ion implantation process to be performed at a temperature greater than or about -100 °C to control damage. Furthermore, according to MPEP § 2144.05 (II-A), differences in temperature will not support the patentability of subject matter encompassed by the prior art unless there is evidence indicating such dimension is critical. “[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955)”.
Regarding claim 4; as best understood based on the 35 U.S.C. 112(b) issue identified above, Wang in view of Raley teaches all the limitations the semiconductor processing method of claim 3.
Further, Wang teaches wherein the ion implantation process is performed with helium, neon, argon, silicon, boron, carbon, nitrogen, or germanium ions. (Wang: Fig. 3: 333 carbon; Fig. 4: 438 argon).
Regarding claim 5; Wang teaches all the limitations the semiconductor processing method of claim 1.
Wang fails to teach wherein the post-deposition treatment comprises a beamline ion implantation process or a plasma doping process.
However, Raley teaches wherein the post-deposition treatment comprises a beamline ion implantation process or a plasma doping process. (Fig. 6: 620; Para. 31: "The ion implantation modification step may also be achieved by using ion beam implantation or gas cluster ion beam implantation.").
It would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify Wang by having the post-deposition treatment comprise a beamline ion implantation process or a plasma doping process for dose control and uniformity.
Regarding claim 8; Wang teaches a semiconductor processing method (Fig. 1A: fabrication sequence 100) comprising:
forming a layer of silicon nitride on a semiconductor substrate (Fig. 1A: dielectric material 105 disposed on substrate 103),
wherein the layer of silicon nitride is characterized by a first roughness (a first roughness is implied by reducing the roughness);
transferring the semiconductor substrate to a beamline ion implantation chamber or plasma doping chamber (Para. 64: "The processing apparatus 551 may include a chamber 552 to enclose components configured to perform wet or dry deposition or etch operations, possibly in addition to other operations (e.g., by having a source for atom implantation operations)… The system 550 may include a number of chambers 552 that are each configured to perform particular processes (e.g., a wet etch process, a dry etch process, a wet deposition process, a dry deposition process, a wet clean process, a dry clean process, an atom implantation process, among others) during the fabrication sequence.");
performing a beamline ion implantation process or a plasma doping process on the layer of silicon nitride;
and reducing a surface roughness of the layer of silicon nitride to a second roughness less than the first roughness. (Para. 29: "As described herein, the atoms may be implanted to reduce a probability of the unintended bend of, or roughness on, the pillar").
Wang fails to teach performing a beamline ion implantation process or a plasma doping process on the layer of silicon nitride.
However, Raley teaches performing a beamline ion implantation process or a plasma doping process on the layer of silicon nitride; (Fig. 6: 620; Para. 31: "The ion implantation modification step may also be achieved by using ion beam implantation or gas cluster ion beam implantation.").
It would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify Wang to comprise a beamline ion implantation process or a plasma doping process in order to reduce roughness of a silicon nitride layer while having dose control and uniformity.
Regarding claim 9; Wang in view of Raley teaches all the limitations of the semiconductor processing method of claim 8.
Further, Wang teaches wherein the layer of silicon nitride is formed on a layer of polysilicon. (Wang: Fig. 1A: Para. 22).
Regarding claim 10; Wang in view of Raley teaches all the limitations of the semiconductor processing method of claim 8.
Further, Wang teaches wherein the layer of silicon nitride is formed through plasma-enhanced chemical vapor deposition (Wang: Fig. 1A; Para. 22).
Regarding claim 14; as best understood based on the 35 U.S.C. 112(b) issue identified above, Wang in view of Raley teaches all the limitations of the semiconductor processing method of claim 8.
Wang fails to teach wherein the beamline ion implantation process or the plasma doping process is performed at a temperature of less than or about 50 °C.
However, Raley teaches wherein the beamline ion implantation process or the plasma doping process is performed at a temperature of less than or about 50 °C (Fig. 6: 620; Para. 31: "In one exemplary embodiment, the hydrogen (H.sub.2) plasma may be performed with process conditions of 0 W to 500 W source power, 20 W to 200 W bias power, 5 mT to 50 mT pressure, '110° C. to 100° C. (and more preferably 40° C.) electrostatic chuck temperature,").
It would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify Wang by having the beamline ion implantation process or the plasma doping process to be performed at a temperature less than or about 50 °C to control damage. Furthermore, according to MPEP § 2144.05 (II-A), differences in temperature will not support the patentability of subject matter encompassed by the prior art unless there is evidence indicating such dimension is critical. “[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955)”.
Regarding claim 15; Wang in view of Raley teaches all the limitations of semiconductor processing method of claim 8.
Further, Wang teaches wherein the beamline ion implantation process or the plasma doping process is performed with helium, neon, argon, silicon, boron, carbon, nitrogen, or germanium ions (Wang: Fig. 3: 333 carbon; Fig. 4: 438 argon).
Regarding claim 17; Wang teaches a semiconductor processing method (Fig. 1A: fabrication sequence 100) comprising:
forming a layer of silicon nitride on a semiconductor substrate within a first semiconductor processing chamber (Para. 64: "The processing apparatus 551 may include a chamber 552 to enclose components configured to perform wet or dry deposition or etch operations, possibly in addition to other operations (e.g., by having a source for atom implantation operations)… The system 550 may include a number of chambers 552 that are each configured to perform particular processes (e.g., a wet etch process, a dry etch process, a wet deposition process, a dry deposition process, a wet clean process, a dry clean process, an atom implantation process, among others) during the fabrication sequence."),
wherein the layer of silicon nitride is characterized by a first roughness (a first roughness is implied by reducing the roughness),
and wherein the layer of silicon nitride is formed on a layer of material (Fig. 1A: dielectric material 105 disposed on substrate 103);
transferring the semiconductor substrate from the first semiconductor processing chamber to an ion implantation chamber (Para. 64: "The processing apparatus 551 may include a chamber 552 to enclose components configured to perform wet or dry deposition or etch operations, possibly in addition to other operations (e.g., by having a source for atom implantation operations)… The system 550 may include a number of chambers 552 that are each configured to perform particular processes (e.g., a wet etch process, a dry etch process, a wet deposition process, a dry deposition process, a wet clean process, a dry clean process, an atom implantation process, among others) during the fabrication sequence.");
performing an ion implantation process on the layer of silicon nitride (Fig. 1A: Para. 31: "The atoms 113 may be preferentially implanted to an intended (e.g., selected) depth and/or an intended density"; Para. 34: "The atoms 113 shown and described as being implanted at point 101-5 are illustrated at point 101-6 as having an increased density (represented by increased stippling) in the hard mask material 106 portions of the pillars 115 than the densities of the atoms implanted into the lower RI material 109 and dielectric material 105 portions."),
wherein the ion implantation process comprises a beamline ion implantation process or a plasma doping process;
and reducing a surface roughness of the layer of silicon nitride to a second roughness less than the first roughness (Para. 29: "As described herein, the atoms may be implanted to reduce a probability of the unintended bend of, or roughness on, the pillar").
Wang fails to teach wherein the ion implantation process comprises a beamline ion implantation process or a plasma doping process.
However, Raley teaches wherein the ion implantation process comprises a beamline ion implantation process or a plasma doping process (Fig. 6: 620; Para. 31: "The ion implantation modification step may also be achieved by using ion beam implantation or gas cluster ion beam implantation.").
It would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify Wang to have the ion implantation process comprise a beamline ion implantation process or a plasma doping process as disclosed in Raley in order to have dose control and uniformity.
Regarding claim 18; Wang in view of Raley teaches all the limitations of the semiconductor processing method of claim 17.
Further, Wang teaches wherein the layer of material comprises polysilicon (Wang: Fig. 1A: Para. 22).
Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over Wang et al, US 20210005455 A1 (Wang), in view of Raley et al, US 20220037152 A1 (Raley) as applied to claim 15 above, and further in view of Haverkamp et al, US 20110236594 A1 (Haverkamp).
Regarding claim 16, Wang in view of Raley teaches all the limitations of the semiconductor processing method of claim 15.
Wang in view of Raley fails to teach specific values for “the second roughness”. Thus, Wang in view of Raley fails to teach the claimed roughness configuration “wherein the second roughness is less than or about 0.40 nm”.
Haverkamp teaches the first roughness is 5.1 angstroms (Para. 55: “For reference, the roughness of a 1000 .ANG. silicon nitride film deposited on a bare silicon substrate is 5.1 .ANG. Ra.”), and this roughness reasonably corresponds to the first roughness of Wang in view of Raley because it is a characteristic measured in the same way, (i.e., before “performing a beamline ion implantation process or a plasma doping process on the layer of silicon nitride”). Accordingly, the second roughness (of Wang in view of Raley) must necessarily be less than the first roughness (of Haverkamp) because this first roughness is still subject to the same technique as before (i.e., the “beamline ion implantation process or a plasma doping process on the layer of silicon nitride” of Wang in view of Raley, cited in the claim 8 rejection). This resultant “second roughness” would therefore be less than 5.1 angstroms; and this roughness is reasonably close to the claimed configuration “wherein the second roughness is less than or about 0.40 nm” because it includes values within the same order of magnitude. According to MPEP § 2144.05 (I), “a prima facie case of obviousness exists where the claimed ranges or amounts do not overlap with the prior art but are merely close. Titanium Metals Corp. of America v. Banner, 778 F.2d 775, 783, 227 USPQ 773, 779 (Fed. Cir. 1985).” Therefore, it would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify Wang in view of Raley to have a second roughness less than or about 0.40 nm as disclosed in Haverkamp in order to improve performance.
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Wang et al, US 20210005455 A1 (Wang), in view of Raley et al, US 20220037152 A1 (Raley) as applied to claim 17 above, and further in view of Haverkamp et al, US 20110236594 A1 (Haverkamp).
Regarding claim 20, Wang in view of Raley teach all the limitations of the semiconductor processing method of claim 17.
Wang in view of Raley fails to teach specific values for “the first roughness” or “the second roughness”. Thus, Wang in view of Raley fails to teach the claimed roughness configurations “wherein the first roughness is at least about 0.60 nm, and wherein the second roughness is less than or about 0.50 nm.”
However, Haverkamp teaches the first roughness is 5.1 angstroms (Para. 55: “For reference, the roughness of a 1000 .ANG. silicon nitride film deposited on a bare silicon substrate is 5.1 .ANG. Ra.”), and this roughness reasonably corresponds to the first roughness of Wang because it is a characteristic measured in the same way, (i.e., before “performing an ion implantation process on the layer of silicon nitride”). This roughness is reasonably close to the claimed configuration “wherein the first roughness is at least about 0.60 nm” because it includes values within the same order of magnitude. According to MPEP § 2144.05 (I), “a prima facie case of obviousness exists where the claimed ranges or amounts do not overlap with the prior art but are merely close. Titanium Metals Corp. of America v. Banner, 778 F.2d 775, 783, 227 USPQ 773, 779 (Fed. Cir. 1985).”
Accordingly, the second roughness (of Wang in view of Raley) must necessarily be less than the first roughness (of Haverkamp) because this first roughness is still subject to the same technique as before (i.e., the “ion implantation process on the layer of silicon nitride” of Wang in view of Raley, cited in the claim 17 rejection). This resultant “second roughness” would therefore be less than 5.1 angstroms; and this roughness is reasonably close to the claimed configuration “wherein the second roughness is less than or about 0.50 nm” because it includes values within the same order of magnitude. According to MPEP § 2144.05 (I), “a prima facie case of obviousness exists where the claimed ranges or amounts do not overlap with the prior art but are merely close. Titanium Metals Corp. of America v. Banner, 778 F.2d 775, 783, 227 USPQ 773, 779 (Fed. Cir. 1985).”
Therefore, it would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify Wang in view of Raley to have a first roughness of at least about 0.60 nm and a second roughness less than or about 0.50 nm as disclosed in Haverkamp in order to improve performance.
Claims 11-13 are rejected under 35 U.S.C. 103 as being unpatentable over Wang et al, US 20210005455 A1 (Wang), in view of in view of Raley et al, US 20220037152 A1, as applied to claim 8 above, and in further view of Shero et al, US 11424119 B2 (Shero).
Regarding claim 11; as best understood based on the 35 U.S.C. 112(b) issue identified above, Wang in view of Raley teaches all the limitations of the semiconductor processing method of claim 8.
Wang in view of Raley fails to teach wherein the layer of silicon nitride is characterized by a thickness of less than or about 100 nm.
However, Shero teaches wherein the layer of silicon nitride is characterized by a thickness of less than or about 100 nm (Col. 6, Lines 28-29: “silicon nitride film with a thickness of between approximately 0.3 nm and approximately 30 nm.”).
Wang, Raley, and Shero are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify Wang in view of Raley to have the layer of silicon nitride characterized by a thickness of less than or about 100 nm in order to create smaller devices. Furthermore, according to MPEP § 2131.03 (I), “a specific example in the prior art which is within a claimed range anticipates the range. "[W]hen, as by a recitation of ranges or otherwise, a claim covers several compositions, the claim is ‘anticipated’ if one of them is in the prior art." Titanium Metals Corp. v. Banner, 778 F.2d 775, 227 USPQ 773 (Fed. Cir. 1985).”
Regarding claim 12; as best understood based on the 35 U.S.C. 112(b) issue identified above, Wang in view of Raley teaches all the limitations of the semiconductor processing method of claim 8, wherein the layer of silicon nitride is formed at a temperature of less than or about 500 °C, and wherein the beamline ion implantation process or the plasma doping process is performed at a temperature of less than or about 550 °C (Raley Fig. 6: 620; Para. 31: "In one exemplary embodiment, the hydrogen (H.sub.2) plasma may be performed with process conditions of 0 W to 500 W source power, 20 W to 200 W bias power, 5 mT to 50 mT pressure, '110° C. to 100° C. (and more preferably 40° C.) electrostatic chuck temperature,").
Wang in view of Raley fails to teach wherein the layer of silicon nitride is formed at a temperature of less than or about 500 °C.
However, Shero teaches wherein the layer of silicon nitride is formed at a temperature of less than or about 500 °C (Col. 2, Lines 8-12: “The step of selectively depositing a layer comprising silicon nitride… A temperature of a susceptor within the reaction chamber and/or a reaction chamber during the step of selectively depositing is between about 100° C. and about 500° C.”).
It would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify Wang in view of Raley in further view of Shero to have the layer of silicon nitride formed at a temperature of less than or equal 500 °C in order to control damage. Furthermore, according to MPEP § 2144.05 (II-A), differences in temperature will not support the patentability of subject matter encompassed by the prior art unless there is evidence indicating such dimension is critical. “[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955)”.
Regarding claim 13; as best understood based on the 35 U.S.C. 112(b) issue identified above, Wang in view of Raley in further view of Shero teaches the semiconductor processing method of claim 12.
Further, Wang in view of Raley teaches wherein the beamline ion implantation process or the plasma doping process is performed at a temperature of greater than or about -100 °C. (Raley: Fig. 6: 620; Para. 31: "In one exemplary embodiment, the hydrogen (H.sub.2) plasma may be performed with process conditions of 0 W to 500 W source power, 20 W to 200 W bias power, 5 mT to 50 mT pressure, '110° C. to 100° C. (and more preferably 40° C.) electrostatic chuck temperature,").
It would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify Wang in view of Raley in further view of Shero to have beamline ion implantation process or the plasma doping process is performed at a temperature of greater than or about -100 °C in order to control damage. Furthermore, according to MPEP § 2144.05 (II-A), differences in temperature will not support the patentability of subject matter encompassed by the prior art unless there is evidence indicating such dimension is critical. “[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955)”.
Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over Wang et al, US 20210005455 A1 (Wang), in view of in view of Raley et al, US 20220037152 A1, as applied to claim 17 above, and in further view of Shero et al, US 11424119 B2 (Shero).
Regarding claim 19; as best understood based on the 35 U.S.C. 112(b) issue identified above, Wang in view of Raley teaches the semiconductor processing method of claim 17, wherein the layer of silicon nitride is formed at a temperature of less than or about 550 °C, and wherein the ion implantation process is performed at a temperature of greater than or about -100 °C. (Raley: Fig. 6: 620; Para. 31: "In one exemplary embodiment, the hydrogen (H.sub.2) plasma may be performed with process conditions of 0 W to 500 W source power, 20 W to 200 W bias power, 5 mT to 50 mT pressure, '110° C. to 100° C. (and more preferably 40° C.) electrostatic chuck temperature,").
Wang in view of Raley fails to teach wherein the layer of silicon nitride is formed at a temperature of less than or about 550 °C.
However, Shero teaches wherein the layer of silicon nitride is formed at a temperature of less than or about 550 °C (Col. 2, Lines 8-12: “The step of selectively depositing a layer comprising silicon nitride… A temperature of a susceptor within the reaction chamber and/or a reaction chamber during the step of selectively depositing is between about 100° C. and about 500° C.”).
Wang, Raley, and Shero are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify Wang in view of Raley in further view of Shero to have the layer of silicon nitride formed at a temperature of less than or about 550 °C in order to control damage. Furthermore, according to MPEP § 2144.05 (II-A), differences in temperature will not support the patentability of subject matter encompassed by the prior art unless there is evidence indicating such dimension is critical. “[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955)”.
Conclusion
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/AUBRIE IRENE HETHERINGTON/Examiner, Art Unit 2817 8/7/2026
/Kretelia Graham/Supervisory Patent Examiner, Art Unit 2817
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