DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Group I, Species I (Fig. 4-5), (claims 1-10) in the reply filed on 06/18/2026 is acknowledged.
Claims 11-16 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 6/18/26.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 1-10 are rejected under 35 U.S.C. 112(b), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor regards as the invention.
Claim 1 defines “an encapsulation resin encapsulating the semiconductor element and the electrical conductor” and “the encapsulation resin covers the element back surface, the element side surface, and the wiring front surface” is indefinite. As described in specification para [0031] and Fig.4 shows an encapsulation portion 80 of the encapsulation resin 60 covers the element back surface, the element side surface, and the wiring front surface. Appropriate correction is required.
Claim 4 defines “wherein the element front surface of the semiconductor element and the resin front surface of the encapsulation resin each include a cut mark” is indefinite. Para [0107] describes a cut mark is formed in the exposed wiring side surface 45 of the wiring line 40 and the encapsulation side surface 83 of the encapsulation portion 80 (the resin side surface 63 of the encapsulation resin 60). Appropriate correction is required.
Claim 10 defines in line 6 “the substrate include..” has antecedent issues which should be “the flat substrate includes..”. Appropriate correction is required.
Claims 2-10 are also rejected being dependent on claim 1.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-10 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yanagida et al (JP 2020027850A).
Regarding claim 1: Yanagida teaches in Fig. 20 about a semiconductor device, comprising:
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a semiconductor element 20 including an element front surface, an element back surface opposite to the element front surface, and an element side surface joining the element front surface and the element back surface (As marked);
an electrical conductor 30 opposed to the element back surface and including a wiring line 31 on which the semiconductor element is mounted (As shown); and
an encapsulation resin 60 encapsulating the semiconductor element and the electrical conductor, wherein
the wiring line 31 includes a wiring front surface opposed to the element back surface and a wiring back surface opposite to the wiring front surface (as marked),
the electrical conductor includes a terminal 32 extending from the wiring back surface in a direction (downward direction -Z) opposite from the semiconductor element (+Z direction),
the encapsulation resin covers the element back surface, the element side surface, and the wiring front surface (As shown by 60A), and
the element front surface is exposed without being covered by the encapsulation resin (as shown the element front surface is no covered by 60).
Regarding claim 2: Yanagida teaches in Fig. 20 wherein the encapsulation resin includes a resin front surface facing in a same direction as the element front surface of the semiconductor element, and the element front surface of the semiconductor element is greater in area than the resin front surface.
Regarding claim 3: Yanagida teaches in Fig. 20 wherein the encapsulation resin includes a resin front surface facing in a same direction as the element front surface of the semiconductor element, and the resin front surface is flush with the element front surface of the semiconductor element.
Regarding claim 4: As marked above, Yanagida teaches in Fig. 20 wherein the element front surface of the semiconductor element and the resin front surface of the encapsulation resin each include a cut mark.
Regarding claim 5: As marked above, Yanagida teaches in Fig. 20 wherein the encapsulation resin includes a resin front surface facing in a same direction as the element front surface of the semiconductor element, a resin back surface opposite to the resin front surface, and a resin side surface joining the resin front surface and the resin back surface, and the terminal is exposed from the resin back surface and the resin side surface.
Regarding claim 6: As marked above, Yanagida teaches in Fig. 20 wherein the terminal includes an exposed terminal side surface exposed from the resin side surface, and the exposed terminal side surface is flush with the resin side surface.
Regarding claim 7: As marked above, Yanagida teaches in Fig. 20 wherein the wiring line includes an exposed wiring side surface exposed from the resin side surface, and the exposed wiring side surface is flush with the resin side surface.
Regarding claim 8: Yanagida teaches in Fig. 20 wherein the semiconductor element 10 and the wiring line 31 are electrically connected by a conductive bonding portion 13 arranged between the semiconductor element and the wiring line, and the encapsulation resin covers a region of the wiring front surface excluding a region in which the bonding portion is arranged (as shown).
Regarding claim 9: Yanagida teaches in Fig. 20 wherein the wiring line extends in a direction orthogonal to a thickness-wise direction of the encapsulation resin.
Regarding claim 10: Yanagida teaches in Fig. 20 wherein the encapsulation resin 60 includes
a flat substrate 60B, and
an encapsulation portion 60A formed on the substrate to encapsulate the semiconductor element 10,
the substrate includes a substrate front surface facing in a same direction as the element front surface of the semiconductor element (as marked), and
the wiring line 31 is formed on the substrate front surface (as marked above).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MOHAMMED SHAMSUZZAMAN whose telephone number is (571)270-1839. The examiner can normally be reached Monday-Friday 7 am -4 pm EST.
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/Mohammed Shamsuzzaman/Primary Examiner, Art Unit 2897
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