Prosecution Insights
Last updated: September 25, 2026
Application No. 18/616,917

SEMICONDUCTOR DEVICE

Non-Final OA §102§103
Filed
Mar 26, 2024
Priority
May 16, 2023 — JP 2023-080894
Examiner
GALVAN, ANGELICA ROS ESTIGOY
Art Unit
Tech Center
Assignee
Renesas Electronics Corporation
OA Round
1 (Non-Final)
Grant Probability
Favorable
1-2
OA Rounds

Examiner Intelligence

Grants only 0% of cases
0%
Career Allowance Rate
0 granted / 0 resolved
-60.0% vs TC avg
Minimal +0% lift
Without
With
+0.0%
Interview Lift
resolved cases with interview
Typical timeline
Avg Prosecution
19 currently pending
Career history
11
Total Applications
across all art units
This examiner has no resolved cases yet (career too new); statute-level performance unavailable. The Grant Probability card shows Tech Center averages instead.

Office Action

§102 §103
DETAILED ACTION This Office Action is in response to Application filed March 26, 2024. Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Priority Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55. Election/Restrictions Applicants’ election without traverse of Species A, drawn to a semiconductor device whose structure is shown in Figs. 1-21, which read on claims 1-5 and 7, in the reply filed on July 13, 2026 is acknowledged. Claims 6 and 8-17 withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected species, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on July 13, 2026. Claim Objections Claim 3 is objected to because of the following informality: On lines 3 of claim 3, a typo of “trenche” instead of “trench” should be corrected. Appropriate correction is required. Claim Rejections - 35 USC § 102 (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claim(s) 1-4 is/are rejected under 35 U.S.C. 102a(1) as being anticipated by Nishiwaki (JP 2012059943 A, which Applicants filed on July 21, 2026 together with IDS; attached English Translation of JP 2012059943 A is used for current Office Action). Regarding claim 1, as best understood, Nishiwaki discloses a semiconductor device (Fig. 13) comprising: a semiconductor substrate (11) of a first conductivity type having an upper surface and a lower surface; a first trench (20) formed in the semiconductor substrate (11) so as to reach a predetermined depth from the upper surface of the semiconductor substrate (11); a field plate electrode (22) formed in a lower portion of the first trench (20) inside the first trench (20) and electrically isolated from the semiconductor substrate (11); a first gate electrode (26) formed in an upper portion of the first trench (20) inside the first trench (20) and electrically isolated from the semiconductor substrate (11) and the field plate electrode (22); a second trench (30) formed in the semiconductor substrate (11) so as to reach a predetermined depth from the upper surface of the semiconductor substrate (11); and a second gate electrode (32) formed inside the second trench (30) and electrically isolated from the semiconductor substrate (11), wherein a depth of the first trench (20) is greater than a depth of the second trench (30); and wherein the first trench (20) is surrounded by the second trench (30) in plan view. Regarding claim 2, Nishiwaki discloses the semiconductor device according to claim 1, wherein a gate potential is supplied to the first gate electrode (26) and the second gate electrode (32), and the field plate electrode (22) is electrically floating. Regarding claim 3, Nishiwaki discloses the semiconductor device according to claim 1, wherein the second trench (Fig. 18b, 30) forms a honeycomb structure (Fig. 18b, 7B) in plan view, and one first trench (20) is formed in a regular hexagon of the honeycomb structure (Fig. 18b, 7B). Regarding claim 4, Nishiwaki discloses the semiconductor device according to claim 1, wherein the second trench (30) forms a honeycomb structure (Fig. 18b, 7B) in plan view, and a center portion of the first trench (20) in plan view corresponds to a center of gravity of a regular hexagon of the honeycomb structure (Fig. 18b, 7B). Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Nishiwaki (JP 2012059943 A). Regarding claim 5, as best understood, Nishiwaki discloses the semiconductor device according to claim 4. Nishiwaki does not disclose the first trench has a circular planar shape in Fig. 18b. Nishiwaki discloses the first trench has a circular planar shape in Fig. 18c. It would have been obvious for one of ordinary skill in the art to substitute the hexagonal shaped first trench disclosed by Nishiwaki in Fig. 18b with the circular shaped first trench disclosed by Nishiwaki in Fig. 18c because it is common practice to improve device performance by optimizing the shape of materials used. Allowable Subject Matter Claim 7 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to ANGELICA ROSE E. GALVAN whose telephone number is (571)270-0122. The examiner can normally be reached Monday - Friday 8:30am - 6:00pm ET. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Joshua Benitez can be reached at (571) 270-1435. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /JAY C KIM/Primary Examiner, Art Unit 2815 /ANGELICA ROSE GALVAN/Examiner, Art Unit 2815
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Prosecution Timeline

Mar 26, 2024
Application Filed
Aug 10, 2026
Non-Final Rejection mailed — §102, §103 (current)

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Prosecution Projections

1-2
Expected OA Rounds
Grant Probability
Low
PTA Risk
Based on 0 resolved cases by this examiner. Grant probability derived from career allowance rate.

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