Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on March 26, 2024 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Response to Amendment
The Amendment filed February 23, 2026 has been entered. Claims 1-15 & 17-21 remain pending in the application. Claims 1, 2, 6, 7, 10-13, & 17 have been amended. Claim 16 is canceled. Claims 18-21 are new. Applicant’s amendments to the Claims have overcome each and every objection and 35 U.S.C. § 112(a) & 112(b) rejections previously set forth in the Non-Final Office Action mailed November 24, 2025, hereafter referred to as the Non-Final Office Action.
Response to Arguments
Applicant's arguments, please refer to pp. 7-9 of applicant’s remarks, filed February 23, 2026 have been entered and fully considered. In light of the amendments, the rejection(s) have been withdrawn. However, upon further consideration, in light of the amendment(s), a new ground(s) of rejection(s) have been made, and applicant’s arguments are rendered moot. Therefore, the rejection(s) of amended independent claims 1, 6 & 10, and dependent claims 2-5, 7-9, 11-15 & 17-21, which depend from and incorporate the limitations of amended independent claims 1, 6 & 10, are respectively maintained. Updated rejections based on amended features follow.
Claim Objections
Claim 6 is objected to because of the following informalities:
Claim 6 recites, “and alignment formation aligned with the first alignment member with the second alignment member,” in ll. 11-13, suggest rephrasing to read, “and alignment formation aligned with the first alignment member and with the second alignment member,”.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 1-21 is rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Claim 1 recited the new limitation, “a first distance between the first and second chamfered surfaces at an interface between the first and second alignment members being greater than a second distance between the first and second chamfered surfaces at a first end of the first alignment member opposite the second alignment member,” in ll. 11-14. The amended claim language is part of a method, but does not mention in the disclosure or figures “a first distance…at an interface…being greater than a second distance…,” which is important due to the alignment taking place in the apparatus of the invention. Claims 2-5 are rejected by virtue of dependance to claim 1, which do not rectify the defect
Claim 6 recites the new limitation, “first and second chamfered surfaces in the first alignment member, a gap between the first and second chamfered surfaces being narrower at a first end of the alignment member than at a second end of the first alignment member” in ll. 6-9. The amended claim language is part of an apparatus, but does not mention in the disclosure or figures a “gap between the first and second chamfered surfaces being narrower at a first end…”. Claims 7-9 are rejected by virtue of dependance to claim 6, which do not rectify the defect.
Claim 10 recites the new limitation, “the exposing the protected second surface of the semiconductor device to the chamfered surface preceding the aligning the first alignment member with the second alignment member” in ll. 9-11. The amended claim language is part of a method, but does not mention in the disclosure or figures the “chamfered surface preceding the aligning with the first alignment member…”. Claims 11-21 are rejected by virtue of dependance to claim 10, which do not rectify the defect.
Claim 18 recites the new limitation ”wherein the first alignment member includes a second chamfered surface opposite the first chamfered surface along a first direction.” in ll. 1-2. Neither the disclosure or the figures mention a “second chamfered surface” that is “opposite” to the “first chamfered surface” along a “first direction”, instead the disclosure mentions tapering, upward and horizontal directions. Claims 19-21 are rejected by virtue of dependance to claim 18, which do not rectify the defect.
Claim 19 recites the new limitation “wherein the first alignment member has a first end opposite a second end along a second direction transverse to the first direction”, in ll. 1-2. Neither the disclosure or figures mention a “first end opposite a second end along a second direction transverse to the first direction”, instead mentions tapering, upward and horizontal directions in the disclosure. Claims 20-21 are rejected by virtue of dependance to claim 19, which do not rectify the defect.
Claim 20 recites the new limitation “wherein a gap between the first and second chamfered surfaces has a width…”, in ll. 1-3, where neither the disclosure or the figures mention a gap or something similar between the first and second chamfered surfaces, or mention a “first” or “second” widths along a “first” “or second” directions, instead mention tapering, upward and horizontal directions in the disclosure. Claim 21 is rejected by virtue of dependance to claim 20, which does not rectify the defect.
Claim 21 recites the new limitation, “the first width is approximately a width of the semiconductor device” in ll. 1-2. The first width is part of a method, but does not mention in the disclosure what the “first width” corresponds to, which could be either a first or second alignment member, or the mentioned “gap” between the alignment members, or the chamfered surfaces.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-21 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recites the amended limitation “a first distance between the first and second chamfered surfaces at an interface between the first and second alignment members being greater than a second distance between the first and second chamfered surfaces at a first end of the first alignment member opposite the second alignment member,” in ll. 11-14, and introduces indefiniteness for this claim, not clearly defining the metes and bounds. Neither the disclosure or figures mention “a first distance…at an interface…being greater than a second distance…,” and unable to determine that the “first distance” being “greater than a second distance between the first and second chamfered surfaces…”. Instead the disclosure mentions tapering, upward and horizontal directions, and unable to determine if the directions pertain to those disclose in the disclosure. Claims 2-5 are rejected by virtue of dependance to claim 1, which do not rectify the defect.
Claim 6 recites the amended limitation “first and second chamfered surfaces in the first alignment member, a gap between the first and second chamfered surfaces being narrower at a first end of the alignment member than at a second end of the first alignment member;” In ll. 6-9, and introduces indefiniteness for this claim, not clearly defining the metes and bounds. Neither the disclosure or figures mention a “gap between the first and second chamfered surfaces being narrower at a first end…”, and unable to determine if the “gap” (which is not visible in the figures) or the alignment members (“first” or “second”) are “narrower“. Claims 7-9 are rejected by virtue of dependance to claim 6, which do not rectify the defect.
Claim 10 recites the amended limitation “the exposing the protected second surface of the semiconductor device to the chamfered surface preceding the aligning the first alignment member with the second alignment member.” In ll. 9-11, and introduces indefiniteness for this claim. Neither the disclosure or figures mention a “protected second surface of the semiconductor device” and unable to determine which “chamfered surface preceding” (“first” or “second”) “the aligning the first alignment member with the second alignment member”. Claims 11-21 are rejected by virtue of dependance to claim 10, which do not rectify the defect.
Claim 18 recites the new limitation ”wherein the first alignment member includes a second chamfered surface opposite the first chamfered surface along a first direction.” in ll. 1-2, and introduces indefiniteness for this claim, not clearly defining the metes and bounds. Neither the disclosure or the figures mention a “second chamfered surface” that is “opposite” to the “first chamfered surface” along a “first direction”, instead the disclosure mentions tapering, upward and horizontal directions, unable to determine the “first direction”. Claims 19-21 are rejected by virtue of dependance to claim 18, which do not rectify the defect.
Claim 21 recites the new limitation "the first width is approximately a width of the semiconductor device" in ll. 1-2, and introduces indefiniteness for this claim, not clearly defining the metes and bounds. Unable to determine if the “first width” corresponds to either a first or second alignment member, or a first or second chamfered surface, or the mentioned “gap” between the first or second alignment members, or substrate, or the chamfered surfaces.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2, 5 & 10-13 & 18-21 are rejected under 35 U.S.C. 103 as being unpatentable over Akram et al. (US 2001/0024129 A1, Pub. Date Sep. 27, 2001, hereinafter Akram), in view of Sugano (WO 2007043177 A1, Pub. Date Apr. 19, 2007, hereinafter, Sugano), in view of Lee et al. (US 2020/0044306 A1, Pub. Date Feb. 6, 2020, hereinafter, Lee), and further in view of NPL: Parrish, Sarah. "A Study of Defects in High Reliability Die Sort Applications." International Symposium on Microelectronics. Vol. 2019. No. 1. International Microelectronics Assembly and Packaging Society, 2019, hereinafter, Parrish.
Regarding independent claim 1, Akram, teaches:
A method ([Abstract], [0003], [0012], [0022]-[0024] & [0051]-[0053]), comprising:
Akram, is silent in regard to:
aligning electrical contact formations in an array of electrical contact formations on a first surface of a semiconductor device with electrically conductive pins in an array of electrically conductive pins,
aligning the first alignment member with a second alignment member having the array of electrically conductive pins aligned therewith,
wherein the array of electrical contact formations is aligned with respect to the array of electrically conductive pins in response to the first and second alignment members being mutually aligned.
However, Akram, in combination with Sugano, further teach:
aligning electrical contact formations in an array of electrical contact formations on a first surface of a semiconductor device with electrically conductive pins in an array of electrically conductive pins (Disclosed in combination: Akram: Figs. 1 & 3; [Abstract], [0003], [0012], [0022]-[0024] [0051]-[0053] & [0084]: interposer 100 aligns the conductive structures 152 (e.g., solder bumps) of a semiconductor device 150 with the conductive structures 142 (e.g., solder bumps/pins) on its bottom side, which are aligned with the test sockets/pads of the test substrate; Sugano: Fig. 7; [0054]: Fig. 7 illustrates the semiconductor device 100 with contact pads 102 aligned to and contacting the conductive pins 113 of the test socket 112),
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It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor testing method of Akram to incorporate the mutual mechanical alignment system (the mating IC housing and test socket taught by Sugano), according to known methods. The motivation to do so would be to ensure accurate, repeatable, and automated physical alignment of the semiconductor device with the test socket prior to the electrical engagement. Forcing the mutual alignment of the holding member and the socket ensures that the microscopic contact pads on the device are accurately coupled to the contact pins, preventing misalignment, reducing the risk of crushing or damaging the conductive pins during automated testing operations, improving overall test yield, thus yielding expected predictable results (KSR).
However, Sugano, further teaches:
aligning the first alignment member with a second alignment member having the array of electrically conductive pins aligned therewith (Fig. 7; [0054]: teaches mutually aligning the first and second alignment members),
wherein the array of electrical contact formations is aligned with respect to the array of electrically conductive pins in response to the first and second alignment members being mutually aligned (Fig. 7; [0054] & [0056]: connects the mutual alignment of the housing/socket to the alignment of the contacts/pins).
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It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor testing method of Akram to incorporate the mutual mechanical alignment system (the first alignment member housing and the second alignment member test socket with mating guide pins and holes) taught by Sugano, according to known methods. The motivation to do so would be to provide a mechanism that forces the accurate, mutual physical alignment of the holding member and the socket prior to electrical engagement. As taught by Sugano, this ensures that the microscopic contact pads on the device are accurately coupled to the contact pins, preventing misalignment, reducing the risk of crushing or damaging the conductive pins during automated testing operations, improving overall test yield and reliability, thus yielding expected predictable results (KSR).
Akram, in combination with Sugano, are silent in regard to:
wherein the semiconductor device comprises, opposite the first surface, a second surface protected by a protection layer,
However, Lee, further teaches:
wherein the semiconductor device comprises, opposite the first surface, a second surface protected by a protection layer ([Abstract], [0027]-[0028], [0038], [0048]-[0049], [0052], [0060], [0063]-[0069], [Claim 1], [Claim 4] & [Claim 18]: teaches a semiconductor device comprising a protective layer (insulating encapsulation) that encapsulates the chip),
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to further modify the semiconductor device undergoing the testing and alignment method of Akram and Sugano to comprise the insulating encapsulation (protection layer) covering the surfaces opposite the contacts, as taught by Lee, according to known methods. The motivation to do so would be to physically protect the fragile semiconductor chip from mechanical stress, chipping, or environmental damage during the automated handling, physical clamping, and alignment processes executed by the test fixtures, ensuring the structural integrity of the device before, during, and after testing, and yielding expected predictable results (KSR).
Akram, in combination with Sugano, and Lee, are silent in regard to:
wherein the aligning includes:
aligning the semiconductor device to a first alignment member by exposing the protected second surface of the semiconductor device to a first chamfered surface in the first alignment member, the first alignment member having a second chamfered surface opposite the first chamfered surface; and
a first distance between the first and second chamfered surfaces at an interface between the first and second alignment members being greater than a second distance between the first and second chamfered surfaces at a first end of the first alignment member opposite the second alignment member,
However, Parish, further teaches:
wherein the aligning includes:
aligning the semiconductor device to a first alignment member by exposing the protected second surface of the semiconductor device to a first chamfered surface in the first alignment member, the first alignment member having a second chamfered surface opposite the first chamfered surface (Fig. 1; [II. Sensitive Device Surfaces, C. Die Sorting, pp. 2-3]: teaches a first alignment member (a die collet) having chamfered/slanted surfaces used to align a semiconductor device without touching its protected back surface); and
a first distance between the first and second chamfered surfaces at an interface between the first and second alignment members being greater than a second distance between the first and second chamfered surfaces at a first end of the first alignment member opposite the second alignment member (Fig. 1; [II. Sensitive Device Surfaces, C. Die Sorting, pp. 2-3]: teaches the exact inverted geometry, discloses that the tools “can be in the form of an inverted pyramid collet”, visually depicted in “Fig. 1 Pick-up Tool Comparison…(c) Inverted pyramid style collet”. An ”inverted pyramid” geometry defines an internal cavity where the bottom opening (interface) is geometrically wider or greater in distance than the internal top ceiling (first end), creating the edge-grip profile),
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor testing method of Akram to incorporate the mutual mechanical alignment system (the first and second alignment members) taught by Sugano, further modifying the semiconductor device to include the insulating encapsulation taught by Lee, and further modifying the first alignment member to utilize the inverted pyramid collet geometry taught by Parish, according to known methods. The motivation to combine Akram and Sugano would be to provide a mechanical guide system that forces accurate physical alignment between the holding member and the socket prior to electrical engagement, preventing pin damage and ensuring reliable contact. The motivation to further incorporate Lee would be to protect the fragile semiconductor chip during the automated handling and testing operations by encapsulating the surfaces opposite the contacts with a protective insulating layer. Finally, the motivation to incorporate the inverted pyramid collet of Parish as the first alignment member would be to provide an automated robotic handling mechanism that can securely catch, hold, and mutually align the semiconductor device by its edges, ensuring that “only the top edges of the device are contacted rather than the top surface” to prevent damage to the handling tool from scratching or damaging the protected encapsulation layer during the alignment process of the chip and during testing operations, as taught by Parrish, thus yielding predictable results (KSR).
Regarding dependent claim 2, Akram, teaches:
The method of claim 1 ([Abstract], [0003], [0012], [0022]-[0024], [0051]-[0053] & [Claim 73]), wherein:
Akram, in combination with Sugano, and Lee, are silent in regard to:
the chamfered surface in the first alignment member includes a tapered surface converging in a tapering direction from the interface between the first and second alignment members towards a first end of the first alignment member, and
aligning the semiconductor device to the first alignment member includes advancing the semiconductor device with respect to the first chamfered surface in the tapering direction with the protected second surface exposed to the first chamfered surface.
However, Parish, further teaches:
the chamfered surface in the first alignment member includes a tapered surface converging in a tapering direction from the interface between the first and second alignment members towards a first end of the first alignment member (Fig. 1; [II. Sensitive Device Surfaces, C. Die Sorting, pp. 2-3]: teaches the structural geometry of the first alignment member cavity converging from the wider bottom opening to a narrower top end, discloses pick-up tools “in the form of an inverted pyramid collet”, visually depicted in “Fig. 1 Pick-up Tool Comparison…(c) Inverted pyramid style collet”, the internal sidewalls form a tapered surface that converges as it moves upward (tapering direction) from the bottom opening (interface) towards the top (first end) of the collet), and
aligning the semiconductor device to the first alignment member includes advancing the semiconductor device with respect to the first chamfered surface in the tapering direction with the protected second surface exposed to the first chamfered surface (Fig. 1c; [Abstract], [I. Introduction, page 1] & [II. Sensitive Device Surfaces, C. Die Sorting, pp. 2-3]: teaches the operation method of aligning the device into the collet cavity. By utilizing the tool for the “die pick and place process”, relative motion is created where the die advances upward into the collet’s cavity (in the tapering direction). States that this is done so that “only the top edges of the device are contacted rather than the top surface,” so that the protected back surface of the die is exposed to and guided by the chamfered interior walls as it advances into the grip of the converging collet).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the testing apparatus of Akram and Sugano to utilize the inverted pyramid collet of Parrish to securely hold the encapsulated semiconductor device of Lee, according to known methods. The inverted pyramid collet, taught by Parrish, inherently comprises a tapered inner surface converging from the bottom opening toward the top end (Fig. 1(c) of Parrish). Utilizing this collect for picking and placing the die inherently requires advancing the semiconductor device into the cavity in the tapering direction until the chamfered inner walls engage the top edges of the device, leaving the protected top surface safely exposed to the interior cavity without making damaging contact, as intended by Parrish, yielded expected predictable results (KSR).
Regarding dependent claim 5, Akram, teaches:
The method of claim 1 ([Abstract], [0003], [0012], [0022]-[0024] & [0051]-[0053]), wherein the semiconductor device includes a Wafer Level Chip Scale Package semiconductor device ([0003] & [0010]).
Regarding independent claim 10, Akram, teaches:
A method ([Abstract], [0003], [0012], [0022]-[0024], & [0051]-[0053], [0059], [0062], [0064] & [0090]), comprising:
Akram, is silent in regard to:
aligning electrical contact formations on a first surface of the semiconductor device with electrically conductive pins;
mutually aligning the first alignment member with a second alignment member having the electrically conductive pins thereby aligning the electrical contact formations with the electrically conductive pins,
However, Sugano, further teaches:
aligning electrical contact formations on a first surface of the semiconductor device with electrically conductive pins (Fig. 7; [0054] & [0056]: teaches aligning the contact pads of the device to the conductive pins);
mutually aligning the first alignment member with a second alignment member having the electrically conductive pins thereby aligning the electrical contact formations with the electrically conductive pins (Fig. 7; [0054] & [0056]: teaches mutual alignment of the holding member and the socket),
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to further modify the semiconductor testing method of Akram to incorporate the step of mutually aligning the first alignment member with a second alignment member having the electrically conductive pins, as taught by Sugano, according to known methods. The motivation to do so would be to utilize a mechanical guide system (such as mating guide pins and holes) that forces accurate, repeatable physical alignment between the device holding member and the test socket prior to electrical engagement. As taught by Sugano, forcing this mutual alignment ensures that the microscopic electrical contact arrays are accurately coupled, preventing misalignment, reducing the risk of crushing or damaging the conductive pins during automated testing operations, and improving overall test reliability, thus yielding expected predictable results (KSR).
Akram, in combination with Sugano, are silent in regard to:
aligning the semiconductor device to a first alignment member by exposing a protected second surface of the semiconductor device to a first chamfered surface in the first alignment member; and
However, Lee, in combination with Parrish, further teach:
aligning the semiconductor device to a first alignment member by exposing a protected second surface of the semiconductor device to a first chamfered surface in the first alignment member (Disclosed in combination: Lee: [Abstract], [0027]-[0028], [0038], [0048]-[0049], [0052], [0060], [0063]-[0069], [Claim 1], [Claim 4] & [Claim 18]: teaches a semiconductor device comprising a protective layer (insulating encapsulation) that encapsulates the chip; Parrish: Fig. 1c; [Abstract], [I. Introduction, page 1] & [II. Sensitive Device Surfaces, C. Die Sorting, pp. 2-3]: teaches aligning the device into a collet (first alignment member) having chamfered surfaces without touching the protected top surface, “…a collet-style pick-up tool approach can be used where only the top edges of the device are contacted rather than the top surface.” This structurally necessitates exposing the protected surface to the chamfered walls of the inverted pyramid collet during alignment By utilizing the tool for the “die pick and place process”, relative motion is created where the die advances upward into the collet’s cavity (in the tapering direction). States that this is done so that “only the top edges of the device are contacted rather than the top surface,” so that the protected back surface of the die is exposed to and guided by the chamfered interior walls as it advances into the grip of the converging collet); and
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to further modify the automated handling and alignment apparatus used for the encapsulated semiconductor device of Lee to utilize the inverted pyramid collet geometry taught by Parrish, according to known methods. The motivation to combine these teachings would be to provide a handling mechanism capable of securely catching, holding, and aligning the encapsulated device by its edges without physically contacting its protected surface. As taught by Parrish, utilizing an inverted, chamfered cavity, ensures that “only the top edges of the device are contacted rather than the top surface.” A POSITA would be motivated to implement Parrish’s edge-grip design when handling the device of Lee to prevent the robotic picking tool from physically touching, scratching, or compromising the insulating encapsulation layer during the mutual alignment and testing operations, thus yielding expected predictable results (KSR).
Akram, in combination with Lee, are silent in regard to:
the exposing the protected second surface of the semiconductor device to the chamfered surface preceding the aligning the first alignment member with the second alignment member.
However, Sugano, in combination with Parrish, further teach:
the exposing the protected second surface of the semiconductor device to the chamfered surface preceding the aligning the first alignment member with the second alignment member (Disclosed in combination: Sugano: Fig. 7; [0054] & [0056]; Parrish: Fig. 1c; [Abstract], [I. Introduction, page 1] & [II. Sensitive Device Surfaces, C. Die Sorting, pp. 2-3]: chronologically and inherently taught by the robotic pick-and-place method taught by the combination of references. Parish’s “pick and place process” requires the “pick-up tool” (first alignment member) to pick up the device, which forces the device into the chamfered cavity and exposes the protected surface. The picking action must logically and physically precede the step of moving the tool to the testing location to mutually align the tool with the test socket (second alignment member, as taught by Sugano).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor testing method of Akram to incorporate the mutual mechanism alignment steps taught by Sugano, further modifying the semiconductor device to include the insulating encapsulation taught by Lee, and further modifying the first alignment member to utilize the inverted pyramid collect geometry taught by Parrish, according to known methods. The motivation to combine Akram and Sugano would be to provide a mechanical guide system that forces accurate physical alignment between the holding member and the socket prior to electrical engagement, preventing pin damage. The motivation to further incorporate Lee would be to protect the fragile semiconductor chip with an insulating layer during the handling operations. Finally, the motivation to incorporate the pyramid collet of Parrish as the first alignment member would be to utilize an automated pick-and-place handler than can securely catch and align the device by its edges. As intended by Parrish, this would ensure that the protected top surface of the device is exposed to the cavity rather than contacted, preventing damage to the encapsulation. Utilizing this automated robotic pick-and-place method inherently requires the step of picking the device with the collet (exposing it to the chamfered surface) to chronologically precede the step of moving the collet to mutually align with the testing socket, thus yielding expected predictable results (KSR).
Regarding dependent claim 11, Akram, teaches:
The method of claim 10 ([Abstract], [0003], [0012], [0022]-[0024], [0051]-[0053], [0059], [0062], [0064] & [0090]),
Akram, in combination with Sugano, and Lee, are silent in regard to:
wherein the first chamfered surface includes a tapered surface converging in a tapering direction from a first end towards a second end of the first alignment member.
However, Parrish, further teaches:
wherein the first chamfered surface includes a tapered surface converging in a tapering direction from a first end towards a second end of the first alignment member (Fig. 1c; [Abstract], [I. Introduction, page 1] & [II. Sensitive Device Surfaces, C. Die Sorting, pp. 2-3]: teaches the structural geometry of the first alignment member cavity converging from a wider opening to a narrower end, discloses pick-up tools in the “form of an inverted pyramid collet” as visually depicted in “Fig. 1 Pick-up Tool Comparison…(c) Inverted pyramid style collet,” the internal sidewalls form a tapered/slanted surface that inherently converges as it moves in a tapering direction from the wide bottom opening (first end) towards the narrower top ceiling (second end) of the collet).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the testing apparatus of Akram and Sugano to utilize the inverted pyramid collet of Parrish to securely hold the encapsulated semiconductor device of Lee without damaging its top surface, according to known methods. The “inverted pyramid collet” taught by Parrish inherently comprises a first chamfered surface that includes a tapered surface converging in a tapering direction. As visually depicted in Fig. 1(c), an inverted pyramid geometry physically requires the internal slanted walls to converge from the wider bottom opening (a first end) towards the narrower internal top ceiling (a second end) to catch and grip the top edges of the advancing semiconductor device, thus yielding expected predictable results (KSR).
Regarding dependent claim 12, Akram, teaches:
The method of claim 11 ([Abstract], [0003], [0012], [0022]-[0024], [0051]-[0053], [0059], [0062], [0064] & [0090])
Akram, in combination with Sugano, and Lee, are silent in regard to:
wherein the aligning the semiconductor device to the first alignment member includes advancing the semiconductor device with respect to the first chamfered surface in the tapering direction.
However, Parrish, further teaches:
wherein the aligning the semiconductor device to the first alignment member includes advancing the semiconductor device with respect to the first chamfered surface in the tapering direction (Fig. 1c; [Abstract], [I. Introduction, page 1] & [II. Sensitive Device Surfaces, C. Die Sorting, pp. 2-3]: teaches the operational method of aligning the device into the converging collet cavity. By utilizing the “inverted pyramid collet” for the “die pick and place process,” relative motion is created where the semiconductor device advances into the collet’s cavity (in the tapering direction). Parrish states that this is done so that “only the top edges of the device are contacted rather than the top surface”, which physically requires the device to advance relative to the chamfered interior walls until the narrowing taper halts its advancement by gripping the edges).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the testing apparatus of Akram and Sugano to utilize the inverted pyramid collet of Parrish to securely hold the encapsulated semiconductor device of Lee without damaging its top surface, according to known methods. The “inverted pyramid collet” taught by Parrish inherently comprises a tapered inner surface converging from the bottom opening toward the top end. Utilizing this specific collet for the automated picking and placing of the die inherently requires the step of advancing the semiconductor device into the cavity in the tapering direction until the chamfered inner walls physically engage the top edges of the device, achieving the edge-grip intended by Parrish, thus yielding expected predictable results (KSR).
Regarding dependent claim 13, Akram, teaches:
The method of claim 12 ([Abstract], [0003], [0012], [0022]-[0024], [0051]-[0053], [0059], [0062], [0064], & [0090])
Akram, in combination with Sugano, and Lee, are silent in regard to:
wherein the protected second surface is exposed to the first chamfered surface.
However, Parrish, further teaches:
wherein the protected second surface is exposed to the first chamfered surface (Fig. 1c; [Abstract], [I. Introduction, page 1] & [II. Sensitive Device Surfaces, C. Die Sorting, pp. 2-3]: teaches that the configuration of the inverted picking tool leaves the protected top surface exposed to the chamfer cavity walls rather than touching it, states “…a collet-style pick-up tool approach can be used where only the top edges of the device are contacted rather than the top surface”. By avoiding contact with the top surface while the device is held within the converging cavity, the protected second surface (from Lee) inherently remains safely exposed to the first chamfered surface).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the testing apparatus of Akram and Sugano to utilize the inverted pyramid collet of Parrish to securely hold the encapsulated semiconductor device of Lee without damaging its top surface, according to known methods. The “inverted pyramid collet” taught by Parrish is designed to ensure that “only the top edges of the device are contacted rather than the top surface”. By physically gripping only the edges of the device within the collet’s cavity, the protected second surface of the device is inherently left exposed to the first chamfered surface of the alignment member, avoiding damaging physical contact, as intended by Parrish, thus yielding expected predictable results (KSR).
Regarding dependent claim 18, Akram, teaches:
The method of claim 10 ([Abstract], [0003], [0012], [0022]-[0024], [0051]-[0053], [0059], [0062], [0064] & [0090]),
Akram, in combination with Sugano, and Lee, are silent in regard to:
wherein the first alignment member includes a second chamfered surface opposite the first chamfered surface along a first direction.
However, Parrish, further teaches:
wherein the first alignment member includes a second chamfered surface opposite the first chamfered surface along a first direction (Fig. 1c; [Abstract], [I. Introduction, page 1] & [II. Sensitive Device Surfaces, C. Die Sorting, pp. 2-3]: teaches the structural geometry of the first alignment member having opposing chamfered surfaces. Discloses pick-up tools in the “form of an inverted pyramid collet”, as visually depicted in “Fig. 1 Pick-up Tool Comparison…(c) Inverted pyramid style collet,” an inverted pyramid cavity physically requires corresponding slanted interior walls on opposite sides to enclose and grip the die. Taking a cross-section along a first direction across the collet inherently reveals a first chamfered surface and a second chamfered surface directly opposite of it).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the testing apparatus of Akram and Sugano to utilize the inverted pyramid collet of Parrish to securely hold the encapsulated semiconductor device of Lee without damaging its top surface, according to known methods. The “inverted pyramid collet” taught by Parrish inherently comprises a second chamfered surface opposite a first chamfered surface along a first direction. As visually depicted in Parrish (Fig. 1(c)), an inverted pyramid geometric cavity physically necessitates opposing slanted internal walls in order to catch, center, and grip the opposing top edges of a quadrilateral semiconductor device during automated pick-and-place operations, thus yielding expected predictable results (KSR).
Regarding dependent claim 19, Akram, teaches:
The method of claim 18 ([Abstract], [0003], [0012], [0022]-[0024], [0051]-[0053], [0059], [0062], [0064] & [0090]),
Akram, in combination with Lee, are silent in regard to:
wherein the first alignment member has a first end opposite a second end along a second direction transverse to the first direction,
However, Sugano, in combination with Parrish, further teach:
wherein the first alignment member has a first end opposite a second end along a second direction transverse to the first direction (Disclosed in combination: Sugano: Fig. 7; [0054] & [0056]: teaches the IC housing portion 530 has an upper end and a lower edge/end; Parrish: Fig. 1c; [Abstract], [I. Introduction, page 1] & [II. Sensitive Device Surfaces, C. Die Sorting, pp. 2-3]: teaches the three-dimensional geometry of the alignment member. Parrish’s inverted pyramid style collet (Fig. 1(c)) is a 3D structure that inherently has a vertical/longitudinal axis (a second direction) that is perpendicular (transverse) to the horizontal plane (first direction) containing the opposing chamfered walls. This transverse axis spans from the internal ceiling (first end) to the wide bottom opening (second end)),
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the first alignment member (IC housing) of Sugano’s mutual mechanical alignment apparatus to utilize the inverted pyramid collet geometry taught by Parrish, according to known methods. The motivation to do so would be to provide an automated robotic handling mechanism capable of securely holding the semiconductor device during the mutual alignment process while preventing physical damage to the device’s protected top surface. Sugano’s method requires the holding member to be physically driven into engagement with the test socket’s guide pins, a POSITA would be motivated to utilize Parrish’s edge-gripping collet to ensure that “only the top edges of the device are contacted rather than the top surface” during the automated handling, preventing the tool from scratching or compromising the sensitive encapsulating layer, thus yielding expected predictable results (KSR).
Akram, is silent in regard to:
the second end being directly coupled to the second alignment member.
However, Sugano, further teaches:
the second end being directly coupled to the second alignment member (Fig. 7; [0054] & [0056]: teaches that the lower end of the first alignment member directly couples to the test socket. By fitting the lower end of the housing directly onto the test socket’s guide pins, the second end is directly coupled to the second alignment member).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the testing apparatus of Akram to incorporate the mutual mechanical alignment system taught by Sugano, while utilizing the inverted pyramid collet of Parrish as the first alignment member to securely hold the encapsulated semiconductor device of Lee, according to known methods. The 3D structure of an inverted pyramid collet inherently has a longitudinal axis ( a second direction from the top ceiling to the bottom opening) that is transverse to its horizontal gripping axis (the first direction). Sugano teaches the structural configuration wherein the lower end (the second end) of the device-holding member directly couples to the test socket (the second alignment member) via mating alignment formations. Utilizing this specific coupling arrangement at the second end of the tool would have been obvious to a POSITA to physically secure the holding member against the socket, ensuring a constrained and repeatable physical alignment prior to electrical engagement, thus yielding expected predictable results (KSR).
Regarding dependent claim 20, Akram, teaches:
The method of claim 19 ([Abstract], [0003], [0012], [0022]-[0024], [0051]-[0053], [0059], [0062], [0064] & [0090]),
Akram, in combination with Sugano, and Lee, are silent in regard to:
wherein a gap between the first and second chamfered surfaces has a first width along the first direction at the first end and a second width along the first direction at the second end, the first width being smaller than the second width.
However, Parrish, further teaches:
wherein a gap between the first and second chamfered surfaces has a first width along the first direction at the first end and a second width along the first direction at the second end, the first width being smaller than the second width (Fig. 1c; [Abstract], [I. Introduction, page 1] & [II. Sensitive Device Surfaces, C. Die Sorting, pp. 2-3]: teaches the structural dimensions of the inverted pyramid collet cavity, discloses the pick-up tools in the “form of an inverted pyramid collet”. As visually depicted in “Fig. 1 Pick-up Tool Comparison…(c) Inverted pyramid style collet,” an inverted pyramid geometry physically requires that the horizontal gap (along the first direction) between the opposing chamfered walls is narrower at the internal ceiling (first width at the first end) and wider at the bottom opening (second width at the second end) in order to successfully guide and edge-grip the semiconductor device).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the testing apparatus of Akram to incorporate the mutual mechanical alignment system taught by Sugano, while utilizing the inverted pyramid collet of Parrish as the first alignment member to securely hold the encapsulated semiconductor device of Lee, according to known methods. The “inverted pyramid collet” taught by Parrish inherently comprises a gap between the opposing chamfered surfaces that is narrower at the top ceiling (first width at the first end) and wider at the bottom opening (second width at the second end). As visually depicted in Parrish (Fig. 1(c)), this inverted width differential is the physical mechanism that creates the edge-grip, allowing the wide bottom to clear the device and the narrow top gap to catch the device’s edges during automated pick-and-place operations, thus yielding expected predictable results (KSR).
Regarding dependent claim 21, Akram, teaches:
The method of claim 20 ([Abstract], [0003], [0012], [0022]-[0024], [0051]-[0053], [0059], [0062], [0064] & [0090]),
Akram, in combination with Sugano, and Lee, are silent in regard to:
wherein the first width is approximately a width of the semiconductor device.
However, Parrish, further teaches:
wherein the first width is approximately a width of the semiconductor device (Fig. 1c; [Abstract], [I. Introduction, page 1] & [II. Sensitive Device Surfaces, C. Die Sorting, pp. 2-3]: teaches dimensional sizing of the collet to match the die to achieve edge contact. Teaches utilizing a collet where “only the top edges of the device are contacted rather than the top surface”. To physically achieve this edge-only contact, the narrowest gap between the chamfered surfaces (the first width at the first end) must inherently be approximately equal to the width of the semiconductor device. If the first width were significantly smaller, the device would not fit into the cavity. Therefore, sizing the collet to approximately the width of the specific die is a structural requirement).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the testing apparatus of Akram to incorporate the mutual mechanical alignment system taught by Sugano, while utilizing the inverted pyramid collet of Parrish as the first alignment member to securely hold the encapsulated semiconductor device of Lee, according to known methods. The sizing of the “inverted pyramid collet” taught by Parrish, so that its upper, narrower gap (the first width) is approximately the width of the semiconductor device is an inherent structural necessity to achieve the stated function. As taught by Parrish, the tool must be configured so that “only the top edges of the device are contacted rather than the top surface.” A POSITA would find it obvious to dimension the first width of the collet’s cavity to be approximately equal to the width of the semiconductor device being testing, as failing to do so would result in either the device failing to fit into the tool or the tool failing to grip the edges and damage the protected top surface, thus yielding expected predictable results (KSR).
Claims 3-4, 6-9, 14-15, & 17 are rejected under 35 U.S.C. 103 as being unpatentable over Akram, in view of Akram et al. (US 2001/0000650A1, Pub. Date May 3, 2001, hereinafter Akram’650), in view of Sugano, in view of Lee, and further in view of Parrish.
Regarding dependent claim 3, Akram, teaches:
The method of claim 1 ([Abstract], [0003], [0012], [0022]-[0024], [0051]-[0053], [0064], [0080] & [0093]), wherein the first and second alignment members ([0011]-[0012], [0051]-[0053] & [0093]
Akram, is silent in regard to:
have complementary mating formations wherein the first and second alignment members are mutually aligned via the complementary mating formations.
However, Akram’650, further teaches:
have complementary mating formations (Figs. 17A-17C; [0008] & [0127]-[0129]) wherein the first and second alignment members are mutually aligned via the complementary mating formations (Figs. 17A-17C; [0008] & [0127]-[0129]).
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It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate complementary mating formations wherein the first and second alignment members are mutually aligned via the complementary mating formations, of Akram’650 to Akram, according to known methods. In order to attain and improve the alignment between the interconnect/interposer and the base/test substrate, where Akram’650 identifies mechanical alignment techniques to complex optical systems, disclosing an assembly fixture 146 to align the interconnect 16E to the base 24E, alignment relies on complementary mating features such as alignment pins 154 that mate with corresponding pockets 156 in the base. This is an example of using complementary formations to mutually align two components of a test system, and therefore would be obvious for a POSITA to integrate the mechanical pin-and-pocket alignment of Akram’650 to ensure precise alignment required for the interposer 100 and test substrate of Akram, where the combination uses a known technique from a related field (semiconductor test system assembly) to solve the alignment problem, yielding expected results (KSR).
Regarding dependent claim 4, Akram, teaches:
The method of claim 3 ([Abstract], [0003], [0012], [0022]-[0023], [0051]-[0053], [0064], [0080] & [0093]),
Akram, is silent in regard to:
wherein the complementary mating formations include complementary mating cavities and protrusions carried by the first and second alignment members.
However, Akram’650, further teaches:
wherein the complementary mating formations include complementary mating cavities and protrusions carried by the first and second alignment members (Figs. 17A-17C; [0008], [0090], [0094], & [0127]-[0129]: assembly fixture 146 is used to align the interconnect 16E on the base 24E (second member), the base 24E is shown to have pockets 156 (cavities) that mate with alignment pins 154 (protrusions) carried by the assembly fixture 146, where the alignment pins 154 and pockets 156 provide precise positioning of the interconnect 16E on the base 24E).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate complementary mating formations that include complementary mating cavities and protrusions carried by the first and second alignment members, of Akram’650 to Akram, in order to attain and improve the alignment between the interconnect/interposer (first member) and the base/test substrate (second member), where Akram’650 teaches a method for achieving precise alignment in a semiconductor test system assembly with a standard mechanical solution, disclosing alignment pins 154 (protrusions) mating with pockets 156 (cavities) on the base 24E (second member), where this pin-and-pocket system is an example of complementary mating cavities and protrusions, therefore is obvious for a POSITA to integrate the aligned pin-and-pocket mechanism of Akram’650 to ensure precise alignment required between the interposer and test substrate of Akram, where the combination uses a known technique from a related field (semiconductor test system assembly) to solve the precise alignment problem, via cavities and protrusions, yielding expected results (KSR).
Regarding independent claim 6, Akram, teaches:
An apparatus ([Abstract], [0003], [0012], [0022]-[0024], & [0051]-[0053]), comprising:
Akram, in combination with Akram’650, Sugano, and Parrish, are silent in regard to:
a semiconductor device having a first surface and a protected second surface, the first surface including an array of electrically conductive pins;
However, Akram, in combination with Lee, further teach:
a semiconductor device having a first surface (Akram: Figs. 1 & 3; [Abstract], [0003], [0012], [0022]-[0024], [0049], [0051]-[0053], [0059]-[0063] & [Claim 4]) and a protected second surface (Disclosed in combination: Akram: Figs. 1 & 3; [Abstract], [0003], [0009]-[0010], [0012], [0022]-[0024], [0049], [0051]-[0053], [0059]-[0063] & [Claim 4]; Lee: [Abstract], [0027]-[0028], [0038], [0048]-[0049], [0052], [0060], [0063]-[0069], [Claim 1], [Claim 4] & [Claim 18]: teaches the protected second surface on a semiconductor device comprising a protective layer (insulating encapsulation) that encapsulates the chip), the first surface including an array of electrically conductive pins (Akram: Figs. 1 & 3; [0009]-[0010], [0022]-[0024], [0049], [0051]-[0053], [0059]-[0063] & [Claim 4]: teaches a semiconductor device 150 with a first surface having an array of conductive structures 152 (which are disclosed as being configurable as “conductive pillars” equivalent to pins));
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to further modify the semiconductor device undergoing the testing and alignment method of Akram and Sugano to comprise the insulating encapsulation (protection layer) covering the surfaces opposite the active contacts, as taught by Lee, according to known methods. The motivation to do so would be to physically protect the fragile semiconductor chip from mechanical stress, chipping, or environmental damage during the automated handling, physical clamping, and alignment processes executed by Akram’s testing fixtures. As taught by Lee, providing this encapsulation ensures the structural integrity of the device is maintained before, during, and after testing operations, thus yielding expected predictable results (KSR).
Akram, in combination with Akram’650, Sugano, and Lee, are silent in regard to:
a first alignment member aligned with the semiconductor device in response to the protected second surface of the semiconductor device being exposed to first and second chamfered surfaces in the first alignment member, a gap between the first and second chamfered surfaces being narrower at a first end of the first alignment member than at a second end of the first alignment member;
However, Parrish, further teaches:
a first alignment member aligned with the semiconductor device in response to the protected second surface of the semiconductor device being exposed to first and second chamfered surfaces in the first alignment member, a gap between the first and second chamfered surfaces being narrower at a first end of the first alignment member than at a second end of the first alignment member (Fig. 1c; [Abstract], [I. Introduction, page 1] & [II. Sensitive Device Surfaces, C. Die Sorting, pp. 2-3]: teaches the first alignment member (collect) having the exact inverted geometry, discloses an “inverted pyramid style collect”. The inverted pyramid geometry structurally requires that the gap between the opposing chamfered/slanted surfaces is narrower at the top/ceiling (first end) than at the bottom opening (second end), further states this exposes the protected top surface to the cavity without touching it ”…only the top edges of the device are contacted rather than the top surface”);
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor testing method of Akram to incorporate the mutual mechanical alignment system (the first and second alignment members) taught by Sugano, further modifying the semiconductor device to include the insulating encapsulation taught by Lee, and further modifying the first alignment member to utilize the inverted pyramid collet geometry taught by Parish, according to known methods. The motivation to combine Akram and Sugano would be to provide a mechanical guide system that forces accurate physical alignment between the holding member and the socket prior to electrical engagement, preventing pin damage and ensuring reliable contact. The motivation to further incorporate Lee would be to protect the fragile semiconductor chip during the automated handling and testing operations by encapsulating the surfaces opposite the contacts with a protective insulating layer. Finally, the motivation to incorporate the inverted pyramid collet of Parish as the first alignment member would be to provide an automated robotic handling mechanism that can securely catch, hold, and mutually align the semiconductor device by its edges, ensuring that “only the top edges of the device are contacted rather than the top surface” to prevent damage to the handling tool from physically touching, scratching, damaging, or compromising the protected encapsulation layer (second layer) of the device during the mutual alignment process of the chip and during testing operations, as taught by Parrish, thus yielding predictable results (KSR).
Akram, in combination with Akram’650, are silent in regard to:
a second alignment member aligned with the array of electrically conductive pins, the second end of the first alignment member being coupled to the second alignment member; and
alignment formation aligned with the first alignment member with the second alignment member, wherein the array of electrical formations is aligned with respect to the array of electrically conductive pins in response to the first and second alignment members being mutually aligned.
However, Sugano, further teaches:
a second alignment member aligned with the array of electrically conductive pins, the second end of the first alignment member being coupled to the second alignment member (Fig. 7; [0054] & [0056]: teaches a second alignment member (test socket 112) configured to align with the device’s conductive arrays, further teaches coupling the lower interface (second end) of the housing/collet to the test socket); and
alignment formation aligned with the first alignment member with the second alignment member (Fig. 7; [0054] & [0056]: teaches alignment formations used to mutually align the two members, where the guide holes 533 and guide pins 114 constitute the “alignment formation”), wherein the array of electrical formations is aligned with respect to the array of electrically conductive pins in response to the first and second alignment members being mutually aligned (Fig. 7; [0054] & [0056]: teaches that mutual alignment of macroscopic members forces the alignment of the microscopic electrical arrays).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor testing apparatus of Akram to incorporate the mutual mechanical alignment system (the first alignment member, the second alignment member, and the mating alignment formations) as taught by Sugano, according to known methods. The motivation to do so would be to provide a mechanical guide system (such as guide pins and mating holes) that forces the accurate, mutual physical alignment between the device holding member and the test socket prior to electrical engagement. As taught by Sugano, forcing the mutual alignment of these macroscopic members ensures that the microscopic electrical contact arrays on the device are accurately coupled, preventing misalignment, reducing the risk of crushing or damaging the conductive pins during automated testing operations, improving overall test yield and reliability, thus yielding expected predictable results (KSR).
Regarding dependent claim 7, Akram, teaches:
The apparatus of claim 6 ([Abstract], [0003], [0012], [0022]-[0024] & [0051]-[0053]), wherein:
Akram, in combination with Akram’650, Sugano, and Lee, are silent in regard to:
the apparatus includes a picking tool configured to advance the semiconductor device with respect to the first and second chamfered surfaces with the protected second surface exposed to the first and second chamfered surfaces.
However, Parrish, further teaches:
the apparatus includes a picking tool configured to advance the semiconductor device with respect to the first and second chamfered surfaces (Fig. 1c; [Abstract], [I. Introduction, page 1] & [II. Sensitive Device Surfaces, C. Die Sorting, pp. 2-3]: teaches the inclusion of a picking tool, refers to the first alignment member as a “pick-up tool” used during the “die pick process”. During the automatic pick-and-place operation, relative motion is created between the die and the tool. The die advances into the chamfered cavity of the ”inverted pyramid style collect” until the slanted walls grip the edges of the device) with the protected second surface exposed to the first and second chamfered surfaces (Fig. 1c; [Abstract], [I. Introduction, page 1] & [II. Sensitive Device Surfaces, C. Die Sorting, pp. 2-3]: teaches that the configuration of the inverted picking tool leaves the protected surface exposed to the chamfered cavity walls rather than touching it, “…a collet-style pick-up tool approach can be used where only the top edges of the device are contacted rather than the top surface”. This ensures the protected second surface (from Lee) remains safely exposed within the chamfered cavity as the tool advances over it).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the testing apparatus of Akram and Sugano to utilize the inverted pyramid collet of Parrish to securely hold the encapsulated semiconductor device of Lee, according to known methods. The inverted pyramid collet, taught by Parrish, is disclosed as a “pick-up tool” (i.e., a picking tool) used in automated die sorting and handing operations. Utilizing this automated picking tool inherently configures the apparatus to advance the semiconductor device relative to the chamfered inner surfaces of the tool’s cavity. As intended by Parrish, this advancement is controlled such that “only the top edges of the device are contacted rather than the top surface”, leaving the protected second surface safely exposed to the first and second chamfered surfaces without making damaging physical contact, yielded expected predictable results (KSR).
Regarding dependent claim 8, Akram, teaches:
The apparatus of claim 6 ([Abstract], [0003], [0012], [0022]-[0024] & [0051]-[0053]), wherein the first and second alignment members ([0011]-[0012], [0051]-[0053] & [0093])
Akram, is silent in regard to:
have complementary mating formations wherein the first and second alignment members are mutually aligned in response to the complementary mating formations being mutually engaged.
However, Akram’650, further teaches:
have complementary mating formations (Figs. 17A-17C; [0008] & [0127]-[0129]) wherein the first and second alignment members are mutually aligned in response to the complementary mating formations being mutually engaged (Figs. 17A-17C; [0008] & [0127]-[0129]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate complementary mating formations wherein the first and second alignment members are mutually aligned in response to the complementary mating formations being mutually engaged, of Akram’650 to Akram, according to known methods. In order to attain and improve the alignment between the interconnect/interposer and the base/test substrate, Akram establishes the need for the interposer and test substrate to be aligned precisely, Akram’650 teaches a mechanical alignment apparatus that uses mutual engagement and protrusions (pins 154) and cavities (pockets 156) to achieve the precise alignment of the interconnect 16E on the base 24E, an example of using complementary formations to mutually align two components of a test system. Therefore would be obvious for a POSITA to integrate the mechanical pin-and-pocket alignment of Akram’650 to ensure precise alignment required for the interposer 100 and test substrate of Akram, where the combination uses a known technique from a related field (semiconductor test system assembly) to solve the alignment problem, yielding expected results (KSR).
Regarding dependent claim 9, Akram, teaches:
The apparatus of claim 8 [Abstract], [0003], [0012], [0022]-[0024], & [0051]-[0053], [0064], [0080], & [0093]),
Akram, is silent in regard to:
wherein the complementary mating formations include complementary mating cavities and protrusions carried by the first and second alignment members.
However, Akram’650, further teaches:
wherein the complementary mating formations include complementary mating cavities and protrusions carried by the first and second alignment members (Figs. 17A-17C; [0008], [0090], [0094] & [0127]-[0129]: assembly fixture 146 is used to align the interconnect 16E on the base 24E (second member), the base 24E is shown to have pockets 156 (cavities) that mate with alignment pins 154 (protrusions) carried by the assembly fixture 146, where the alignment pins 154 and pockets 156 provide precise positioning of the interconnect 16E on the base 24E).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate complementary mating formations that include complementary mating cavities and protrusions carried by the first and second alignment members, of Akram’650 to Akram, according to known methods. In order to attain and improve the alignment between the interconnect/interposer (first member) and the base/test substrate (second member), where Akram’650 teaches a method for achieving precise alignment in a semiconductor test system assembly with a standard mechanical solution, disclosing alignment pins 154 (protrusions) mating with pockets 156 (cavities) on the base 24E (second member), where this pin-and-pocket system is an example of complementary mating cavities and protrusions. Therefore would be obvious for a POSITA to integrate the aligned pin-and-pocket mechanism of Akram’650 to ensure precise alignment required between the interposer and test substrate of Akram, where the combination uses a known technique from a related field (semiconductor test system assembly) to solve the precise alignment problem, via cavities and protrusions, yielding expected results (KSR).
Regarding dependent claim 14, Akram, teaches:
The method of claim 10 ([Abstract], [0003], [0012], [0022]-[0024], [0051]-[0053], [0059], [0062], [0064], [0080], [0090] & [0093]), wherein the first and second alignment members ([0011]-[0012], [0051]-[0053] & [0093])
Akram, is silent in regard to:
have complementary mating formations wherein the first and second alignment members are mutually aligned via the complementary mating formations.
However, Akram’650, further teaches:
have complementary mating formations (Figs. 17A-17C; [0008] & [0127]-[0129]) wherein the first and second alignment members are mutually aligned via the complementary mating formations (Figs. 17A-17C; [0008] & [0127]-[0129]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate complementary mating formations wherein the first and second alignment members are mutually aligned via the complementary mating formations, of Akram’650 to Akram, according to known methods. In order to attain and improve the alignment between the interconnect/interposer and the base/test substrate, where Akram’650 identifies mechanical alignment techniques to complex optical systems, disclosing an assembly fixture 146 to align the interconnect 16E to the base 24E, alignment relies on complementary mating features such as alignment pins 154 that mate with corresponding pockets 156 in the base, an example of using complementary formations to mutually align two components of a test system. Therefore would be obvious for a POSITA to integrate the mechanical pin-and-pocket alignment of Akram’650 to ensure precise alignment required for the interposer 100 and test substrate of Akram, where the combination uses a known technique from a related field (semiconductor test system assembly) to solve the alignment problem, yielding expected results (KSR).
Regarding dependent claim 15, Akram, teaches:
The method of claim 14 ([Abstract], [0003], [0012], [0022]-[0024], [0051]-[0053], [0059], [0062], [0064], [0080], [0090] & [0093]),
Akram, is silent in regard to:
wherein the complementary mating formations include complementary mating cavities and protrusions carried by the first and second alignment members.
However, Akram’650, further teaches:
wherein the complementary mating formations include complementary mating cavities and protrusions carried by the first and second alignment members (Figs. 17A-17C; [0008], [0090], [0094], & [0127]-[0129]: assembly fixture 146 is used to align the interconnect 16E on the base 24E (second member), the base 24E is shown to have pockets 156 (cavities) that mate with alignment pins 154 (protrusions) carried by the assembly fixture 146, where the alignment pins 154 and pockets 156 provide precise positioning of the interconnect 16E on the base 24E).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate complementary mating formations that include complementary mating cavities and protrusions carried by the first and second alignment members, of Akram’650 to Akram, according to known methods. In order to attain and improve the alignment between the interconnect/interposer (first member) and the base/test substrate (second member), where Akram’650 teaches a method for achieving precise alignment in a semiconductor test system assembly with a standard mechanical solution, disclosing alignment pins 154 (protrusions) mating with pockets 156 (cavities) on the base 24E (second member), where this pin-and-pocket system is an example of complementary mating cavities and protrusions. Therefore would be obvious for a POSITA to integrate the aligned pin-and-pocket mechanism of Akram’650 to ensure precise alignment required between the interposer and test substrate of Akram, where the combination uses a known technique from a related field (semiconductor test system assembly) to solve the precise alignment problem, via cavities and protrusions, yielding expected results (KSR).
Regarding dependent claim 17, Akram, teaches:
The method of claim 10 ([Abstract], [0003], [0012], [0022]-[0024], [0051]-[0053], [0059], [0062], [0064], [0080], [0090] & [0093]) wherein the second alignment member includes ([0051]-[0053]: fence 120 disposed on the substrate)
Akram, in combination , Akram’650, are silent in regard to:
a plurality of protrusions facing and configured to interact and align with the plurality of cavities.
However, Sugano, further teaches
a plurality of protrusions facing and configured to interact and align with the plurality of cavities (Figs. 6-7; [0054] & [0056]: teaches the second alignment member (test socket 112) having protrusions (guide pins 114) that face and insert into cavities (guide holes 533)).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the testing apparatus of Akram to incorporate the mutual mechanical alignment system taught by Sugano, according to known methods. Sugano teaches the specific structural configuration of this alignment mechanism. As detailed in Sugano ([0054] and Figs. 6-7), the test socket (second alignment member) includes guide pins (protrusions) that face and are configured to insert into and interact with corresponding guide holes (cavities) formed on the mating surface of the holding tool. Utilizing this specific protrusion-and-cavity mating arrangement would have been obvious to a POSITA to ensure constrained, repeatable, and secure physical alignment between the two members prior to electrical engagement, thus yielding expected predictable results (KSR).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to HUGO NAVARRO whose telephone number is (571)272-6122. The examiner can normally be reached Monday-Friday 08:30-5:00 pm EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Eman Alkafawi can be reached at 571-272-4448. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/HUGO NAVARRO/ Examiner, Art Unit 2858 April 12, 2026
/EMAN A ALKAFAWI/Supervisory Patent Examiner, Art Unit 2858 4/17/2026
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