DETAILED ACTION
Notice of Pre-AIA or AIA Status
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 02/05/2026 has been entered.
Response to Arguments
Applicant's arguments, filed 12/18/2025, have been fully considered but they are not persuasive.
First of all, the argument attempts to narrow the interpretation of "computing device" in Gulati-1, but the specification of Gulati-1 is broad enough to encompass the claimed "shader engines of a parallel processor." For instance, Gulati-1 explicitly defines a "computing device" as including "display sub-systems" and "vehicle display systems or subsystems" (Gulati-1, para. [0022]). This directly corresponds to the "display system" recited in the claim. Furthermore, Gulati-1 identifies a GPU as the processor. The specification states that the processor "may include or be coupled to a digital signal processor or a graphics processing unit (GPU) that generates or processes images for display by a display device" (Gulati-1, para. [0041]). Moreover, a GPU is the quintessential example of a "parallel processor." It is well-known in the art that a GPU operates in parallel and contains multiple "shader engines" (also known as shader cores or streaming multiprocessors) to perform its graphics and compute operations. Besides, Gulati-1 teaches that this processor (the GPU) performs the ICV calculations. The method of Gulati-1 involves a processor "determining integrity check values for each display region of interest" based on an image (Gulati-1, claim 1, para. [0075]-[0076]). Since the processor can be a GPU, and a GPU performs operations via its shader engines, it is inherent and obvious that the "error checking" of the ROIs is performed "at one or more shader engines of" that GPU.
Therefore, Gulati-1 discloses the concept of a display system where a parallel processor (a GPU) performs error checking on a configurable number of ROIs. A person of ordinary skill in the art reading Gulati-1 would understand that this error-checking operation is executed by the fundamental processing units of that parallel processor, the shader engines.
Second of all, the argument also challenges the recitation of "transmitting the frame to a display controller of the display system for display." However, Gulati-1 explicitly discloses this step. For instance, Gulati-1 states that in response to a successful integrity check, the computing device will "output the processed image" (Gulati-1, para. [0077]). This output step is further defined as "sending the processed image to a display for rendering" or "providing the processed image to another computing device, such as another SoC" (Gulati-1, para. [0077]).Sending an image "to a display for rendering" inherently involves transmitting it to a display controller, which is the interface between the main processing system (SoC) and the display panel itself. And Gulati-1 further reinforces this by describing an embodiment where a second SoC (115) is placed between the first SoC and the display to perform a final data integrity check, confirming that the transmission path includes a display controller (Gulati-1, para. [0050], [0096]).
Finally, the argument attempts to isolate the features of each reference, but the combination is straightforward. As an illustration, Gulati-2 provides the context of a safety-critical display system and the concept of using a software model of the display processor to generate a reference check value (Gulati-2, Abstract, [0057]). Further, Gulati-1 provides the mechanism for dynamically verifying different sets of ROIs using a parallel processor. Therefore, it would have been obvious to a skilled artisan to implement the ROI integrity verification method of Gulati-1 within the safety-critical display system framework of Gulati-2. In doing so, the processor performing the verification in Gulati-1 would necessarily be the type of processor (including a GPU) found in the Gulati-2 system. Consequently, the error checking would naturally be performed by the shader engines of that GPU.
Thus, Gulati-1 explicitly discloses a display system that uses a processor (which can be a GPU) to perform error checking on regions of interest. Gulati-2 discloses a similar safety-critical display system. The combination of these references teaches or suggests every limitation of the challenged claims, including error checking by the shader engines of a parallel processor and the transmission of the frame to a display controller. The arguments presented do not establish a patentable distinction over the combined teachings of Gulati-1 and Gulati-2.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-4, 8-11, 15-17 are rejected under 35 U.S.C. 103 as being unpatentable over Gulati et al (US 2018/0165814 A1), hereinafter D2 and further in view of Gulati et al (US 2020/0198466 A1), hereinafter D1,
Claim 1: D2 teaches a method comprising:
error checking (e.g. D2 teaches error checking on regions of interest (ROIs) using a processor (3) and display processor (10) that calculate and compare data integrity check values. See para [0057], [0060]-[0061], Claim 1) a configurable number of regions of interest of a frame (e.g. D2 teaches "one or more regions-of-interest (ROI)" that are "user-configurable" and may be grouped in different ways. See para [0051], [0068]-[0072], FIGS. 5-6. The ROIs are defined for safety-critical image areas such as tell-tale icons in an instrument cluster. See para [0068]-[0071]);
and transmitting the frame to a display controller of the display system for display (e.g. D2 includes a "display interface controller (23)" configured to send images processed by the display processor to a display. See para [0064]. The processed image is output to display device (12) via the display interface controller. See para [0050], [0064]).
Not explicitly taught by D2 is the specific location of error checking at "shader engines of a parallel processor." D2 describes a processor (3) that may be a CPU and a separate display processor (10) with hardware blocks (buffer logic, fetch logic, source pipes, layer mixer, DSPP) ([0041], [0045]-[0050]). And D1 explicitly discloses that the processor may be coupled to a graphics processing unit (GPU) that generates or processes images for display ([0041]). A GPU is a well-known parallel processor, and its image processing operations, including error checking, are inherently performed by its fundamental processing units, which are commonly referred to as shader engines (also known as shader cores or streaming multiprocessors). D1 further teaches that this processor determines integrity check values for ROIs ([0075]-[0076], Claim 1).
Therefore, a POSITA, before the effective filing date of the claimed invention, would have been motivated to combine the teachings of D2 and D1 for the following reasons:
D2 teaches a robust method for error checking ROIs to ensure data content integrity in safety-critical display systems (Abstract, [0057]). However, D2 does not specify that the error checking is performed by a GPU. D1 explicitly teaches that a processor for image processing may be coupled to a graphics processing unit (GPU) that generates or processes images for display ([0041]). GPUs are well-known parallel processors commonly integrated into system-on-chip (SoC) designs for vehicles to handle graphics-intensive tasks efficiently. A skilled artisan would recognize that implementing the error-checking functions of D2 on a GPU's shader engines would leverage existing hardware capabilities, improve processing efficiency, and reduce the burden on the main CPU. The motivation is to achieve optimal performance by distributing processing tasks to the most suitable hardware components.
D2 broadly teaches error checking at a "processor" but does not detail the internal architecture of that processor. D1 fills this gap by teaching the use of a GPU for image processing tasks ([0041]). It is axiomatic in the art that a GPU operates in parallel and performs its operations via its fundamental processing units, commonly referred to as shader engines, shader cores, or streaming multiprocessors. These units execute the pixel shaders, vertex shaders, and compute kernels that process image data. Therefore, when D1 teaches that a GPU "determines integrity check values for each display region of interest" ([0075]), a person of ordinary skill would understand that this determination is performed by the shader engines of that GPU. The combination of D2's error-checking method with D1's explicit disclosure of a GPU processor inherently results in error checking being performed "at one or more shader engines of a parallel processor."
D2 already teaches the essential components of a display processing system: configurable ROIs, error checking via integrity check values, a layer mixer for blending images, and a display interface controller for transmission to a display ([0045]-[0050], [0057], [0064]). D1 provides the specific implementation of a GPU as the processor that performs the integrity check value calculations ([0041], [0075]). Combining these references would have been a straightforward matter of applying known techniques (error checking using a GPU's shader engines) to a known system (D2's display subsystem) to yield predictable results, an integrated display system capable of efficient, hardware-accelerated error checking on user-configurable ROIs.
The combination of D2 and D1 amounts to no more than substituting the generic processor in D2 with a GPU (parallel processor) as taught by D1 to perform the same error-checking function. This is a simple substitution of one known element for another to obtain predictable results, which is a classic rationale for obviousness under MPEP 2143.
As per claim 8, the claimed features are rejected similarly to claim 1 above.
Claim 2: D1 and D2 teach the method of claim 1, further comprising:
overlaying, at the parallel processor, the regions of interest on a dynamic background to generate a blended image (e.g. D2 includes a "layer mixer (20)" configured to perform "blending and mixing of the image with one or more other surfaces". See para [0048]. The layer mixer receives an image from source pipes and can layer a frame (e.g., from a video source) with "one or more surfaces that include a graphical trajectory lines... GUI menu options, and the like". See para [0048]. This constitutes overlaying graphics (which can include safety-critical ROIs) onto a dynamic background image to generate a blended/mixed image. See para [0048]. Also D1 supports this concept by discussing composite images formed from different sources and combined before display. See para [0039]);
and inputting the blended image to a single display pipe of the display controller (e.g. D2's display subsystem pipeline (11) processes the blended image through subsequent blocks (e.g., DSPP 22) and the display interface controller (23) before sending it to the display. See para [0050] and [0064]. The display interface controller (23) and the overall display subsystem pipeline (11) constitute a "single display pipe", a dedicated processing and transmission path for the final composed image.
As per claim 9 the claimed features are rejected similarly to claim 2 above.
Claim 3: D1 and D2 teach the method of claim 1, wherein error checking comprises: performing, at a GPU engine of the parallel processor, a first data integrity check on each of the regions of interest (e.g. [0076]- D1). D1 teaches, in paragraph [0023], that “The SOC may include a variety of different types of processors and processor cores, such as a general purpose processor, a central processing unit (CPU), a digital signal processor (DSP), a graphics processing unit (GPU), an accelerated processing unit (APU), a sub-system processor, an auxiliary processor, a single-core processor, and a multicore processor.” However, D1 and D2 fail to teach that the processor is a shader engine. Nevertheless, it is well known in the art that shader engines are specialized processing units within a GPU architecture that are capable of executing operations efficiently, particularly for image, video, and pixel-level computing. Therefore, it would have been obvious to a person of ordinary skill in the art, before the effective filing date of the claimed invention, to use any type of graphic processing unit, such as a shader engine, in the teaching of D1 and D2, since such a modification would have involved substituting a known component for another to yield predictable results.
As per claim 10, the claimed features are rejected similarly to claim 3 above.
As per claim 15, the claimed features are rejected similarly to claim 3 above.
Claim 4: D1 and D2 teach the method of claim 3, wherein performing the first data integrity check comprises: calculating a first cyclic redundancy check (CRC) value for each of the regions of interest (e.g. [0075]- D1); and comparing, at an external component of the display system, the first CRC value to a reference value (e.g. [0076]- D1).
As per claims 11 and 17, the claimed features are rejected similarly to claim 4 above.
Claim 16: D1 and D2 teach the method of claim 15, wherein the parallel processor is further configured to: overlaying the regions of interest on a dynamic background (e.g. [0066] & figs. 4A & 4B, D1).
Claim(s) 6, 7, 13, 14, 19 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over D1 and D2 as applied to claim 1 above, and further in view of Hardacker et al (US 2019/0181982 A1), hereinafter D3.
Claim 6: D1 and D2 teach the method of claim 1, but fail to teach transmitting the frame from the display controller to a display via a serializer/deserializer. However, such a technique was known in the art, before the effective filing date of the claimed invention, as disclosed by D3 (e.g. [0028]). Therefore, it would have been obvious to a person of ordinary skill in the art, before the effective filing date of the claimed invention, to incorporate the SERDES-based transmission system disclosed by D3 into the system taught by D1 and D2 in order to improve data efficiency and to support higher display resolutions.
As per claims 13 and 19, the claimed features are rejected similarly to claim 6 above.
Claim 7: D1, D2 and D3 teach the method of claim 6, further comprising: calculating, at the serializer/deserializer, a cyclic redundancy check (CRC) value for each of the regions of interest (e.g. [0028]- D3); and sending the CRC value to an external component of the display system for comparison to a reference value (e.g. [0028]- D3).
As per claims 14 and 20, the claimed features are rejected similarly to claim 7 above.
Allowable Subject Matter
Claims 5, 12 and 18 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
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/GUERRIER MERANT/Primary Examiner, Art Unit 2111 2/18/2026