DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
An amendment responsive to the non-final Office Action dated May 19, 2026 was submitted on July 23, 2026. Claims 1, 6, 11, 18 and 19 were amended. Claims 1-20 are currently pending.
The amendments to claims 1 and 11 have overcome the prior art rejections of claims 1-18 (¶¶ 6-29 of the Office Action). These rejections have therefore been withdrawn. However, upon further consideration, new grounds of rejection of these claims have been made as detailed below.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1-10 are rejected under 35 U.S.C. 103 as being unpatentable over Harris et al. (U.S. Patent Application Publication No. 2022/0262652 A1, cited in IDS submitted May 31, 2024) in view of Mitsuishi et al. (Japanese Patent Publication No. JP 2010-207908 A, machine language translation provided in previous Office Action and cited below), Wang et al. (U.S. Patent Application Publication No. 2020/0371046 A1, cited in previous Office Action) and either of Pan et al. (Chinese Patent Publication No. CN 103091277 A, machine language translation provided in previous Office Action and cited below) or Hawthorne et al. (U.S. Patent Application Publication No. 2008/0217530 A1).
Regarding claim 1, Harris discloses an integrated bonder system for processing a substrate (Abstract of Harris, multi-chamber processing tool for bonding substrates; FIG. 1 of Harris, separate components of tool are combined or integrated together to form the tool), the system comprising: a mainframe comprising a substrate handling system (Abstract, Title of Harris, modular mainframe layout; [0024] of Harris, tool comprises a robot for handling the substrates); a bonder chamber connected to the mainframe (FIG. 1, [0040] of Harris, tool includes a bonder chamber #140); a metrology chamber connected to the mainframe (FIG. 1, [0040] of Harris, tool includes a metrology chamber #118); and a controller connected to the mainframe (FIG. 1, [0041] of Harris, tool includes a controller #180).
Harris does not specifically disclose that: the metrology chamber is configured to measure a characteristic of a surface of the substrate; and that the controller is configured to receive a measurement of the characteristic and determine whether the surface is suitable for bonding in the bonder chamber based at least on the measurement. Moreover, Harris discloses that the controller enables data collection and feedback from the multi-chamber processing tool to optimize performance ([0041] of Harris) but does not specifically the details of the controller configuration. Mitsuishi, however, discloses a method for bonding semiconductor substrates comprising activating the bonding surfaces of the substrates, measuring the surface roughness of the substrates, and bonding the substrates, wherein the process is changed based on the surface roughness measurement ([0006] of Mitsuishi). According to Mitsuishi, if the measured surface roughness is above a predetermined value, the substrate is returned to the beginning of the bonding process for further processing ([0074]-[0075] of Mitsuishi, bonding prohibited and process starts again if measured roughness above predetermined value). Also according to Mitsuishi, surface roughness values below the predetermined value are suitable for achieving bonding whereas surface roughness values above the predetermined value are not suitable for achieving bonding ([0072] of Mitsuishi). It would have been obvious to a person having ordinary skill in the art as of the effective filing date of the claimed invention to configure the controller to receive a measurement of the characteristic and determine whether the surface is suitable for bonding in the bonder chamber based at least on the measurement. One of skill in the art would have been motivated to do so in order to ensure that the surface roughness conditions are suitable for achieving bonding of the substrates as taught by Mitsuishi ([0072] of Mitsuishi).
Harris also does not specifically disclose that the characteristic includes a surface chemical measurement. Harris, however, discloses that the processing tool may include one or more metrology chambers configured to take measurements of the substrates ([0040] of Harris). Wang discloses that contamination present on the bonding surfaces of the wafers can prevent proper bonding of the wafers during a wafer bonding process ([0045] of Wang). Pan discloses a method for detecting surface contamination (i.e., a surface chemical measurement) on a wafer using infrared transmission (Abstract of Pan). Hawthorne discloses a semiconductor inspection system for identifying contamination on the surface of a silicon wafer (Abstract of Hawthorne). It would have been obvious to a person having ordinary skill in the art as of the effective filing date of the claimed invention identify contaminants on the bonding surfaces of the wafers in the modified system. One of skill in the art would have been motivated to do so in order to detect contaminants that would interfere with bonding as taught by Wang and either of Pan or Hawthorne.
Regarding claim 2, Mitsuishi discloses that the characteristic includes at least one of surface potential, contact angle, hydrophobicity, cleanliness, surface functionalization, bond surface dishing, or roughness ([0006] of Mitsuishi, surface roughness measured; claim only requires one of the recited characteristics).
Regarding claim 3, Mitsuishi discloses that the metrology chamber includes at least one of an atomic force microscope or an infrared spectrometer configured to measure the characteristic ([0060] of Mitsuishi, surface roughness measuring instrument may be an atomic force microscope; claim only requires one of the recited metrology tools).
Regarding claim 4, Mitsuishi discloses that the metrology chamber is configured to obtain measurements of the characteristic by at least one of: Raman spectroscopy, AFM profiling, AFM-IR spectroscopy, Fourier transform, KPFM, phase angle mapping, or adhesion mapping ([0060] of Mitsuishi, surface roughness measuring instrument may be an atomic force microscope; metrology chamber would therefore be configured to obtain measurements by AFM profiling; claim only requires one of the recited measurement types).
Regarding claim 5, Mitsuishi discloses that the metrology chamber is configured to measure the characteristic without contacting the substrate ([0062] of Mitsuishi, surface roughness measured using laser; laser is a non-contact imaging device).
Regarding claim 6, Mitsuishi discloses that the characteristic includes at least one of dimensional measurements or surface chemical measurements ([0006] of Mitsuishi, surface roughness measured; surface roughness is a dimensional characteristics of the surface).
Regarding claim 7, Harris discloses the system further comprising a process chamber configured to activate the surface of the substrate for bonding in the bonder chamber ([0033] of Harris, system can include a plasma chamber).
Regarding claim 8, Harris discloses that the process chamber includes a plasma chamber connected to the mainframe (FIG. 1 of Harris, plasma chambers #130a #130b).
Regarding claim 9, Harris discloses that the process chamber includes a wet clean chamber connected to the mainframe (FIG. 1, [0033] of Harris, wet clean chamber #122a #122b).
Regarding claim 10, Harris discloses that the mainframe is configured to transport the substrate to the process chamber before the metrology chamber, wherein the measured surface is activated (FIG. 1 of Harris, plasma chambers #130a #130b located upstream of metrology chamber #118).
Claims 11-18 are rejected under 35 U.S.C. 103 as being unpatentable over Guo et al. (U.S. Patent Application Publication No. 2019/0051524 A1, cited in previous Office Action) in view of Harris, Mitsuishi, Wang and either of Pan or Hawthorne.
Regarding claim 11, Guo discloses a substrate processing method (Abstract of Guo, wafer bonding method), the method comprising: activating a substrate for bonding (Abstract of Guo, method includes performing a plasma activation treatment on surfaces of the wafers); measuring a surface characteristic of a surface of the activated substrate ([0073] of Guo, RMS of surface roughness of the polished wafer surfaces can be less than 0.5 nm; determination of the surface roughness would necessarily require measuring the roughness); determining whether the surface is suitable for bonding based at least on the measuring ([0073] of Guo, RMS of surface roughness of the polished wafer surfaces can be less than 0.5 nm); and bonding the substrate (Abstract of Guo, process involves bonding the wafers).
Guo does not specifically disclose that the substrate processing method is a method for an integrated bonder system wherein activation occurs in at least one process chamber of the integrated bonder system, wherein the surface characteristic is measured in a metrology chamber of the integrated bonder system, wherein the integrated bonder system includes a mainframe connected to the at least one process chamber, the metrology chamber, and the bonder chamber. Harris discloses a modular mainframe layout for a multi-chamber substrate processing tool (Title and Abstract of Harris). The multi chamber processing tool of Harris includes one or more plasma chambers (FIG. 1, plasma chamber #130a #130b), a metrology chamber (FIG. 1 of Harris, metrology chamber #118), and one or more bonder chambers (FIG. 1 of Harris, bonder chambers #140). According to Harris, the multi-chamber processing tool provides for expandability and higher throughput ([0002]-[0003] of Harris). It would have been obvious to a person having ordinary skill in the art as of the effective filing date of the claimed invention to conduct the wafer bonding process of Guo in the multi-chamber processing tool of Harris. One of skill in the art would have been motivated to do so in order to provide for expandability and higher throughput as taught by Harris ([0002]-[0003] of Harris).
Harris does not specifically disclose bonding the substrate in a bonder chamber of the integrated bonder system if the surface is suitable for bonding or re-activating the substrate if the surface is not suitable for bonding. Moreover, Harris discloses that the system has a controller to enable data collection and feedback from the multi-chamber processing tool to optimize performance ([0041] of Harris) but does not specifically the details of the controller configuration such as using metrology data to determine if the surface is suitable for bonding. Mitsuishi, however, discloses a method for bonding semiconductor substrates comprising activating the bonding surfaces of the substrate, measuring the surface roughness of the substrates, and bonding the substrates, wherein the process is changed based on the surface roughness measurement ([0006] of Mitsuishi). According to Mitsuishi, if the measured surface roughness is above a predetermined value, the substrate is returned to the beginning of the bonding process for further processing including a further activation step ([0074]-[0075] of Mitsuishi, bonding prohibited and process starts again if measured roughness above predetermined value). Also according to Mitsuishi, surface roughness values below the predetermined value are suitable for achieving bonding whereas surface roughness values above the predetermined value are not suitable for achieving bonding ([0072] of Mitsuishi). It would have been obvious to a person having ordinary skill in the art as of the effective filing date of the claimed invention to bond the substrate in a bonder chamber of the integrated bonder system if the surface is suitable for bonding or re-activate the substrate if the surface is not suitable for bonding in the modified method. One of skill in the art would have been motivated to do so in order to ensure that the surface roughness conditions are suitable for achieving bonding of the substrates as taught by Mitsuishi ([0072] of Mitsuishi).
Harris also does not specifically disclose that the characteristic includes a surface chemical measurement. Harris, however, discloses that the processing tool may include one or more metrology chambers configured to take measurements of the substrates ([0040] of Harris). Wang discloses that contamination present on the bonding surfaces of the wafers can prevent proper bonding of the wafers during a wafer bonding process ([0045] of Wang). Pan discloses a method for detecting surface contamination (i.e., a surface chemical measurement) on a wafer using infrared transmission (Abstract of Pan). Hawthorne discloses a semiconductor inspection system for identifying contamination on the surface of a silicon wafer (Abstract of Hawthorne). It would have been obvious to a person having ordinary skill in the art as of the effective filing date of the claimed invention identify contaminants on the bonding surfaces of the wafers in the modified process. One of skill in the art would have been motivated to do so in order to detect contaminants that would interfere with bonding as taught by Wang and either of Pan or Hawthorne.
Regarding claim 12, Mitsuishi discloses that the characteristic includes at least one of surface potential, contact angle, non-contact angle, hydrophobicity, cleanliness, surface functionalization, bond surface dishing, or roughness ([0072] of Mitsuishi, surface roughness measured).
Regarding claim 13, Mitsuishi discloses that the measuring includes at least one of Raman spectroscopy, AFM profiling, AFM-IR spectroscopy, Fourier transform, KPFM, phase angle mapping, or adhesion mapping ([0060] of Mitsuishi, atomic force microscope or AFM used to measure roughness).
Regarding claim 14, Harris discloses that activating includes performing a degas process on the substrate ([0035] of Harris, degas process performed).
Regarding claim 15, Mitsuishi discloses that activating includes performing a surface treatment process on the substrate (Abstract of Mitsuishi, joining faces of substrates activated).
Regarding claim 16, Harris discloses that activating includes performing a wet clean process on the substrate ([0034] of Harris, wet clean process performed).
Regarding claim 17, Wang and Pan suggest the method further comprising identifying contaminants on the surface. Moreover, Wang discloses that contamination present on the bonding surfaces of the wafers can prevent proper bonding of the wafers during a wafer bonding process ([0045] of Wang) and Pan discloses a method for detecting surface contamination on a wafer using infrared transmission (Abstract of Pan).
Regarding claim 18, Mitsuishi discloses that the surface characteristic includes at least one of dimensional measurements or surface chemical measurements ([0072] of Mitsuishi, surface roughness measured which is a dimensional measurement of the surface; claim only requires one of the recited measurement types).
Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over Guo in view of Harris, Mitsuishi, Wang and Ji et al. (Chinese Patent Publication No. CN 109781654 A, machine language translation provided and cited below).
Regarding claim 19, Guo discloses a substrate processing method (Abstract of Guo, wafer bonding method), the method comprising: activating a substrate for bonding (Abstract of Guo, method includes performing a plasma activation treatment on surfaces of the wafers); measuring a surface characteristic of a surface of the activated substrate ([0073] of Guo, RMS of surface roughness of the polished wafer surfaces can be less than 0.5 nm; determination of the surface roughness would necessarily require measuring the roughness); determining whether the surface is suitable for bonding based at least on the measuring ([0073] of Guo, RMS of surface roughness of the polished wafer surfaces can be less than 0.5 nm); and bonding the substrate (Abstract of Guo, process involves bonding the wafers).
Guo does not specifically disclose that the substrate processing method is a method for an integrated bonder system wherein activation occurs in at least one process chamber of the integrated bonder system, wherein the surface characteristic is measured in a metrology chamber of the integrated bonder system, wherein the integrated bonder system includes a mainframe connected to the at least one process chamber, the metrology chamber, and the bonder chamber. Harris discloses a modular mainframe layout for a multi-chamber substrate processing tool (Title and Abstract of Harris). The multi chamber processing tool of Harris includes one or more plasma chambers (FIG. 1, plasma chamber #130a #130b), a metrology chamber (FIG. 1 of Harris, metrology chamber #118), and one or more bonder chambers (FIG. 1 of Harris, bonder chambers #140). According to Harris, the multi-chamber processing tool provides for expandability and higher throughput ([0002]-[0003] of Harris). It would have been obvious to a person having ordinary skill in the art as of the effective filing date of the claimed invention to conduct the wafer bonding process of Guo in the multi-chamber processing tool of Harris. One of skill in the art would have been motivated to do so in order to provide for expandability and higher throughput as taught by Harris ([0002]-[0003] of Harris).
Harris does not specifically disclose bonding the substrate in a bonder chamber of the integrated bonder system if the surface is suitable for bonding or re-activating the substrate if the surface is not suitable for bonding. Moreover, Harris discloses that the system has a controller to enable data collection and feedback from the multi-chamber processing tool to optimize performance ([0041] of Harris) but does not specifically the details of the controller configuration such as using metrology data to determine if the surface is suitable for bonding. Mitsuishi, however, discloses a method for bonding semiconductor substrates comprising activating the bonding surfaces of the substrate, measuring the surface roughness of the substrates, and bonding the substrates, wherein the process is changed based on the surface roughness measurement ([0006] of Mitsuishi). According to Mitsuishi, if the measured surface roughness is above a predetermined value, the substrate is returned to the beginning of the bonding process for further processing including a further activation step ([0074]-[0075] of Mitsuishi, bonding prohibited and process starts again if measured roughness above predetermined value). Also according to Mitsuishi, surface roughness values below the predetermined value are suitable for achieving bonding whereas surface roughness values above the predetermined value are not suitable for achieving bonding ([0072] of Mitsuishi). It would have been obvious to a person having ordinary skill in the art as of the effective filing date of the claimed invention to bond the substrate in a bonder chamber of the integrated bonder system if the surface is suitable for bonding or re-activate the substrate if the surface is not suitable for bonding in the modified method. One of skill in the art would have been motivated to do so in order to ensure that the surface roughness conditions are suitable for achieving bonding of the substrates as taught by Mitsuishi ([0072] of Mitsuishi).
Harris also does not specifically disclose that determining includes comparing a measured infrared spectrum of the surface to a standard spectrum. Harris, however, discloses that the processing tool may include one or more metrology chambers configured to take measurements of the substrates ([0040] of Harris). Wang discloses that contamination present on the bonding surfaces of the wafers can prevent proper bonding of the wafers during a wafer bonding process ([0045] of Wang). Ji discloses a method for detecting surface contamination of a wafer comprising comparing a measured IR spectrum to a standard spectrum (Abstract, [0011] of Ji). It would have been obvious to a person having ordinary skill in the art as of the effective filing date of the claimed invention to identify contaminants on the bonding surfaces of the wafers in the modified process by comparing a measured infrared spectrum of the surface to a standard spectrum. One of skill in the art would have been motivated to do so in order to detect contaminants that would interfere with bonding as taught by Wang and Ji.
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Guo in view of Harris, Mitsuishi, Wang and Ji as applied to claim 19 above and further in view of Tsai et al. (U.S. Patent Application Publication No. 2019/0244851 A1, cited in previous Office Action).
Regarding claim 20, Ji does not specifically disclose that determining whether the surface is suitable for bonding is based on whether a difference between the measured infrared spectrum and the standard spectrum exceeds a predetermined threshold. Tsai, however, discloses a method for bonding semiconductor devices wherein an inspection module is used to determine the level of surface contamination (Abstract, [0027] of Tsai). Tsai also discloses determining if a percentage of the bonding surface which is contaminated is greater than a threshold value and cleaning the surface if the threshold value is exceeded ([0031] of Tsai). It would have been obvious to a person having ordinary skill in the art as of the effective filing date of the claimed invention to determine whether the surface is suitable for bonding based on whether a difference between the measured infrared spectrum and the standard spectrum exceeds a predetermined threshold in the modified process since Tsai establishes that it was known to do so at the time the invention was made. Moreover, as set forth in the MPEP, the rationale to support a conclusion that the claim would have been obvious is that all the claimed elements were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods with no change in their respective functions, and the combination yielded nothing more than predictable results to one of ordinary skill in the art (MPEP § 2143 I A). The prior art included each element claimed, although not necessarily in a single prior art reference, with the only difference between the claimed invention and the prior art being the lack of actual combination of the elements in a single prior art reference. In addition, one of ordinary skill in the art could have combined the elements as claimed by known methods, and that in combination, each element merely performs the same function as it does separately. One of ordinary skill in the art also would have recognized that the results of the combination were predictable.
Response to Arguments
Applicant's arguments have been fully considered to the extent that they apply to the new grounds of rejection but they are not persuasive.
The applicant asserts that none of the references cited in the previous Office Action teach or reasonably suggest a system as recited in claim 1 or a method as recited in claim 11 comprising measuring a surface characteristic of a surface of the activated substrate wherein the characteristic includes a surface chemical measurement (pp. 7-9 of the amendment). Harris, however, discloses that the processing tool may include one or more metrology chambers configured to take measurements of the substrates ([0040] of Harris). Wang discloses that contamination present on the bonding surfaces of the wafers can prevent proper bonding of the wafers during a wafer bonding process ([0045] of Wang). Pan discloses a method for detecting surface contamination (i.e., a surface chemical measurement) on a wafer using infrared transmission (Abstract of Pan). The newly cited Hawthorne reference discloses a semiconductor inspection system for identifying contamination on the surface of a silicon wafer (Abstract of Hawthorne). Harris, Wang and either of Pan or Hawthorne therefore suggest conducting a surface chemical measurement of the activated substrate.
The applicant also asserts that Tsai fails to teach or reasonably suggest comparing a measure IR spectrum to a standard spectrum as recited in claim 19. The Office Action, however, is relying upon the newly cited Ji reference to address this limitation.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHRISTOPHER W. RAIMUND whose telephone number is (571) 270-7560. The examiner can normally be reached M-Th 7:00-4:30.
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CHRISTOPHER W. RAIMUND
Primary Examiner
Art Unit 1746
/CHRISTOPHER W RAIMUND/Primary Examiner, Art Unit 1746
