DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Response to Amendment
Applicant's amendment to the claims, filed on July 2nd, 2026, is acknowledged. Entry of amendment is accepted and made of record.
Election/Restrictions
Applicant's election with traverse of Species I directed to Fig. 1 (claims 1-5, 8-9 and 10-20) in the reply filed on July 2nd, 2026 is acknowledged. The traversal is on the ground(s) that the Examiner has not established a serious search or examiner burden and no argument provided that the species would be classified in different class/subclass. This is not found persuasive because there is no requirement from MPEP 809.02 for the Examiner must provide any argument relating to species being classified in different class/subclass. In fact, the Examiners provided three reasons for search and/or examination burden in the previous office action is sufficient enough.
The requirement is still deemed proper and is therefore made FINAL.
Claims 4-5 and 14-15 recites “the logic chiplet further comprises a vias through” and/or “the logic chiplet is positioned between the memory chiplet and the top redistribution layer” which are being described as logic chiplet 202 having through-silicon vias 212 and positioned between memory chiplet 204 and the top distribution layer 203 in non-elected Species II of Fig. 2. Also claims 8-9 recites “the logic chiplet is positioned between the first redistribution layer and the second redistribution layer” in lines 12-13 which is being described as logic chiplet 202 positioned between interconnects 210 and top distribution layer 203 in non-elected Species II of Fig. 2. In addition, claims 18-19 recites “the logic chiplet is positioned between the additional redistribution layer and the top redistribution layer” in lines 12-13 of claim 18 which are being described as logic chiplet 202 positioned between interconnects 210 and the top distribution layer 203 in non-elected Species II of Fig. 2. Therefore, claims 4-5, 8-9, 14-15 and 18-19 are also withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected Species, there being no allowable generic or linking claim.
Claims 6-7 are not elected by the Applicant. However, claims 6-7 recites limitations in elected Species I of Fig. 1 and will be examined.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
a. Determining the scope and contents of the prior art.
b. Ascertaining the differences between the prior art and the claims at issue.
c. Resolving the level of ordinary skill in the pertinent art.
d. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-3, 6-7 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Secker et al. (Pub. No.: US 2013/0320560 A1), hereinafter as Secker in view of BRUN et al. (Pub. No.: US 2023/0207475 A1), hereinafter as Brun.
Regarding claim 1, Secker discloses a multi-chiplet assembly in Fig. 8 comprising: a logic chiplet (Memory controller 808) comprising an active frontside (the bottom side of second active circuit layer 818) having first active circuitry (active circuitry within the layer) (see [0033]); and a memory chiplet (an uppermost DRAM memory device 830) electrically coupled to the logic chiplet and comprising an active frontside (an active frontside of the DRAM memory device 830) having a second active circuitry (active circuitry at the active frontside of the uppermost DRAM memory device 830), wherein: the memory chiplet is configured as a main memory of the logic chiplet (DRAM memory device 830 of memory device stack 828 function as main memory) (see [0032-0033]); the active frontside of the logic chiplet faces a first direction (the bottom side of second active circuit layer 808 facing a down-ward direction) (see Fig. 8).
Secker fails to disclose the active frontside of the memory chiplet faces a second direction opposite the first direction.
Brun discloses a multi-chiplet assembly in Fig. 1A comprising a logic chiplet (die 141 being processor die/computational die) comprising an active frontside (the bottom side) having a first active circuitry (the bottom side having active circuitry connecting to interconnects 144) facing a first direction (downward direction) (see [0020]); a memory chiplet (first chiplet 151) comprising an active frontside (active surface 153) having second active circuitry (active circuitry at active surface 153) and the active frontside of the memory chiplet faces a second direction (up-ward direction) opposite the first direction (see Fig. 8 and [0022-0023]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the memory chiplet of Secker to have the active frontside having the second active circuitry facing a second direction opposite to the first direction as same as the memory chiplet of Brun because the modified structure would improve interconnect density and bandwidth and provide low latency for memory system by reducing connection pitch and shorten physical path and elimination of resistance and capacitance relay.
Regarding claim 2, the combination of Secker and Brun discloses the multi-chiplet assembly of claim 1, further comprising a redistribution layer (contact 834) (see Secker, Fig. 8 and [0033]), wherein the memory chiplet further comprises vias through (TSV 832) which the first active circuitry of the logic chiplet is electrically coupled to the redistribution layer (TSV 832 connecting the second active circuit layer 818 of Memory controller 808 to contact 834) (see Secker, Fig. 8 and [0033]).
Regarding claim 3, the combination of Secker and Brun discloses the multi-chiplet assembly of claim 2, further comprising an additional logic chiplet (Logic controller 806) directly coupled to the logic chiplet, wherein the logic chiplet is positioned between the additional logic chiplet and the memory chiplet (see Secker, Fig. 8 and [0033]).
Regarding claim 6, the combination of Secker and Brun discloses the multi-chiplet assembly of claim 1, Secker discloses the multi-chipplet assembly further comprising: through-package vias (TSVs 832 in the lowermost DRAM device 830) (see Fig. 8 and [0033]); a first redistribution layer (layer of bond pads 826) positioned between the logic chiplet and the memory chiplet (between Memory controller 808 and the uppermost DRAM memory device 830), the first redistribution layer coupling the first active circuitry of the logic chiplet (active circuitry of second active circuit layer 818) to the second active circuitry of the memory chiplet (active circuitry of the uppermost DRAM memory device 830) and the through-package vias (TSVs 832 in the lowermost DRAM device 830) (see Secker, Fig. 8 and [0032-0033]); and a second redistribution layer (layer of BGA of contacts 834) electrically coupled to the first active circuitry of the logic chiplet (active circuitry of second active circuit layer 818) by the through-package vias (TSVs 832 in the lowermost DRAM device 830), wherein: the active frontside of the logic chiplet faces the first direction (down-ward direction) and the first redistribution layer (layer of bond pads 826) and the second redistribution layer (layer of BGA of contacts 834) (see Fig. 8 of Secker and [0033]); the memory chiplet further comprises a backside (bottom surface of the uppermost DRAM memory device 830) facing the first direction (down-ward direction) and the second redistribution layer (layer of BGA of contacts 834); and the memory chiplet is positioned between the first redistribution layer and the second redistribution layer (the uppermost DRAM memory device 830 positioned between layer of bond pads 826 and layer of BGA of contacts 834) (see Fig. 8 of Secker).
Regarding claim 7, the combination of Secker and Brun discloses the multi-chiplet assembly of claim 6, further comprising an additional logic chiplet (Logic controller 806) directly coupled to the logic chiplet (Memory controller 808), wherein the logic chiplet is positioned between the additional logic chiplet and the memory chiplet (see Secker, Fig. 8 and [0033]).
Regarding claim 20, Secker discloses a method of manufacturing a multi-chiplet assembly in Fig. 8, the method comprising: electrically coupled a plurality of vias of a main-memory chiplet (plurality of TSVs 832 of an uppermost DRAM memory device 830) to a redistribution layer (layer of contacts 834) (see Fig. 8 and [0032-0033]), the main-memory chiplet comprising: the plurality of vias; and comprising an active frontside (an active frontside of the uppermost DRAM memory device 830) having a first active circuitry (active circuitry at the active frontside of the uppermost DRAM memory device 830) (see Fig. 8 and [0033]); electrically coupling a logic chiplet (Memory controller 808) to the main-memory chiplet, the logic chiplet comprising an active frontside (the bottom side of second active circuit layer 818) having second active circuitry (active circuitry within the layer) (see [0033]), wherein: the active frontside of the logic chiplet faces a second direction (down-ward direction) opposite a first direction (up-ward direction) (see Fig. 8); and the second active circuitry of the logic chiplet is electrically coupled to the redistribution layer by the plurality of vias of the main-memory chiplet (active circuitry of second active circuit layer 818 electrically coupled to contacts 834 by the plurality of vias 832) (see Fig. 8 and [0032-0033]).
Secker fails to disclose the method comprising wherein the active frontside of the memory chiplet faces away from the redistribution layer and faces the first direction.
Brun discloses a multi-chiplet assembly in Fig. 1A comprising electrically coupling a plurality of vias (TSVs 159) of a main memory chiplet (first chiplet 151) to a redistribution layer (layer of solders 158) (see [0022-0023]), and the main memory chiplet comprising the plurality of vias; and an active frontside (active surface 153) having first active circuitry (active circuitry at active surface 153), wherein the active frontside of the memory chiplet faces away from the redistribution layer (away from layer of solder 158) (see Fig. 8 and [0022-0023]); electrically coupling a logic chiplet (die 141 being processor die/computational die) to the main-memory chiplet comprising an active frontside (the bottom side) having a second active circuitry (the bottom side having active circuitry connecting to interconnects 144) (see [0020]), wherein: the active frontside of the main-memory chiplet faces a first direction (up-ward direction) (see Fig. 1A); the active frontside of the logic chiplet faces a second direction (down-ward direction) opposite the first direction (see Fig. 1A).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the memory chiplet of Secker to have the active frontside of the memory chiplet faces away from the redistribution layer and faces the first direction as same as the memory chiplet of Brun because the modified structure would improve interconnect density and bandwidth and provide low latency for memory system by reducing connection pitch and shorten physical path and elimination of resistance and capacitance relay.
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Secker et al. (Pub. No.: US 2013/0320560 A1), hereinafter as Secker in view of BRUN et al. (Pub. No.: US 2023/0207475 A1), hereinafter as Brun, as applied to claim 1 and further in view of Jeong et al. (Pub. No.: US 2022/0007511 A), hereinafter as Jeong.
Regarding claim 10, the combination of Secker and Brun discloses the multi-chiplet assembly of claim 1, further comprising: a first sub-package comprising the logic chiplet and the memory chiplet (first sub-package comprising a system module 802) (see Secker, Fig. 8 and [0032]). But the combination of Secker and Brun fails to disclose a second sub-package comprising an auxiliary chiplet.
Jeong discloses a muti-chiplet assembly in Figs. 3 and 10 comprising a first sub-package (semiconductor package 400) comprising a logic chiplet (ASIC chip 420) and memory chiplet (high bandwidth memory chip 420) and a second sub-package (substrate 100A) comprising an auxiliary chiplet (passive components 112a/112b) (see [0032-0033] and [0115-0017]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the second sub-package comprising an auxiliary chiplet of Jeong into the multi-chiplet assembly of Secker because the modified structure would enhance electrical performance of the memory package assembly by minimizing parasitic inductance, reducing signal distortion with shorter electrical connection and lowering manufacturing cost.
Claims 11-13 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Secker et al. (Pub. No.: US 2013/0320560 A1), hereinafter as Secker in view of BRUN et al. (Pub. No.: US 2023/0207475 A1), hereinafter as Brun, and further in view of Jeong et al. (Pub. No.: US 2022/0007511 A), hereinafter as Jeong.
Regarding claim 11, Secker discloses a multi-chiplet assembly in Fig. 8 comprising: a second sub-package comprising : a logic chiplet (Memory controller 808) comprising an active frontside (the bottom side of second active circuit layer 818) having first active circuitry (active circuitry within the layer) (see [0033]); and a memory chiplet (an uppermost DRAM memory device 830) electrically coupled to the logic chiplet and comprising an active frontside (an active frontside of the DRAM memory device 830) having a second active circuitry (active circuitry at the active frontside of the uppermost DRAM memory device 830) (see [0032-0033]); the active frontside of the logic chiplet faces a first direction (the bottom side of second active circuit layer 808 facing a down-ward direction) (see Fig. 8).
Secker fails to disclose a first sub-package comprising: a top redistribution layer;a bottom redistribution layer; and at least one auxiliary chiplet positioned between the top redistribution layer and the bottom redistribution layer; the second sub-package coupled to the top redistribution layer; and the active frontside of the memory chiplet faces a second direction opposite the first direction.
Jeong discloses a muti-chiplet assembly in Figs. 3 and 10 comprising a first sub-package (substrate 100A) comprising: a top redistribution layer (second build-up structure 130) (see Fig. 3 and [0032]); a bottom redistribution layer (first build-up structure 120) (see Fig. 3 and [0032]); and at least one auxiliary chiplet (passive components 112a/112b) positioned between the top redistribution layer and the bottom redistribution layer (see Fig. 3 and [0033]); a second sub-package (semiconductor package 400) coupled to the top redistribution layer and the second sub-package comprising a logic chiplet (ASIC chip 420) and memory chiplet (high bandwidth memory chip 420) (see Fig. 10, [0032-0033] and [0115-0017]).
The first substrate package of Jeong (substrate 100A) being incorporated into the a multi-chiplet assembly of Secker for positioning between DRAM device stack 828 and multi-layer circuit board 804 for disclosing a first sub-package comprising: a top redistribution layer;a bottom redistribution layer, and at least one auxiliary chiplet positioned between the top redistribution layer and the bottom redistribution layer and the second sub-package coupled to the top redistribution layer.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the first sub-package comprising an auxiliary chiplet of Jeong into the multi-chiplet assembly of Secker because the modified structure would enhance electrical performance of the memory package assembly by minimizing parasitic inductance, reducing signal distortion with shorter electrical connection and lowering manufacturing cost.
The combination of Secker and Jeong fails to disclose the active frontside of the memory chiplet faces a second direction opposite the first direction.
Brun discloses a multi-chiplet assembly in Fig. 1A comprising a logic chiplet (die 141 being processor die/computational die) comprising an active frontside (the bottom side) having a first active circuitry (the bottom side having active circuitry connecting to interconnects 144) facing a first direction (downward direction) (see [0020]); a memory chiplet (first chiplet 151) comprising an active frontside (active surface 153) having second active circuitry (active circuitry at active surface 153) and the active frontside of the memory chiplet faces a second direction (up-ward direction) opposite the first direction (see Fig. 8 and [0022-0023]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the memory chiplet of Secker to have the active frontside having the second active circuitry facing a second direction opposite to the first direction as same as the memory chiplet of Brun because the modified structure would improve interconnect density and bandwidth and provide low latency for memory system by reducing connection pitch and shorten physical path and elimination of resistance and capacitance relay.
Regarding claim 12, the combination of Secker, Jeong and Brun discloses the multi-chiplet assembly of claim 11, the memory chiplet (an uppermost DRAM memory device 830 of Secker) is positioned between the logic chiplet (Memory controller 808 of Secker) and the top redistribution layer (second build-up structure 130) (see Fig. 8 of Secker and Figs. 3, 10 of Jeong); and wherein the memory chiplet further comprises vias through (TSV 832) which the first active circuitry of the logic chiplet is electrically coupled to the top redistribution layer (TSV 832 connecting the second active circuit layer 818 of Memory controller 808 to second build-up structure 130) (see Secker, Fig. 8 and [0033]; Jeong, Figs. 3, 10 and [0032]).
Regarding claim 13, the combination of Secker, Jeong and Brun discloses the multi-chiplet assembly of claim 12, further comprising an additional logic chiplet (Logic controller 806) directly coupled to the logic chiplet, wherein the logic chiplet is positioned between the additional logic chiplet and the memory chiplet (see Secker, Fig. 8 and [0033]).
Regarding claim 16, the combination of Secker, Jeong and Brun discloses the multi-chiplet assembly of claim 12, wherein: the second sub-package further comprises: through-package vias (through vias 116 of Jeong) (see Fig. 3 of Jeong and [0038], [0057]); an additional redistribution layer (layer of bond pads 826 of Secker) positioned between the logic chiplet and the memory chiplet (between Memory controller 808 and the uppermost DRAM memory device 830 of Secker), the additional redistribution layer coupling the first active circuitry of the logic chiplet (active circuitry of second active circuit layer 818 of Secker) to the second active circuitry of the memory chiplet (active circuitry of the uppermost DRAM memory device 830 of Secker) and the through-package vias (through vias 116 of Jeong) (see Secker, Fig. 8, [0032-0033]; and Jeong, Fig. 3 and [0038]); and the active frontside of the logic chiplet (the bottom side of second active circuit layer 818 of Secker) faces the first direction (down-ward direction) and the top redistribution layer (second build-up structure 130 of Jeong) (see Jeong, Fig. 3 and [0032]); the memory chiplet further comprises a backside (bottom surface of the uppermost DRAM memory device 830 of Secker) facing the first direction (down-ward direction) and the top redistribution layer (second build-up structure 130 of Jeong) (see Fig. 8 of Secker and Fig. 3 of Jeong); and the memory chiplet is positioned between the additional redistribution layer and the top redistribution layer (the uppermost DRAM memory device 830 of Secker positioned between layer of bond pads 826 and second build-up structure 130 of Jeong) (see Fig. 8 of Secker).
Regarding claim 17, the combination of Secker, Jeong and Brun discloses the multi-chiplet assembly of claim 16, further comprising an additional logic chiplet (Logic controller 806) directly coupled to the logic chiplet (Memory controller 808), wherein the logic chiplet is positioned between the additional logic chiplet and the additional redistribution layer (between Logic controller 806 and layer of bond pads 826) (see Secker, Fig. 8 and [0033]).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CUONG B NGUYEN whose telephone number is (571)270-1509 (Email: CuongB.Nguyen@uspto.gov). The examiner can normally be reached Monday-Friday, 8:30 AM-5:00 PM Eastern Standard Time.
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/CUONG B NGUYEN/Primary Examiner, Art Unit 2818
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