DETAILED ACTION
This action is responsive to the following communications: the Application filed March 26, 2024, and the information disclosure statement (IDS) filed March 26, 2024.
Claims 1-20 are pending. Claims 1, 12 and 15 are independent.
Notice of Pre-AIA or AIA Status
The present application is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on March 26, 2024 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of AIA 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-4, 6-7, 12-13, 15-16 and 18 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Cho et al. (US 8,279,659).
Regarding independent claims 1 and 12, and its method independent claim 15, the claimed limitation(s) of memory device having sense amplifier enabling circuitry is a well-known technology for a type of memory (e.g., SRAM) for its purpose. For support, of the above asserted facts, see for example, Cho et al. disclose a circuit (see e.g., FIG. 2) comprising:
static random-access memory (202) cells;
a sense amplifier (204) coupled to the SRAM cells (202); and
SRAM mimic circuitry (214) comprising a plurality of selectable banks (244, i.e., multiple transistor stacked devices 248 controlled by 214) of SRAM mimic cells (DC), wherein the SRAM mimic circuitry is configured to select a subset of the selectable (i.e., controlled by 214) banks to drive a sense amplifier enable (SAE) signal for enabling (205 SAEN) the sense amplifier (204) during a read operation (i.e., sensing means a read operation) of the SRAM cells (see FIG. 2 along with timing diagram FIG. 3, and accompanying disclosure).
Further, regarding method claim 15, where the claimed and prior art products are identical or substantially identical in structure or composition, or are produced by identical or substantially identical processes, a prima facie case of either anticipation or obviousness has been established. Examiner has an authority to shift the burden to applicant and require applicant to either: (1) show the prior art memory device and the claimed memory device are not substantially identical; or (2) prove, by evidence, that the prior art memory device is not capable of performing the functions claimed. see MPEP 2112.01(I).
Regarding claims 2 and 13, which depends from claims 1 and 12, respectively, Cho et al disclose an adjustable voltage supply configured to adjust a gate voltage of transistors in the plurality of selectable banks (see FIG. 214 along with FIG. 3: 304 and 306).
Regarding claim 3, which depends from claim 2, Cho et al disclose the adjustable voltage supply comprises a voltage divider (see FIG. 3: 304 and 306).
Regarding claim 4, which depends from claim 3, Cho et al disclose voltage divider comprises a plurality of wire resistors that have linear behavior across process, voltage, temperature (PVT) corners (e.g., col. 5, lines 62-63: … under a variety of process, voltage ,temperature, or other operating conditions; further it’s an inherent characteristic of memory device).
Regarding claim 6, which depends from claim 2, Cho et al disclose the SRAM mimic circuitry comprises: a plurality of inverters, wherein each output of the plurality of inverters is coupled to gates of the transistors in a respective one of the plurality of selectable banks, wherein power supplies of the plurality of inverters is coupled to the adjustable voltage supply in order to adjust the gate voltage of transistors in the plurality of selectable banks (see FIGS. 2-3 and accompanying disclosure).
Regarding claim 7, which depends from claim 1, Cho et al disclose a configurable delay circuit configured to receive the SAE signal from the SRAM mimic circuitry, provide a delay, and forward the SAE signal to the sense amplifier (see FIGS. 2-3 and accompanying disclosure).
Regarding claim 16, which depends from claim 15, Cho et al disclose the gate voltage is adjusted using a voltage divider (see FIG. 3: 304 and 306), wherein the voltage divider comprises a plurality of wire resistors that have linear behavior across process, voltage, temperature (PVT) corners (e.g., col. 5, lines 62-63: … under a variety of process, voltage ,temperature, or other operating conditions; further it’s an inherent characteristic of memory device).
Regarding claim 18, which depends from claim 15, Cho et al disclose Delaying the SAE signal using a configurable delay circuit (see FIGS. 2-3 and accompanying disclosure).
Claim Rejections - 35 USC § 103
The following is a quotation of AIA 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 5, 8-11, 14, 17 and 19-20 are rejected under AIA 35 U.S.C. 103 as being unpatentable over Cho et al. (US 8,279,659).
Regarding claims 5 and 14, Cho et al. teach the limitations of claims 2 and 13, respectively.
Cho et al. further teach a feedback loop coupled to an output and an input of the SRAM mimic circuitry, wherein the feedback loop is configured to selectively bypass the adjustable voltage supply so that a rail voltage is used as the gate voltage of transistors in the plurality of selectable banks (see FIGS. 2-3 and accompanying disclosure).
Cho et al. do not explicitly disclose a feedback loop.
However, feedback loop for the sense amplifier enabling circuit of a memory device is a well-known technology for a type of memory for its purpose.
For support, of the above asserted facts, see for example, Lin et al. (US 2015/0248923), e.g., FIG. 7, feedback circuit of sense enable, sae, and accompanying disclosure.
It would have been obvious to one of ordinary skill in the art before the effective filing date to utilize static random access memory used as configuration random access memory includes sese enable signal controls when outputting (reading) data because these conventional technology are well established in the art of the memory devices.
Regarding claims 8 and 19, Cho et al. teach the limitations of claims 1 and 15, respectively.
Cho et al. do not explicitly each of the plurality of selectable banks of SRAM mimic cells comprises a different number of stacks of transistors.
However, having different number of selectable stacked transistors in memory tracking devices is a well-known technology for a type of memory for its purpose.
For support, of the above asserted facts, see for example, Chan et al. (US 6,958,943), FIG. 3 and accompanying disclosure.
It would have been obvious to one of ordinary skill in the art before the effective filing date to utilize different components for stacked elements in memory tracking devices because these conventional technology are well established in the art of the memory devices.
Regarding claims 9 and 20, Cho et al. teach the limitations of claims 8 and 19, respectively.
Cho et al. further teach the stacks of transistors comprises at least two nFET transistors coupled in series (FIG. 2: 248).
Regarding claims 10 and 17, Cho et al. teach the limitations of claims 9 and 15, respectively.
Cho et al. do not explicitly the stacks of transistors have different voltage thresholds than transistors in the SRAM cell.
However, HVT, LVT transistors for stacked elements in memory tracking devices is a well-known technology for a type of memory for its purpose.
It would have been obvious to one of ordinary skill in the art before the effective filing date to utilize different threshold components for stacked elements in memory tracking devices because these conventional technology are well established in the art of the memory devices.
Regarding claim 11, Cho et al. teach the limitations of claim 8.
Cho et al. further teach the stacks of transistors are coupled to a pFET in the SRAM mimic circuitry, wherein the pFET and the stacks of transistors mimic a read path in the SRAM cells (see FIG. 2: 248, 240 paths coupled to SA).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SUNG IL CHO whose telephone number is (571)270-0137. The examiner can normally be reached M-Th, 7:30AM-5PM; Every other F, 7:30AM-4PM EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Alexander G Sofocleous can be reached on 571-272-0635. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/SUNG IL CHO/Primary Examiner, Art Unit 2825