DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 6/11/2025 and 6/22/2025 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Election/Restrictions
Applicant’s election without traverse of Group II (Claims 1-13) in the reply filed on 6/24/2026 is acknowledged.
Response to Amendment
Receipt is acknowledged of an amendment to the claims of application #18617412 received on 6/24/2026. Claims 14-18 are cancelled. Claim 3 is amended. Claims 19-25 are newly added. Claims 1-2 and 4-13 are left in original form. Claims 1-13 and 19-25 are pending. All pending claims are considered and examined.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-4, 6-8, 11-12, 19 and 21-23 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Huang et al. (US 20180102578 A1).
Regarding claim 1, Huang discloses (Fig. 13 & 14) flipped RF filters and components comprising:
a semiconductor substrate 204 (¶89);
a tag IC layer 1402, formed on a front side of the semiconductor substrate (¶89);
a first conductive layer, formed over a back side of the semiconductor substrate opposite to the front side (¶93 - through-silicon-via 1414 can connect to a backside of the substrate 204, where conductive end 1416, and a conductive end of through-silicon-via 1414, are on opposite sides of the pane of substrate 204, or where conductive end 1418, and a conductive end of through-silicon-via 1414, are on opposite sides of the pane of substrate 204); and
a second conductive layer, formed over a side of the tag IC layer that is distal to the semiconductor substrate, so that the tag IC layer and the semiconductor substrate are sandwiched between the first conductive layer and the second conductive layer (¶93 - through-silicon-via 1414 can connect to a backside of the substrate 204, where conductive end 1416, and a conductive end of through-silicon-via 1414, are on opposite sides of the pane of substrate 204, or where conductive end 1418, and a conductive end of through-silicon-via 1414, are on opposite sides of the pane of substrate 204),
wherein the second conductive layer is electrically coupled to the tag IC layer (¶90).
Regarding claim 2, Huang discloses the apparatus of claim 1 above and further discloses wherein the second conductive layer, the tag IC layer, the semiconductor substrate, and the first conductive layer are sequentially stacked along a first direction, and adjacent side surfaces of the second conductive layer, the tag IC layer, the semiconductor substrate, and the first conductive layer are parallel to the first direction and are cut flush (¶52; Fig. 14).
Regarding claim 3, Huang discloses the apparatus of claim 1 above and further discloses wherein the first conductive layer is electrically coupled to the tag IC layer through a through silicon via (TSV) formed in the semiconductor substrate (¶93).
Regarding claim 4, Huang discloses the apparatus of claim 1 above and further discloses wherein the second conductive layer, the tag IC layer, the semiconductor substrate, and the first conductive layer are sequentially stacked along a first direction, and a length of the vertical semiconductor RFID structure along the first direction is about 300 µm to about 800 µm (¶65 - the substrates 204 are thinned to a selected thickness, such as 2-200 microns; two 200µm layers is 400 µm thick and four 200µm layers is 800 µm thick, which is within the claimed endpoints).
Regarding claim 6, Huang discloses the apparatus of claim 1 above and further discloses wherein the tag IC layer comprises at least one of a logic integrated circuit (IC), a memory IC, a power IC, or an analog IC (¶87-¶89).
Regarding claim 7, Huang discloses the apparatus of claim 1 above and further discloses an antenna substrate; an antenna disposed on the antenna substrate, wherein the antenna comprises: a first terminal; and a second terminal; and the vertical semiconductor RFID structure of claim 1, coupled to the antenna, wherein the second conductive layer, the tag IC layer, the semiconductor substrate, and the first conductive layer of the vertical semiconductor RFID structure are sequentially stacked along a first direction, and the first direction is parallel to a top surface of the antenna substrate; from a top view, the first conductive layer overlaps the first terminal without overlapping the second terminal, and the second conductive layer overlaps the second terminal without overlapping the first terminal; and the first conductive layer is electrically coupled to the first terminal, and the second conductive layer is electrically coupled to the second terminal (¶89; ¶93-¶95; Figs. 13, 14, and 15).
Regarding claim 8, Huang discloses the apparatus of claim 7 above and further discloses wherein the vertical semiconductor RFID structure, the antenna, and the antenna substrate are sequentially stacked along a second direction, and the first direction is perpendicular to the second direction (Fig. 14).
Regarding claim 11, Huang discloses the apparatus of claim 7 above and further discloses wherein the first conductive layer and the second conductive layer have spherical shapes, protruding shapes or droplet shapes (¶94, Fig. 15).
Regarding claim 12, Huang discloses the apparatus of claim 7 above and further discloses a first conductive contact layer, surrounding the first conductive layer, and coupled between the first conductive layer and the first terminal of the antenna; and a second conductive contact layer, surrounding the second conductive layer, and coupled between the second conductive layer and the second terminal of the antenna (Fig. 15).
Regarding claim 19, Huang discloses the apparatus of claim 1 above and further discloses wherein the second conductive layer, the tag IC layer, the semiconductor substrate, and the first conductive layer are sequentially stacked along a first direction, and a length of the vertical semiconductor RFID structure along the first direction is larger than a length of the vertical semiconductor RFID along a second direction perpendicular to the first direction (Fig. 13 & 15).
Regarding claim 21, Huang discloses the apparatus of claim 2 above and further discloses wherein edges of side surfaces of the vertical semiconductor RFID structure are passivated, wherein each of the side surfaces of the vertical semiconductor RFID structure is formed by the side surfaces of the second conductive layer, the tag IC layer, the semiconductor substrate, and the first conductive layer (¶52; the substrate stack is cut in the same way as disclosed and are thus also passivated).
Regarding claim 22, Huang discloses the apparatus of claim 3 above and further discloses wherein a thickness of the semiconductor substrate is about 100um to about 300um (¶65 - the substrates 204 are thinned to a selected thickness, such as 2-200 microns).
Regarding claim 23, Huang discloses the apparatus of claim 7 above and further discloses wherein adjacent side surfaces of the second conductive layer, the tag IC layer, the semiconductor substrate, and the first conductive layer are parallel to the first direction and are coplanar (Figs. 13 & 14).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 13 and 24-25 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hotta (US 20190363068 A1).
Regarding claim 13, Huang discloses the apparatus of claim 7 above but does not explicitly disclose an anisotropic conductive adhesive filled between the first conductive layer and the first terminal, and between the second conductive layer and the second terminal.
Hotta teaches a stacked device, stacked structure, and method of manufacturing stacked device comprising: the plurality of terminals are bonded through an anisotropic conductive member (¶15-¶16). The support 46 and the anisotropic conductive member 20 adhere to each other (¶163).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to provide the terminal connection of Huang with the adhesive anisotropic conductive member as taught by Hotta as a simple substitution of one known element for another to obtain predictable results.
Regarding claim 24, Huang discloses the apparatus of claim 7 above but does not explicitly disclose wherein the antenna substrate includes flexible material.
Hotta teaches: the support 46, a flexible and transparent support can be used (¶165).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to provide the substrate of Huang with the flexible substrate as taught by Hotta as a simple substitution of one known element for another to obtain predictable results.
Regarding claim 25, Huang modified by Hotta teaches the apparatus of claim 13 above and further teaches wherein the anisotropic conductive adhesive includes a viscous resin and conductive particles dispersed in the viscous resin (Hotta: ¶153 - The anisotropic conductive member 20 further includes a resin layer 44 that is provided on surfaces 40a and 40b of the insulating substrate 40).
Claim(s) 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Brun et al. (US 20220375844 A1).
Regarding claim 20, Huang discloses the apparatus of claim 1 above but does not explicitly disclose wherein the first conductive layer and the second conductive layer include multiple layers of different metals, respectively.
Brun teaches an integrated circuit package comprising: conductive traces 118 comprised of one or more layers of metals may be disposed on surface 116. For example, conductive trace 118A comprises a single layer of metal; conductive trace 118B comprises three layers of metals. Any number of metal layers may be comprised in conductive traces 118 within the scope of the present disclosure. Any of conductive traces 118, vias 114 and/or through-connections 110 may be formed of any appropriate conductive material, such as copper, silver, nickel, gold, aluminum, or other metals or alloys (¶46). An anisotropic conductive material may include microscopic conductive particles embedded in a binder or a thermoset adhesive film (e.g., a thermoset biphenyl-type epoxy resin, or an acrylic-based material). In some embodiments, the conductive particles may include a polymer and/or one or more metals (e.g., nickel or gold) (¶67).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to provide the first conductive layer and the second conductive layer of Huang with the multiple layers of different metals as taught by Brun as a simple substitution of one known element for another to obtain predictable results.
Allowable Subject Matter
Claims 5 and 9-10 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: Huang discloses (Fig. 13 & 14) flipped RF filters and components comprising: a semiconductor substrate 204 (¶89); a tag IC layer 1402, formed on a front side of the semiconductor substrate (¶89); a first conductive layer, formed over a back side of the semiconductor substrate opposite to the front side (¶93 - through-silicon-via 1414 can connect to a backside of the substrate 204, where conductive end 1416, and a conductive end of through-silicon-via 1414, are on opposite sides of the pane of substrate 204, or where conductive end 1418, and a conductive end of through-silicon-via 1414, are on opposite sides of the pane of substrate 204); and a second conductive layer, formed over a side of the tag IC layer that is distal to the semiconductor substrate, so that the tag IC layer and the semiconductor substrate are sandwiched between the first conductive layer and the second conductive layer (¶93 - through-silicon-via 1414 can connect to a backside of the substrate 204, where conductive end 1416, and a conductive end of through-silicon-via 1414, are on opposite sides of the pane of substrate 204, or where conductive end 1418, and a conductive end of through-silicon-via 1414, are on opposite sides of the pane of substrate 204), wherein the second conductive layer is electrically coupled to the tag IC layer (¶90). The cited prior art of record does not teach, fairly suggests or make obvious a vertical semiconductor radio frequency identification (RFID) structure, comprising: a semiconductor substrate; a tag IC layer, formed on a front side of the semiconductor substrate; a first conductive layer, formed over a back side of the semiconductor substrate opposite to the front side; and a second conductive layer, formed over a side of the tag IC layer that is distal to the semiconductor substrate, so that the tag IC layer and the semiconductor substrate are sandwiched between the first conductive layer and the second conductive layer, wherein the second conductive layer is electrically coupled to the tag IC layer, wherein an interfacing area between the tag IC layer and the semiconductor substrate is in a rectangular shape with a longer side and a shorter side, and a length of the shorter side is about 30 um to about 300 um. (claims 1 & 5); nor a radio frequency identification (RFID) tag device, comprising: a vertical semiconductor radio frequency identification (RFID) structure, comprising: a semiconductor substrate; a tag IC layer, formed on a front side of the semiconductor substrate; a first conductive layer, formed over a back side of the semiconductor substrate opposite to the front side; and a second conductive layer, formed over a side of the tag IC layer that is distal to the semiconductor substrate, so that the tag IC layer and the semiconductor substrate are sandwiched between the first conductive layer and the second conductive layer, wherein the second conductive layer is electrically coupled to the tag IC layer; an antenna substrate; and an antenna disposed on the antenna substrate, wherein the antenna comprises: a first terminal; and a second terminal, wherein the vertical semiconductor RFID structure is coupled to the antenna, wherein the second conductive layer, the tag IC layer, the semiconductor substrate, and the first conductive layer of the vertical semiconductor RFID structure are sequentially stacked along a first direction, and the first direction is parallel to a top surface of the antenna substrate; from a top view, the first conductive layer overlaps the first terminal without overlapping the second terminal, and the second conductive layer overlaps the second terminal without overlapping the first terminal; and the first conductive layer is electrically coupled to the first terminal, and the second conductive layer is electrically coupled to the second terminal, wherein the vertical semiconductor RFID structure, the antenna, and the antenna substrate are sequentially stacked along a second direction, and the first direction is perpendicular to the second direction, wherein an interfacing area between the tag IC layer and the semiconductor substrate is in a rectangular shape with a longer side and a shorter side, wherein the longer side is perpendicular to the second direction, and the shorter side is parallel to the second direction (claims 1 and 7-9).
Conclusion
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/TOAN C LY/Primary Examiner, Art Unit 2876
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