ETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This action is responsive to the application filed March 26, 2024.
Claims 1-20 are pending and are presenting for examination.
Examiner Notes
Examiner cites particular columns and line numbers in the references as applied to the claims below for the convenience of the applicant. Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested that, in preparing responses, the applicant fully consider the references in entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the examiner.
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim Objections
Claims 2-3, 9-10, and 16-17 are objected to because of the following informalities:
As per claim 2 and claim 9, recites to include the following limitation, “wherein the one or more software programs comprise one or more kernels that are generated to perform one or more functions the one or more graph nodes” should be changed to, for example,
-- wherein the one or more software programs comprise one or more kernels that are generated to perform the one or more hardware library functions of the one or more graph nodes -- instead.
As per claim 3 and claim 10, recites to include the following limitation, “wherein graph comprises one or more subgraphs that indicate one or more hardware library functions to be performed by the one or more software programs” should be changed to, for example,
-- wherein the graph comprises one or more subgraphs that indicate the one or more hardware library functions to be performed by the one or more software programs -- instead.
As to claim 16, recites to include the following limitation, “generating one or more kernels to perform one or more functions the one or more graph nodes” should be changed to, for example,
-- generating one or more kernels to perform the one or more hardware library functions of the one or more graph nodes-- instead.
As to claim 17, recites to include the following limitation, “wherein graph comprises one or more subgraphs that indicate one or more hardware library functions to be performed by the one or more software programs” should be changed to, for example,
-- wherein the graph comprises one or more subgraphs that indicate the one or more hardware library functions to be performed by the one or more software programs-- instead.
Appropriate correction is required.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
7. Claims 1-4, 6-11, 13-17, 19, and 20 are rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea without significantly more.
Independent Claims 1, 8, and 15 recite:
A method, comprising:
generating using a complier, one or more software programs based at least in part on a graph comprising one or more graph nodes indicating one or more hardware library functions to be performed by the one or more software programs.
Step 2A – prong 1:
The claims recite the limitation of:
A method, comprising:
generating one or more software programs based at least in part on a graph comprising one or more graph nodes indicating one or more hardware library functions to be performed by the one or more software programs.
The limitation of “generating one or more software programs based at least in part on a graph comprising one or more graph nodes indicating one or more hardware library functions to be performed by the one or more software programs” as drafted, is function that, under its broadest reasonable interpretation, recite the abstract idea of a mental process. The limitations encompass a human mind carrying out the function through observation, evaluation judgment and /or opinion, or even with the aid of pen and paper. Thus, this limitation recites and falls within the “Mental Processes” grouping of abstract ideas under Prong 1.
Step 2A – Prong 2:
Under Prong 2, this judicial exception is not integrated into a practical application. The claims recite the following additional elements “A processor, comprising: one or more circuits to perform a compiler”, “A system, comprising: one or more processors to cause one or more circuits to perform a compiler”, and “using a complier” are recited at a high-level of generality such that it amounts no more than mere instructions to apply the exception using generic computer, and/or mere computer components. Accordingly, the additional elements do not integrate the recited judicial exception into a practical application and the claim is therefore directed to the judicial exception. See MPEP 2106.05(g).
Step 2B:
Under Step 2B, the claims do not include additional elements that are sufficient to amount to significantly more than the judicial exception. As discussed above with respect to integration of the abstract idea into a practical application, the additional elements of “A processor, comprising: one or more circuits to perform a compiler”, “A system, comprising: one or more processors to cause one or more circuits to perform a compiler”, and “using a complier” amount to no more than mere instructions, or generic computer/computer components to carry out the exception. The recitation of generic computer instruction and computer components to apply the judicial exception do not amount to significantly more, thus, cannot provide an inventive concept. Accordingly, the claims are not patent eligible under 35 USC 101.
Regarding to per claims 2 and 9, the limitation of “wherein the one or more software programs comprise one or more kernels that are generated to perform one or more functions the one or more graph nodes” recites further mental processes. The additional elements of “The processor” and “The system” a are merely the use of a computer/instructions running on the computer to carry out the judicial exception, which is neither a practical application under prong 2, nor an inventive concept under step 2B.
Regarding to claim 16, the limitation of “further comprising generating one or more kernels to perform one or more functions the one or more graph nodes” recites further mental processes. The claim does not include any additional element, thus, no limitation that needs to be analyzed under prong 2 for practical application, or under step 2B for significantly more.
Regarding to per claims 3 and 10, the limitation of “wherein graph comprises one or more subgraphs that indicate one or more hardware library functions to be performed by the one or more software programs” is further define data—graph-- which is nothing more than insignificant extra solution activity which is not a practical application under prong 2. Under step 2B, the courts of identified the data gathering, the results of the judicial exception, is well-understood, routine and conventional activity. See MPEP 2106.05(d). The additional elements of “The processor” and “The system” are merely the use of a computer/instructions running on the computer to carry out the judicial exception, which is neither a practical application under prong 2, nor an inventive concept under step 2B.
Regarding to claim 17, the limitation of “wherein graph comprises one or more subgraphs that indicate one or more hardware library functions to be performed by the one or more software programs” is further define data—graph-- which is nothing more than insignificant extra solution activity which is not a practical application under prong 2. Under step 2B, the courts of identified the data gathering, the results of the judicial exception, is well-understood, routine and conventional activity. The claim does not include any additional element, thus, no limitation that needs to be analyzed under prong 2 for practical application, or under step 2B for significantly more.
Regarding to per claims 4 and 11, the limitation of “wherein the graph is a directed acyclic graph (DAG)” is further define data—graph-- which is nothing more than insignificant extra solution activity which is not a practical application under prong 2. Under step 2B, the courts of identified the data gathering, the results of the judicial exception, is well-understood, routine and conventional activity. See MPEP 2106.05(d). The additional elements of “The processor” and “The system” are merely the use of a computer/instructions running on the computer to carry out the judicial exception, which is neither a practical application under prong 2, nor an inventive concept under step 2B.
Regarding to per claims 6 and 13, recites additional elements of “wherein the graph is generated by a deep learning accelerator (DLA) compiler”, “The processor”, and “The system” are merely the use of a computer/instructions running on the computer to carry out the judicial exception, which is neither a practical application under prong 2, nor an inventive concept under step 2B.
Regarding to claim 19, recites additional elements of “wherein the graph is generated by a deep learning accelerator (DLA) compiler” is merely the use of a computer/instructions running on the computer to carry out the judicial exception, which is neither a practical application under prong 2, nor an inventive concept under step 2B.
Regarding to per claims 7, 14, and 20, the limitation of “wherein the one or more software programs comprise two or more functions to be performed by two or more processors simultaneously” merely defines the one or more software program being generated in per claims 1, 8, and 15. Since the human mind can reasonably generate the one or more software program as such as to include “two or more functions generated” recited herein recite a mental process. The additional elements of “The processor” and “The system” a are merely the use of a computer/instructions running on the computer to carry out the judicial exception, which is neither a practical application under prong 2, nor an inventive concept under step 2B.
Claim Rejections - 35 USC § 103
8. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
9. Claims 1-4, 6-11, 13-17, 19, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Surendran et al. (US 20220350683 A1, hereinafter Surendran) in view of Ogawa et al. (US 20050289499 A1, hereinafter Ogawa).
As to claim 1, Surendran discloses a processor, comprising: one or more circuits to perform a compiler to generate one or more software programs – (e.g., “a deep learning (DL) compiler 102 uses a representation of a computer program 104 to generate code 106 –software program-- that combines operations represented in representation of computer program 104. In at least one embodiment, DL compiler 102 is a computer program that runs on a processor (e.g., a CPU)”, “In at least one embodiment, instructions that include combined operations (e.g., code 106 of FIG. 1 generated by DL compiler 102) are launched from a host 302 to a device 304… In at least one embodiment, processor 310 of device 304 includes one or more circuits to perform one or more instructions in a software kernel, including two or more dependent reduction operations, where dependent reduction operations have been combined in software kernel by a compiler (e.g., DL compiler 102 of FIG. 1)”– see at least paragraphs 0056, 0117, 0119, 0120, Figs. 1-3, and associated text) based at least in part on a graph comprising one or more graph nodes indicating one or more functions to be performed by the one or more software programs – (E.g., In at least one embodiment, representation of computer program 104 is a graph (e.g., a directed acyclic graph (DAG)). In at least one embodiment, representation of computer program 104 is a DAG, which expresses data flow dependencies between operations… for generating code 106. In at least one embodiment
, graphs of operations 200 are representations of computer programs, first graph 202 includes six inputs inl, in2, in3, in4, in5, and in6 that are used by various nodes of first graph 202– see at least 0060, 0102, 0103, Figs. 1-3 and associated text).
It is to note that while Surendran discloses a compiler to generate one or more software programs based at least in part on a graph comprising one or more graph nodes indicating one or more functions to be performed by the one or more software programs – (e.g., a deep learning (DL) compiler 102 uses a representation of a computer program 104 to generate code 106, in which computer program 104 is a graph (e.g., a directed acyclic graph (DAG) having various nodes and edges expressed data flow dependencies between operations --see at least 0056, 0060, 0102, 0103, Figs. 1-3 and associated text), but does not explicitly disclose; however, Ogawa, discloses that the graph comprising one or more graph nodes indicating one or more hardware library functions—(e.g., a graph creating from a Control Data Flow Graph (CDFG) including nodes having sharing and scheduling of hardware resource library functions as nodes as such,
First, in the CDFG generation step (step S11), a graph referred to as a "CDFG" (Control Data Flow Graph).
In the initial allocation scheduling step (step S102), an allocation schedule and an allocated resource connection graph are generated based on the CDFG generated in the CDFG generation step. In more detail, prior to the initial allocation scheduling step, a hardware resource library including properties (for example, functions and delay time) of a calculator (for example, an adder, a multiplier, etc.; hereinafter, referred to as a hardware resource) usable in the design target circuit is prepared. In the initial allocation scheduling step, hardware resources, which can perform a calculation executed at each of the processing nodes in the CDFG and which fulfill the design specifications including the operating frequency and the like, are selected from the hardware resource library, and a reallocated to the corresponding processing nodes. The hardware resource allocated to the processing node is referred to as an "allocated resource" – see Ogawa, at least 0009-0010, 0078, Fig. 1, and associated text.
Thus, it would have been obvious to one of ordinary skill in the art before the effective
filing date of the claimed invention to have incorporated hardware resource library functions as nodes as seen in Ogawa into the graph of Surendran for further optimizing compiler via sharing hardware resources and preventing errors as seen in Ogawa (e.g., 0085).
As to claim 8, Surendran discloses a system (i.e. device 304), comprising: one or more processors to cause one or more circuits to perform a compiler to generate one or more software programs (e.g., “a deep learning (DL) compiler 102 uses a representation of a computer program 104 to generate code 106 –software program-- that combines operations represented in representation of computer program 104. In at least one embodiment, DL compiler 102 is a computer program that runs on a processor (e.g., a CPU)”, “In at least one embodiment, instructions that include combined operations (e.g., code 106 of FIG. 1 generated by DL compiler 102) are launched from a host 302 to a device 304… In at least one embodiment, processor 310 of device 304 includes one or more circuits to perform one or more instructions in a software kernel, including two or more dependent reduction operations, where dependent reduction operations have been combined in software kernel by a compiler (e.g., DL compiler 102 of FIG. 1)”– see at least paragraphs 0056, 0117, 0119, 0120, Figs. 1-3,and associated text) based at least in part on a graph comprising one or more graph nodes indicating one or more functions to be performed by the one or more software programs – (E.g., In at least one embodiment, representation of computer program 104 is a graph (e.g., a directed acyclic graph (DAG)). In at least one embodiment, representation of computer program 104 is a DAG, which expresses data flow dependencies between operations… for generating code 106. In at least one embodiment, graphs of operations 200 are representations of computer programs, first graph 202 includes six inputs inl, in2, in3, in4, in5, and in6 that are used by various nodes of first graph 202– see at least 0060, 0102, 0103, Figs. 1-3 and associated text).
It is to note that while Surendran discloses a compiler to generate one or more software programs based at least in part on a graph comprising one or more graph nodes indicating one or more functions to be performed by the one or more software programs – (e.g., a deep learning (DL) compiler 102 uses a representation of a computer program 104 to generate code 106, in which computer program 104 is a graph (e.g., a directed acyclic graph (DAG) having various nodes and edges expressed data flow dependencies between operations --see at least 0056, 0060, 0102, 0103, Figs. 1-3 and associated text), but does not explicitly disclose; however, Ogawa, discloses that the graph comprising one or more graph nodes indicating one or more hardware library functions—(e.g., a graph creating from a Control Data Flow Graph (CDFG) including nodes having sharing and scheduling of hardware resource library functions as nodes as such,
First, in the CDFG generation step (step S11), a graph referred to as a "CDFG" (Control Data Flow Graph).
In the initial allocation scheduling step (step S102), an allocation schedule and an allocated resource connection graph are generated based on the CDFG generated in the CDFG generation step. In more detail, prior to the initial allocation scheduling step, a hardware resource library including properties (for example, functions and delay time) of a calculator (for example, an adder, a multiplier, etc.; hereinafter, referred to as a hardware resource) usable in the design target circuit is prepared. In the initial allocation scheduling step, hardware resources, which can perform a calculation executed at each of the processing nodes in the CDFG and which fulfill the design specifications including the operating frequency and the like, are selected from the hardware resource library, and a reallocated to the corresponding processing nodes. The hardware resource allocated to the processing node is referred to as an "allocated resource" – see Ogawa, at least 0009-0010, 0078, Fig. 1, and associated text.
Thus, it would have been obvious to one of ordinary skill in the art before the effective
filing date of the claimed invention to have incorporated hardware resource library functions as nodes as seen in Ogawa into the graph of Surendran for further optimizing compiler via sharing hardware resources and preventing errors as seen in Ogawa (e.g., 0085).
As per claims 2 and 9, modified Surendran with Ogawa discloses wherein the one or more software programs comprise one or more kernels that are generated to perform one or more functions the one or more graph nodes – (E.g., code 106 includes one or more software
kernels to perform computer program 104 operations (function) representing in a graph – see Surendran, at least paragraphs 0056-0057, Figs. 1-3, and associated text).
As per claims 3 and 10, it is to note that while Surendran discloses wherein graph comprises one or more subgraphs that indicate one or more functions to be performed by the one or more software programs-- (e.g., computer program 104 is a subgraph of a larger graph to be performed by code 106--see Surendran at least paragraphs 0060, 0102, 0103, Figs. 1-3 and associated text), but does not explicitly disclose; however, Ogawa, discloses that the program code is one or more hardware library functions —(e.g., a graph creating from a Control Data Flow Graph (CDFG) including nodes having sharing and scheduling of hardware resource library functions as nodes as such,
First, in the CDFG generation step (step S11), a graph referred to as a "CDFG" (Control Data Flow Graph).
In the initial allocation scheduling step (step S102), an allocation schedule and an allocated resource connection graph are generated based on the CDFG generated in the CDFG generation step. In more detail, prior to the initial allocation scheduling step, a hardware resource library including properties (for example, functions and delay time) of a calculator (for example, an adder, a multiplier, etc.; hereinafter, referred to as a hardware resource) usable in the design target circuit is prepared. In the initial allocation scheduling step, hardware resources, which can perform a calculation executed at each of the processing nodes in the CDFG and which fulfill the design specifications including the operating frequency and the like, are selected from the hardware resource library, and a reallocated to the corresponding processing nodes. The hardware resource allocated to the processing node is referred to as an "allocated resource" – see Ogawa, at least 0009-0010, 0078, Fig. 1, and associated text.
Thus, it would have been obvious to one of ordinary skill in the art before the effective
filing date of the claimed invention to have incorporated hardware resource library functions as nodes as seen in Ogawa into the graph of Surendran for further optimizing compiler via sharing hardware resources and preventing errors as seen in Ogawa (e.g., 0085).
As per claims 4 and 11, modified Surendran with Ogawa discloses wherein the graph is a directed acyclic graph (DAG) --(e.g., a deep learning (DL) compiler 102 uses a representation of a computer program 104 to generate code 106, in which computer program 104 is a graph (e.g., a directed acyclic graph (DAG) having various nodes and edges expressed data flow dependencies between operations – see Surendra, at least paragraphs 0056, 0060, 0102, 0103, Figs. 1-3 and associated text).
As to claim 15, Surendran discloses a method, comprising: generating using a complier, one or more software programs -- (e.g., “a deep learning (DL) compiler 102 uses a representation of a computer program 104 to generate code 106 –software program-- that combines operations represented in representation of computer program 104. In at least one embodiment, DL compiler 102 is a computer program that runs on a processor (e.g., a CPU)”, “In at least one embodiment, instructions that include combined operations (e.g., code 106 of FIG. 1 generated by DL compiler 102) are launched from a host 302 to a device 304… In at least one embodiment, processor 310 of device 304 includes one or more circuits to perform one or more instructions in a software kernel, including two or more dependent reduction operations, where dependent reduction operations have been combined in software kernel by a compiler (e.g., DL compiler 102 of FIG. 1)”– see at least paragraphs 0056, 0117, 0119, 0120, Figs. 1-3, and associated text) based at least in part on a graph comprising one or more graph nodes indicating one or more functions to be performed by the one or more software programs– (E.g., In at least one embodiment, representation of computer program 104 is a graph (e.g., a directed acyclic graph (DAG)). In at least one embodiment, representation of computer program 104 is a DAG, which expresses data flow dependencies between operations… for generating code 106. In at least one embodiment, graphs of operations 200 are representations of computer programs, first graph 202 includes six inputs inl, in2, in3, in4, in5, and in6 that are used by various nodes of first graph 202– see at least 0060, 0102, 0103, Figs. 1-3 and associated text).
It is to note that while Surendran discloses generating using a compiler, one or more software programs based at least in part on a graph comprising one or more graph nodes indicating one or more functions to be performed by the one or more software programs – (e.g., a deep learning (DL) compiler 102 uses a representation of a computer program 104 to generate code 106, in which computer program 104 is a graph (e.g., a directed acyclic graph (DAG) having various nodes and edges expressed data flow dependencies between operations --see at least 0056, 0060, 0102, 0103, Figs. 1-3 and associated text), but does not explicitly disclose; however, Ogawa, discloses that the graph comprising one or more graph nodes indicating one or more hardware library functions—(e.g., a graph creating from a Control Data Flow Graph (CDFG) including nodes having sharing and scheduling of hardware resource library functions as nodes as such,
First, in the CDFG generation step (step S11), a graph referred to as a "CDFG" (Control Data Flow Graph).
In the initial allocation scheduling step (step S102), an allocation schedule and an allocated resource connection graph are generated based on the CDFG generated in the CDFG generation step. In more detail, prior to the initial allocation scheduling step, a hardware resource library including properties (for example, functions and delay time) of a calculator (for example, an adder, a multiplier, etc.; hereinafter, referred to as a hardware resource) usable in the design target circuit is prepared. In the initial allocation scheduling step, hardware resources, which can perform a calculation executed at each of the processing nodes in the CDFG and which fulfill the design specifications including the operating frequency and the like, are selected from the hardware resource library, and a reallocated to the corresponding processing nodes. The hardware resource allocated to the processing node is referred to as an "allocated resource" – see Ogawa, at least 0009-0010, 0078, Fig. 1, and associated text.
Thus, it would have been obvious to one of ordinary skill in the art before the effective
filing date of the claimed invention to have incorporated hardware resource library functions as nodes as seen in Ogawa into the graph of Surendran for further optimizing compiler via sharing hardware resources and preventing errors as seen in Ogawa (e.g., 0085).
As per claims 6, 13, and 19, modified Surendran with Ogawa discloses wherein the graph is generated by a deep learning accelerator (DLA) compiler – (E.g., a graph is generated from deep learning compiler 102—see Surendra, at least paragraphs 0056, 0060, 0062, 0065, 0102, 0103, Figs. 1-3 and associated text).
As per claims 7, 14 and 20, modified Surendran with Ogawa discloses wherein the one or more software programs comprise two or more functions to be performed by two or more processors simultaneously – (E.g., In at least one embodiment, instructions that include combined operations (e.g., code 106 of FIG. 1 generated by DL compiler 102) are launched from a host 302 to a device 304…In at least one embodiment, device 304 is an accelerator that includes a processor 310 (e.g., one or more parallel processors) and memory 312.– see Surendra, at least paragraphs 0117, 0119, Figs. 1-3, and associated text).
As to claim 16, modified Surendran with Ogawa discloses further comprising generating one or more kernels to perform one or more functions the one or more graph nodes– (E.g., code 106 includes one or more software kernels to perform computer program 104 operations (function) representing in a graph – see Surendran, at least paragraphs 0056-0057, Figs. 1-3, and associated text).
As to claim 17, it is to note that while Surendran discloses wherein graph comprises one or more subgraphs that indicate one or more functions to be performed by the one or more software programs -- (e.g., computer program 104 is a subgraph of a larger graph to be performed by code 106--see Surendran at least paragraphs 0060, 0102, 0103, Figs. 1-3 and associated text), but does not explicitly disclose; however, Ogawa, discloses that the program code is one or more hardware library functions —(e.g., a graph creating from a Control Data Flow Graph (CDFG) including nodes having sharing and scheduling of hardware resource library functions as nodes as such,
First, in the CDFG generation step (step S11), a graph referred to as a "CDFG" (Control Data Flow Graph).
In the initial allocation scheduling step (step S102), an allocation schedule and an allocated resource connection graph are generated based on the CDFG generated in the CDFG generation step. In more detail, prior to the initial allocation scheduling step, a hardware resource library including properties (for example, functions and delay time) of a calculator (for example, an adder, a multiplier, etc.; hereinafter, referred to as a hardware resource) usable in the design target circuit is prepared. In the initial allocation scheduling step, hardware resources, which can perform a calculation executed at each of the processing nodes in the CDFG and which fulfill the design specifications including the operating frequency and the like, are selected from the hardware resource library, and a reallocated to the corresponding processing nodes. The hardware resource allocated to the processing node is referred to as an "allocated resource" – see Ogawa, at least 0009-0010, 0078, Fig. 1, and associated text.
Thus, it would have been obvious to one of ordinary skill in the art before the effective
filing date of the claimed invention to have incorporated hardware resource library functions as nodes as seen in Ogawa into the graph of Surendran for further optimizing compiler via sharing hardware resources and preventing errors as seen in Ogawa (e.g., 0085).
10. Claims 5, 12, and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Surendran in view of Ogawa, and in further view of Venkataraja et al. (US 20100262594 A1, hereinafter Venkataraja).
As per claims 5 and 12, it is to note that while Surendran discloses wherein the one or more software programs having one or more kernels that perform one or more functions indicted by the one or more graph nodes --(E.g., code 106 includes one or more software kernels to perform computer program 104 operations (functions) nodes representing in a graph – see Surendran, at least paragraphs 0056-0057, Figs. 1-3, and associated text), but does not explicitly disclose; however, Ogawa, discloses that the one or more functions is one or more hardware library functions — (e.g., a graph creating from a Control Data Flow Graph (CDFG) including nodes having sharing and scheduling of hardware resource library functions as nodes as such,
First, in the CDFG generation step (step S11), a graph referred to as a "CDFG" (Control Data Flow Graph).
In the initial allocation scheduling step (step S102), an allocation schedule and an allocated resource connection graph are generated based on the CDFG generated in the CDFG generation step. In more detail, prior to the initial allocation scheduling step, a hardware resource library including properties (for example, functions and delay time) of a calculator (for example, an adder, a multiplier, etc.; hereinafter, referred to as a hardware resource) usable in the design target circuit is prepared. In the initial allocation scheduling step, hardware resources, which can perform a calculation executed at each of the processing nodes in the CDFG and which fulfill the design specifications including the operating frequency and the like, are selected from the hardware resource library, and a reallocated to the corresponding processing nodes. The hardware resource allocated to the processing node is referred to as an "allocated resource" – see Ogawa, at least 0009-0010, 0078, Fig. 1, and associated text.
Thus, it would have been obvious to one of ordinary skill in the art before the effective
filing date of the claimed invention to have incorporated hardware resource library functions as nodes as seen in Ogawa into the graph of Surendran for further optimizing compiler via sharing hardware resources and preventing errors as seen in Ogawa (e.g., 0085).
It is further to note that modified Surendran with Ogawa does not explicitly disclose that the one or more software programs call one or more kernel that perform the oner or more hardware library functions; however, Venkataraja, in analogous art, discloses the one or more software programs call one or more kernels that perform the oner or more hardware library functions – (e.g., user applications such as 210A-210C – one or more software programs --invoke other low-level/system routines that constitute kernel 240 to perform one or more library routine/functions of library 230 – see Venkataraja, at least paragraph 0042, Fig. 2, and associated text).
Thus, it would have been obvious to one of ordinary skill in the art before the effective
filing date of the claimed invention to have incorporated Venkataraja’s teaching into modified teaching of Surendran with Ogawa enable code program 106 to perform specific tasks from library function as seen in Venkataraja (e.g., 0042).
As to claim 18, it is to note that while Surendran discloses further comprising using the one or more software programs having one or more kernels that perform the one or more functions indicted by the one or more graph nodes--(E.g., code 106 includes one or more software kernels to perform computer program 104 operations (functions) nodes representing in a graph – see Surendran, at least paragraphs 0056-0057, Figs. 1-3, and associated text), but does not explicitly disclose; however, Ogawa, discloses that the one or more functions is one or more hardware library functions — (e.g., a graph creating from a Control Data Flow Graph (CDFG) including nodes having sharing and scheduling of hardware resource library functions as nodes as such,
First, in the CDFG generation step (step S11), a graph referred to as a "CDFG" (Control Data Flow Graph).
In the initial allocation scheduling step (step S102), an allocation schedule and an allocated resource connection graph are generated based on the CDFG generated in the CDFG generation step. In more detail, prior to the initial allocation scheduling step, a hardware resource library including properties (for example, functions and delay time) of a calculator (for example, an adder, a multiplier, etc.; hereinafter, referred to as a hardware resource) usable in the design target circuit is prepared. In the initial allocation scheduling step, hardware resources, which can perform a calculation executed at each of the processing nodes in the CDFG and which fulfill the design specifications including the operating frequency and the like, are selected from the hardware resource library, and a reallocated to the corresponding processing nodes. The hardware resource allocated to the processing node is referred to as an "allocated resource" – see Ogawa, at least 0009-0010, 0078, Fig. 1, and associated text.
Thus, it would have been obvious to one of ordinary skill in the art before the effective
filing date of the claimed invention to have incorporated hardware resource library functions as nodes as seen in Ogawa into the graph of Surendran for further optimizing compiler via sharing hardware resources and preventing errors as seen in Ogawa (e.g., 0085).
It is further to note that modified Surendran with Ogawa does not explicitly disclose that the one or more software programs call one or more kernel that perform the oner or more hardware library functions; however, Venkataraja, in analogous art, discloses the one or more software programs call one or more kernels that perform the oner or more hardware library functions – (e.g., user applications such as 210A-210C – one or more software programs --invoke other low-level/system routines that constitute kernel 240 to perform one or more library routine/functions of library 230 – see Venkataraja, at least paragraph 0042, Fig. 2, and associated text).
Thus, it would have been obvious to one of ordinary skill in the art before the effective
filing date of the claimed invention to have incorporated Venkataraja’s teaching into modified teaching of Surendran with Ogawa enable code program 106 to perform specific tasks from library function as seen in Venkataraja (e.g., 0042).
Conclusion
11. The prior art made of record and not relied upon (cited on 892 form) is considered pertinent to application disclosure.
Nagpal et al. (US-11561826-B1) disclose enable a developer to easily add nodes
, kernels, and processing threads to a neural network application.
Dakkak et al. (US-20240256241-A1) discloses A compiler for generating composable kernels.
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/MARINA LEE/Primary Examiner, Art Unit 2192
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