DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of Claims
The status of the claims is as follows: Claims 1-17 are pending.
Claim 8 has been amended.
Claims 14-17 have been added. An action on the merits for claims 1-17 follows.
Response to Arguments
Applicants’ arguments filed 08/07/2026 have been fully considered but they are not persuasive. In response to applicant’s argument that the process of Stepniak does not allow to include a seed layer it is first noted that the disclosure of Stepniak refutes this assertion by stating that “device processing can include the use of […] seed layers […] which are known in the art” (Stepniak, Paragraph [0041]) and that Stepniak envisions the modification of its process with the use of a seed layer even if it does not specify the exact form the seed layer takes. Furthermore, the device processing method of Stepniak is irrelevant as to the motivation to combine given that only the finalized device is incorporated into the rejection, and the device could conceivably be modified to be made through an entirely different method not disclosed by Stepniak.
Applicant’s assertion on pg. 7 that a seed layer is structurally and procedurally impossible in Stepniak’s architecture Stepniak uses a subtractive process, not a cavity-first additive process and no such cavity exist within Stepniak is also found to be unpersuasive. Firstly, the claims in question are device claims directed at the structure of a device and not the method of its formation. Additionally, the claims are not directed to the inclusion of a specific cavity, but instead directed to using a seed layer, something directly indicated as possible by Stepniak. This is found to be not persuasive because one of ordinary skill in the art could conceivably modify the process of Stepniak to be compatible with a seed layer, such as by depositing the seed layer in stages, or multiple segments, in a way that would be incorporated into Stepniak’s process.
Considering Yang’s specific motivation to combine and lack of shown distinction in the final product of the combined references, the previous rejection is maintained, and a new ground of rejection is put forward for new claims 14-17.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-13 are rejected under 35 U.S.C. 103 as being unpatentable over Stepniak et al. (US 20120211884 A1), hereinafter Stepniak in view of Yang et al. (US 20180211895 A1), hereinafter Yang.
Regarding Claim 1, Stepniak teaches a bond over active circuit (BOAC) semiconductor die package (“semiconductor device;” Fig. 10), comprising:
a semiconductor die (“semiconductor substrate,” (100); Paragraph [0023] describes elements of a semiconductor structure corresponding to but not described regarding Fig. 10) having a device side comprising a circuit (“active circuitry,” (112); Paragraph [0023]);
a conductive member (“conductive layer” including (190, 192, 194); Paragraph [0035]) electrically coupled to the circuit (112), wherein the conductive member (190, 192, 194) comprises an outer surface (top surface of (194)) that is spaced away from the circuit (112) and a plurality of side surfaces extending from the outer surface (top surface of (194)), and wherein the conductive member (190, 192, 194) comprises a plurality of layers (190, 192, and 194) of different metal materials (Paragraph [0035]); and
an insulating member (“passivation layer,” (140); Paragraph [0035]).
Stepniak does not explicitly teach:
a seed layer abutting the plurality of side surfaces of the conductive member; and
an insulating member abutting the seed layer such that the seed layer is between the plurality of side surfaces and the insulating member.
Yang teaches at least a bond over active circuit (BOAC) semiconductor die package (“semiconductor device,” (110a); Fig. 1, Fig. 2 (enlarged view of Fig. 1), Paragraph [0021]), comprising:
a conductive member (“conductor,” (104); Paragraph [0025]);
a seed layer (“electric conductive layer,” (106); Fig. 2, Paragraph [0028]) abutting the plurality of side surfaces of the conductive member (104); (the method of manufacturing a semiconductor device describes that (106) may be configured as a seed layer; Paragraph [0044]) and
an insulating member (“polymeric material,” (105); Paragraph [0027]) abutting the seed layer (106) such that the seed layer (106) is between the plurality of side surfaces and the insulating member (105).
It would have been obvious to one of ordinary skill in the art before the effective filing date of
the claimed invention to incorporate the teachings of Yang into the device of Stepniak such that Stepniak comprises a seed layer abutting/surrounding the conductive member between the conductive member and the insulating member. This is because Stepniak discloses that seed layers are known in the art and may be included within (Stepniak, Paragraph [0041]). Additionally, the seed layer has the added benefit of separating the entire conductive member from the insulating member; preventing a delamination between them (Yang, Paragraph [0034]). (Yang, Paragraph [0034]). A result of the seed layer being implemented in the device of Stepniak is that the insulating layer would necessarily abut the seed layer such that the seed layer is between the plurality of side surfaces and the insulating member of the present application. (A modified Fig. 10 of Stepniak is included below showing the described inclusion of a seed layer (SL) based on Yang and the outer surface (OS) of the conductive member.)
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Regarding Claim 2, Stepniak as modified by Yang teaches the BOAC semiconductor die package (“semiconductor device;” Fig. 10) of claim 1, wherein the conductive member comprises:
a first portion (“first conductive layer,” (190); Paragraph [0035]) comprising a first metal material (“copper;” Paragraph [0035]);
a second portion (“second conductive layer,” (192); Paragraph [0035]) extending from the first portion (190) and comprising a second metal material (“nickel;” Paragraph [0035]); and
a third portion (“third conductive layer,” (194); Paragraph [0035]) extending from the second portion (192) to form the outer surface (OS) and comprising a third metal material (“palladium;” Paragraph [0035]).
Regarding Claim 3, Stepniak as modified by Yang teaches the BOAC semiconductor die package (“semiconductor device;” Fig. 10) of claim 2, wherein the first metal material (“copper”) comprises Copper (Cu), the second metal material (“nickel”) comprises Nickel (Ni), and the third metal material (“palladium”) comprises Palladium (Pd) (Paragraph [0035]).
Regarding Claim 4, Stepniak as modified by Yang teaches the BOAC semiconductor die package (“semiconductor device;” Fig. 10) of claim 2, wherein the seed layer ((SL); modified Fig. 10) is positioned between the insulating member (140) and the third portion (194) (see modified Fig. 10).
Regarding Claim 5, Stepniak as modified by Yang teaches the BOAC semiconductor die package (“semiconductor device;” Fig. 10) of claim 1, wherein the conductive member (190, 192, 194) is positioned within a cavity formed in the insulating member (140).
Regarding Claim 6, Stepniak as modified by Yang teaches the BOAC semiconductor die package (“semiconductor device;” Fig. 10) of claim 5, wherein the insulating member (140) comprises polyimide (PI) (“can include a polyimide coating;” Paragraph 0026. Refers to Fig. 4 but describes the same composition and element number of (140) as in Fig. 10).
Regarding Claim 7, Stepniak as modified by Yang teaches the BOAC semiconductor die package (“semiconductor device;” Fig. 10) of claim 1, wherein the outer surface (OS) is recessed inward from an outer surface (Ins OS) of the insulating member (140) (see Annotated Fig.10 below; the outer surface (OS) of (194) is recessed inward from and below the outer surface (Ins OS) of (140)).
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Regarding Claim 8, Stepniak teaches a bond over active circuit (BOAC) semiconductor die package (“semiconductor device;” Fig. 10), comprising:
a semiconductor die (“semiconductor substrate,” (100); Paragraph [0023] describes elements of a semiconductor structure corresponding to but not described regarding Fig. 10) having a device side comprising a circuit (“active circuitry,” (112); Paragraph [0023]);
an insulating member (“passivation layer,” (140); Paragraph [0035]) on the semiconductor die (100);
a conductive member (“conductive layer” including (190, 192, 194); Paragraph [0035]) positioned within the insulating member (140) and electrically coupled to the circuit (112), wherein the conductive member (190, 192, 194) comprises a longitudinal axis ((LA); annotated Fig. 10), an outer surface ((OS); annotated Fig. 10) axially spaced from the circuit (112) along the longitudinal axis (LA), and an outer perimeter extending from the outer surface (OS) toward the circuit (112), and wherein the conductive member (190, 192, 194) comprises a plurality of layers (190, 192, and 194) of different metal materials (Paragraph [0035]). (Annotated Fig. 10 marking outer surface and longitudinal axis shown for reference.)
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Stepniak does not explicitly teach:
a seed layer surrounding the conductive member along the outer perimeter within the insulating member.
Yang teaches at least bond over active circuit (BOAC) semiconductor die package (“semiconductor device,” (110a); Fig. 1, Fig. 2 (enlarged view of Fig. 1), Paragraph [0021]), comprising:
a seed layer (“electric conductive layer,” (106); Fig. 2, Paragraph [0028]) surrounding the conductive member (“conductor,” (104); Paragraph [0025]) along the outer perimeter within the insulating member (“polymeric material,” (105); Paragraph [0027]). (The method of manufacturing a semiconductor device describes that (106) may be configured as a seed layer; Paragraph [0044]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teachings of Yang into the device of Stepniak such that Stepniak comprises a seed layer abutting/surrounding the conductive member between the conductive member and the insulating member. This is because Stepniak discloses that seed layers are known in the art and may be included within (Stepniak, Paragraph [0041]). Additionally, the seed layer has the added benefit of separating the entire conductive member from the insulating member; preventing a delamination between them (Yang, Paragraph [0034]). A result of the seed layer being implemented in the device of Stepniak is that the seed layer would necessarily surround the conductive member within the insulating member of the present application. (An annotated Fig. 10 of Stepniak is included below showing the described inclusion of a seed layer (SL) based on Yang.)
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Regarding Claim 9, Stepniak as modified by Yang teaches the BOAC semiconductor die package (“semiconductor device;” Fig. 10) of claim 8, wherein the conductive member comprises:
a first portion (“first conductive layer,” (190); Paragraph [0035]) comprising a first metal material (“copper;” Paragraph [0035]);
a second portion (“second conductive layer,” (192); Paragraph [0035]) extending from the first portion (190) and comprising a second metal material (“nickel;” Paragraph [0035]); and
a third portion (“third conductive layer,” (194); Paragraph [0035]) extending from the second portion (192) to form the outer surface (OS) and comprising a third metal material (“palladium;” Paragraph [0035]).
Regarding Claim 10, Stepniak as modified by Yang teaches the BOAC semiconductor die package (“semiconductor device;” Fig. 10) of claim 9, wherein the first metal material (“copper”) comprises Copper (Cu), the second metal material (“nickel”) comprises Nickel (Ni), and the third metal material (“palladium”) comprises Palladium (Pd) (Paragraph [0035]).
Regarding Claim 11, Stepniak as modified by Yang teaches the BOAC semiconductor die package (“semiconductor device;” Fig. 10) of claim 8, wherein the outer surface (OS) is recessed inward from an outer surface of the insulating member (140) (see annotated Fig.10 below; the outer surface (OS) of (194) is recessed inward from and below the outer surface (Ins OS) of (140) along the longitudinal axis (LA)).
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Regarding Claim 12, Stepniak as modified by Yang teaches the BOAC semiconductor die package (“semiconductor device;” Fig. 10) of claim 11, wherein the insulating member (140) comprises polyimide (PI) (“can include a polyimide coating;” Paragraph 0026. Refers to Fig. 4 but describes the same composition and element number of (140) as in Fig. 10).
Regarding Claim 13, Stepniak as modified by Yang teaches the BOAC semiconductor die package (“semiconductor device;” Fig. 10) of claim 8, comprising a second conductive member (second of (190, 192, 194) together) within the insulating member (140) that is adjacent to the conductive member (190, 192, 194), wherein the second conductive member (second of (190, 192, 194) together) is electrically insulated from the conductive member (190, 192, 194) by the insulating member (140).
(Stepniak discloses that Fig. 10 depicts only part of a device and other structures may be part of the semiconductor die Paragraph [0040]. Furthermore, since the device disclosed in Fig. 10 includes an insulator (140) on each side, it would be implicit that a first and second conductive member of (190, 192, and 194) would be electrically insulated from each other when placed side by side.)
Claims 14-17 are rejected under 35 U.S.C. 103 as being unpatentable over Stepniak in view of Yang and further in view of Koduri (US 20190109105 A1), hereinafter Koduri.
Regarding Claim 14, Stepniak teaches a bond over active circuit (BOAC) semiconductor die package (“semiconductor device;” Fig. 10), comprising:
a semiconductor die (“semiconductor substrate,” (100); Paragraph [0023] describes elements of a semiconductor structure corresponding to but not described regarding Fig. 10) having a device side comprising a circuit (“active circuitry,” (112); Paragraph [0023]);
a conductive member (“conductive layer” including (190, 192, 194); Paragraph [0035]) electrically coupled to the circuit (112), wherein the conductive member (190, 192, 194) comprises an outer surface (top surface of (194)) that is spaced away from the circuit (112), a plurality of side surfaces extending from the outer surface (top surface of (194)) towards the circuit (112), and an inner end proximate the circuit (112), and wherein the conductive member (190, 192, 194) comprises a plurality of layers (190, 192, and 194) of different metal materials (Paragraph [0035]); and
an insulating member (“passivation layer,” (140); Paragraph [0053]).
Stepniak does not explicitly teach:
a seed layer abutting the plurality of side surfaces of the conductive member; and
an insulating member abutting the seed layer such that the seed layer is between the plurality of side surfaces and the insulating member.
Yang teaches at least a bond over active circuit (BOAC) semiconductor die package (“semiconductor device,” (110a); Fig. 1, Fig. 2 (enlarged view of Fig. 1), Paragraph [0021]), comprising:
a conductive member (“conductor,” (104); Paragraph [0025]);
a seed layer (“electric conductive layer,” (106); Fig. 2, Paragraph [0028]) abutting the plurality of side surfaces of the conductive member (104); (the method of manufacturing a semiconductor device describes that (106) may be configured as a seed layer; Paragraph [0044]) and
an insulating member (“polymeric material,” (105); Paragraph [0027]) abutting the seed layer (106) such that the seed layer (106) is between the plurality of side surfaces and the insulating member (105).
It would have been obvious to one of ordinary skill in the art before the effective filing date of
the claimed invention to incorporate the teachings of Yang into the device of Stepniak such that Stepniak comprises a seed layer abutting/surrounding the conductive member between the conductive member and the insulating member. This is because Stepniak discloses that seed layers are known in the art and may be included within (Stepniak, Paragraph [0041]). Additionally, the seed layer has the added benefit of separating the entire conductive member from the insulating member; preventing a delamination between them (Yang, Paragraph [0034]). (Yang, Paragraph [0034]). A result of the seed layer being implemented in the device of Stepniak is that the insulating layer would necessarily abut the seed layer such that the seed layer is between the plurality of side surfaces and the insulating member of the present application. (A modified Fig. 10 of Stepniak is included below showing the described inclusion of a seed layer (SL) based on Yang and the outer surface (OS) of the conductive member.)
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Stepniak as modified by Yang additionally does not explicitly teach
the inner end comprising a plurality of projections engaged with one or more conductive terminals of the circuit, and
an insulating member between the inner end and the insulating member.
Koduri teaches at least a semiconductor die package (“semiconductor packaging structure,” (100); Fig. 1, Paragraph [0033]) wherein:
the inner end (bottom of “second metal layer,” (114); Paragraph [0037]) comprising a plurality of projections (“first metal layer,” (107); Fig. 1, Paragraph [0035]) engaged with one or more conductive terminals (“bond pads,” (124); Paragraph [0033]) of the circuit, and
an insulating member (“insulating material,” (104); Paragraph [0034]) abutting the seed layer (“seed layer,” (112); Paragraph [0037]) such that the seed layer (112) is between the inner end (bottom of 114) and the insulating member (104).
It would have been obvious to one of ordinary skill in the art before the effective filing date of
the claimed invention to incorporate the teachings of Koduri into the device of Stepniak modified by Yang such that the inner end of the conductive member comprises a plurality of projections engaged with one or more conductive terminals of the circuit with an insulating member abutting the seed layer such that the seed layer is between the inner end and the insulating member as a result. This is because including multiple contact points with the conductive terminal (spaced apart by the insulator) provides standoff thickness and flexibility for microstresses Paragraph [0035]) below the larger conductive member that spreads out the current and provides strength for the benefit of improving reliability (Paragraph [0037]).
Regarding Claim 15, Stepniak as modified by Yang and Koduri teaches the BOAC semiconductor die package (“semiconductor device;” Fig. 10)) of claim 14, wherein the conductive member (190, 192, 194) comprises:
a first portion (“first conductive layer,” (190); Paragraph [0035]) comprising Copper (Cu) (“copper;” Paragraph [0035]);
a second portion (“second conductive layer,” (192); Paragraph [0035]) extending from the first portion (190) and comprising Nickel (Ni) (“nickel;” Paragraph [0035]); and
a third portion (“third conductive layer,” (194); Paragraph [0035]) extending from the second portion (192), wherein the third portion (194) comprises the outer surface and comprises Palladium (Pd) (“palladium;” Paragraph [0035]).
Regarding Claim 16, Stepniak as modified by Yang and Koduri teaches the BOAC semiconductor die package (Yang, “semiconductor device,” (110a); Fig. 1, Fig. 2 (enlarged view of Fig. 1), Paragraph [0021]) of claim 14, wherein the seed layer (Yang, 106) is a continuous film surrounding the conductive member (Yang, 104) within a cavity formed in the insulating member (Yang, 105), the seed layer (Yang, 106) extending along the plurality of side surfaces and the inner end without extending over the outer surface (Yang, Fig. 2 shows the seed layer (106) surrounding the conductive member on the sides and bottom (corresponding to the inner end) without extending to the upper/outer surface of the conductive member).
Regarding Claim 17, Stepniak as modified by Yang and Koduri teaches the BOAC semiconductor die package (“semiconductor device;” Fig. 10) of claim 14, wherein the insulating member (140) comprises polyimide (PI) (“can include a polyimide coating;” Paragraph 0026. Refers to Fig. 4 but describes the same composition and element number of (140) as in Fig. 10) and the outer surface (OS) of the conductive member (190, 192, 194) is recessed inward from an outer surface (Ins OS) of the insulating member (140). (A modified Fig. 10 of Stepniak is included below showing the described inclusion of a seed layer (SL) based on Yang and the outer surface (OS) of the conductive member.)
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Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this
Office action. THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/NOLAN GABRIEL STUESSY/Examiner, Art Unit 2812
/DAVIENNE N MONBLEAU/Supervisory Patent Examiner, Art Unit 2812
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