DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Inventorship
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 3/27/2024 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Specification
The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Claim Objections
Claims 3 and 16-18 are objected to because of the following informalities:
Claim 3 recites the limitation "corresponding he first" [sic] in line 3.
Claim 3 recites the limitation "the three -level" [sic] in line 4.
Claim 16 must end in with a period.
Claims 17 and 18 inherit the same from claim 16.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recites the limitation "the first-level conversion module" in line 5. There is insufficient antecedent basis for this limitation in the claim. Claim 1 indicates there is more than one first-level conversion module. It is unclear which module the applicant is referring to since at least two modules are so far being claimed (i.e. N being an integrated greater than 1).
Claim 1 recites the limitation "the third-level conversion module" in line 14. There is insufficient antecedent basis for this limitation in the claim. Claim 1 indicates there multiple third-level conversion modules, which third-level module is the applicant referring to?
Claim 2 recites the limitation "the second-level conversion modules" in line 1. There is insufficient antecedent basis for this limitation in the claim. The applicant only claimed 1 so far.
Claim 2 recites the limitation "the same phase" in line 2. There is insufficient antecedent basis for this limitation in the claim.
Claim 2 recites the limitation "the corresponding pulse distribution signal" in line 3. There is insufficient antecedent basis for this limitation in the claim.
Claim 3 recites the limitation "the three-level conversion modules in one second level conversion module" in line 1. There is insufficient antecedent basis for this limitation in the claim.
Claim 3 recites the limitation "the corresponding first phase distribution signal" in line 4. There is insufficient antecedent basis for this limitation in the claim.
Claim 4 recites the limitation "the first output terminals" in line 5. There is insufficient antecedent basis for this limitation in the claim.
Claim 4 recites the limitation "the control circuits" in line 5. There is insufficient antecedent basis for this limitation in the claim.
Claim 4 recites the limitation "the third-level conversion modules" in line 5. There is insufficient antecedent basis for this limitation in the claim. Does this limitation include the at least one third-level conversion module in addition to the multiple third-level conversion modules or is the applicant referring to something else?
Claims 2-20 inherit the same from claim 1.
Please find and correct any and all further errors that may exist.
Appropriate correction is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-4, 6, 7, 11, 12 and 20 is/are rejected under 35 U.S.C. 102a1/a2 as being anticipated by Schuellein (US 20070291520).
Claims 1, 11 and 12; as best as the claim language is understood, Schuellein discloses a multi-phase voltage converter (e.g. figure 1), comprising: a control chip (10) configured to generate N pulse distribution signals (e.g. CLKOUT, PHSOUT, etc.), wherein N is a positive integer greater than 1; a power conversion module (fig. 1) comprising N first-level conversion modules (N being two; two groups of ICs; the first three being group 1 and the second being group 2) wherein the first-level conversion module comprises at least one second-level (e.g. IC1-IC3) conversion module, and the second-level conversion module comprises at least one third-level conversion module (IC2 & IC3); wherein when the second-level conversion module comprises multiple third-level conversion modules (IC2 and IC3), the multiple third-level conversion modules are coupled in parallel with each other; and wherein the first-level conversion module(s) receives (at PHSIN) a corresponding one of the N pulse distribution signals (PHSOUT from 10), the second-level conversion module receives a first phase distribution signal (PHSIN) generated based on the corresponding pulse distribution signal (from PHSOUT), and the third-level conversion module receives a second phase distribution signal (PHSIN) generated based on the first phase distribution signal.
Claim 2; the second-level conversion module in one first-level conversion module operate in the same phase, the first phase distribution signal is consistent with the corresponding pulse distribution signal (CLK or PHS), and the second-level conversion module receives the corresponding pulse distribution signal received by the corresponding first-level conversion module (e.g. IC1 sends signals to IC2).
Claim 3; e.g. IC3 receives signals from IC2.
Claims 4 and 6; controller IC3, power stage Q1, Q2; Inductor L3; average current signal ISHARE. Current sense amplifier (62). See also paragraph [0040].
Claim 7; module 60, 40, 62, etc., controlling Q1/Q2, based on error amp 60 between Ishare and sampling from 62 and 40. see also paragraph [0040].
Claim 20; the current control module is configured to generate a reference signal (output of 60 to summer and to enable amp to PWM 45) for controlling a turn-on time or a turn-off time of at least one switch (Q1/Q2) in the power stage circuit based on the error (e.g. 60) between the average current signal (Ishare) and the current sampling signal (62, 40), and to generate a PWM signal (e.g. PWM latch) as a switch control signal for controlling the at least one switch (Q1/Q2) based on an adjusted reference signal (from 45) and the second phase distribution signal (e.g. PHSIN to PWM latch).
Allowable Subject Matter
Claim 5, 8-10 and 13-19 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Claim 5; prior art fails to disclose or fairly suggest, inter alia, the control chip is configured to receive the average current signal, and to adjust the N pulse distribution signals based on the average current signal.
Claim 8; prior art fails to disclose or fairly suggest, inter alia, an output voltage feedback pin configured to receive a voltage feedback signal representing an output voltage of the multi-phase voltage converter; an average current input pin configured to receive an average current signal characterizing an average value of an inductor current of a power stage circuit generated by each of the third-level conversion modules; and N output pins configured to generate the N pulse distribution signals according to the average current signal and the voltage feedback signal.
Claim 9; prior art fails to disclose or fairly suggest, inter alia, each of the second-level conversion modules other than an output inductor and an output capacitor of a power stage circuit in the third-level conversion module is integrated into a chip, the chip comprising: a signal receiving pin configured to receive the first phase distribution signal; a power input pin configured to receive a supply voltage to supply power to the chip; an average current output pin configured to generate an average current signal characterizing an average value of an inductor current of a power stage circuit generated by each of the third-level conversion modules; and multiple output pins configured to respectively couple to an output capacitor or an output inductor of the power stage circuit in each third-level conversion module, wherein a number of the output pins is the same as a number of the third-level conversion modules.
Claim 10; prior art fails to disclose or fairly suggest, inter alia, each of the third-level conversion modules other than an output inductor and an output capacitor of a power stage circuit in the third-level conversion module is integrated into a chip, the chip comprising: a signal receiving pin configured to receive the second phase distribution signal; a power input pin configured to receive a supply voltage to supply power to the chip; an average current output pin configured to generate an average current signal characterizing an average value of an inductor current of a power stage circuit in the third-level conversion module; and multiple output pins configured to respectively couple to an output capacitor or an d) output inductor of the power stage circuit.
Claim 13; prior art fails to disclose or fairly suggest, inter alia, when the power conversion module has a fault, the first-level conversion module stops power conversion, and the power conversion module transmits fault information to the control chip through signal lines transmitting the N pulse distribution signals.
Claim 14; prior art fails to disclose or fairly suggest, inter alia, the third-level conversion module comprises an error reporting module that is configured to monitor states of the third-level conversion module; and when a fault occurs, the third-level conversion module stops power conversion, and the power conversion module modifies electrical signals on the signal lines transmitting the N pulse distribution signals along signal lines transmitting the second and first phase distribution signals according to types of the fault, in order to transmit different electrical signals to the control chip.
Claim 15; prior art fails to disclose or fairly suggest, inter alia, the control chip comprises an error detection module configured to determine in which first-level conversion module a fault occurs and which type of fault by monitoring electrical signals at signal lines transmitting the N pulse distribution signals.
Claims 16-18; prior art fails to disclose or fairly suggest, inter alia, the control chip comprises: a loop control and compensation module configured to perform loop control, compensation, and protection based on an average current signal and a voltage feedback signal; a pulse distribution signal generation module configured to generate the N pulse distribution signals according to an output signal of the loop control and compensation module; and wherein the average current signal represents an average value of an inductor current of a power stage circuit generated by each of the third-level conversion modules, and the voltage feedback signal represents an output voltage of the multi-phase voltage converter.
Claim 19; prior art fails to disclose or fairly suggest, inter alia, the current control module is configured to adjust the second phase distribution signal based on the error between the average current signal and the current sampling signal, in order to generate a switch control signal for controlling at least one switch in the power stage circuit.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. US 20180167028 Agarwal disclose a smart energy storage system; US 20100315052 Zambeti et al. disclose a PWM multiphase voltage converter; US 20060212138 Zhang discloses a POL system with an analog bus; US 20050088156 Cheung et al. disclose a multichannel interface in a multiphase converter; US 20040208029 Caruthers et al. disclose a circuit for transmitting data using a master controller and slave controller circuits.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to GARY L LAXTON whose telephone number is (571)272-2079. The examiner can normally be reached Monday-Friday, 8 am-4 pm.
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/GARY L LAXTON/Primary Examiner, Art Unit 2838 1/10/2026