DETAILED ACTION
This office action is in response to the application filed on March 27, 2024. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on February 13, 2025 is being considered by the examiner.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-12, 14-16, 18-20 are rejected under 35 U.S.C. 103 as being unpatentable over Lee (US 2019/0333929) in view of Zhang (US 2024/0164096).
With respect to Claim 1, Lee discloses (Fig. 4,12B) most aspects of the current invention including a semiconductor structure for a three-dimensional (3D) memory, comprising:
a substrate (101), having a memory device region (I/A1) and a peripheral region (III/A2) surrounding the memory device region, wherein the memory device region comprises a memory array region and a staircase region;
a circuit structure layer (LS), disposed on the substrate;
a first conductive layer (SR), disposed on the circuit structure layer;
a stacked structure (151/171G), disposed on the first conductive layer in the memory device region, comprising a plurality of second conductive layers (171G) and a plurality of insulating layers (151) alternately stacked, and having a staircase profile in the staircase region;
an oxide layer (169/269), disposed on the first conductive layer and surrounding the stacked structure;
a plurality of first dummy pillars (DPL), disposed in the peripheral, wherein each first dummy pillar in the peripheral region penetrates through the oxide layer and the first conductive layer
However, Lee does not show a first insulating wall, disposed in the oxide layer, penetrating through the first conductive layer, and surrounding the stacked structure and a plurality of first dummy pillars, disposed in the staircase region and each first dummy pillar in the staircase region penetrates through the stacked structure and the first conductive layer.
On the other hand, and in the same field of endeavor, Zhang teaches (Fig 7-9) a semiconductor structure for a three-dimensional (3D) memory, comprising a substrate (not depicted in Fig but describes), having a memory device region (101) and a peripheral region (103) surrounding the memory device region, wherein the memory device region comprises a memory array region (101) and a staircase region (102), a first conductive layer (lowermost conductive layer 12), a stacked structure (11,12), disposed on the first conductive layer in the memory device region, comprising a plurality of conductive layers (11) and a plurality of insulating layers (11) alternately stacked, and having a staircase profile in the staircase region, a first insulating wall (41; isolation structures), disposed in the oxide layer (43), penetrating through the first conductive layer, and surrounding the stacked structure and a plurality of first dummy pillars (42), disposed in the peripheral (103) and the staircase region (102) (par 57), wherein each first dummy pillar (42) in the staircase region penetrates through the stacked structure and the first conductive layer. Zhang teaches the dummy pillars are dielectric layers passing through the stacked structure to assist with support pillars arranged in the staircase region to improve the stability of the stack structure and the reliability of the semiconductor device (par 76).
Therefore, it would have been obvious to one of ordinary skill in the art, and before the effective filing date of the claimed invention to have the arrangement of a first insulating wall, disposed in the oxide layer, penetrating through the first conductive layer, and surrounding the stacked structure and a plurality of first dummy pillars, disposed in the staircase region and each first dummy pillar in the staircase region penetrates through the stacked structure and the first conductive layer and a plurality of first dummy pillars, disposed in the staircase region and each first dummy pillar in the staircase region penetrates through the stacked structure and the first conductive layer in the device of Lee, as taught by Zhang, because the dummy pillars are dielectric layers passing through the stacked structure to assist with support pillars arranged in the staircase region to improve the stability of the stack structure and the reliability of the semiconductor device.
With respect to Claim 2, Zhang teaches (Fig 7-9) further comprising a plurality of supporting pillars (52), disposed in the staircase region, and penetrating through the stacked structure and the first conductive layer.
With respect to Claim 3, Zhang teaches (Fig 7-9) further comprising a plurality of second insulating walls (41; isolation structures) parallel to each other, disposed in the stacked structure to divide the stacked structure into a plurality of blocks arranged parallel to each other.
With respect to Claim 4, Zhang teaches (Fig 7-9) wherein in each of the blocks, the first dummy pillars are located at a first side of the memory array region, and the supporting pillars are located at a second side opposite to the first side of the memory array region.
With respect to Claim 5, Zhang teaches (Fig 7-9) wherein the first dummy pillars in each of the blocks are adjacent to the supporting pillars in an adjacent block, and the supporting pillars in each of the blocks are adjacent to the first dummy pillars in an adjacent block.
With respect to Claim 6, Lee discloses (Fig. 4,12B) further comprising a plurality of vertical channel structures (CP), disposed in the memory array region and penetrating through the stacked structure and the first conductive layer. Additionally, Zhang teaches (Fig 7-8) further comprising a plurality of vertical channel structures (54), disposed in the memory array region (101) and penetrating through the stacked structure and the first conductive layer.
With respect to Claim 7, Zhang teaches (Fig 7-9) wherein the first insulating wall (41; isolation structures) is located in the memory device region and adjacent to a boundary between the memory device region and the peripheral region, and spacing a distance from a lowermost second conductive layer in the stacked structure (see Fig 8-9)
With respect to Claim 8, Lee discloses (Fig. 4-12B) most aspects of the current invention including a manufacturing method of a semiconductor structure for a three-dimensional (3D) memory, comprising:
providing a substrate (101), wherein the substrate has a memory device region (I/A1) and a peripheral region (III/A2) surrounding the memory device region, and the memory device region comprises a memory array region and a staircase region;
forming a circuit structure layer (LS) on the substrate;
forming a first conductive layer (SR) on the circuit structure layer
forming a stacked structure (151/171G) on the first conductive layer in the memory device region, wherein the stacked structure comprises a plurality of second conductive layers (171G) and a plurality of insulating layers (151) alternately stacked and has a staircase profile in the staircase region;
forming an oxide layer (169/269) on the first conductive layer, wherein the oxide layer surrounds the stacked structure
forming a plurality of first dummy pillars (DPL), disposed in the peripheral, wherein each first dummy pillar in the peripheral region penetrates through the oxide layer and the first conductive layer
However, Lee does not show method steps of forming a first insulating wall in the oxide layer, wherein the first insulating wall penetrates through the first conductive layer and surrounds the stacked structure and forming a plurality of first dummy pillars, disposed in the staircase region and each first dummy pillar in the staircase region penetrates through the stacked structure and the first conductive layer.
On the other hand, and in the same field of endeavor, Zhang teaches (Fig 7-9) a manufacturing method of a semiconductor structure for a three-dimensional (3D) memory, comprising providing a substrate (not depicted in Fig but describes), having a memory device region (101) and a peripheral region (103) surrounding the memory device region, wherein the memory device region comprises a memory array region (101) and a staircase region (102), a first conductive layer (lowermost conductive layer 12), a stacked structure (11,12), disposed on the first conductive layer in the memory device region, comprising a plurality of conductive layers (11) and a plurality of insulating layers (11) alternately stacked, and having a staircase profile in the staircase region, forming a first insulating wall (41; isolation structures) in the oxide layer (43), wherein the first insulating wall penetrates through the first conductive layer surrounds the stacked structure, and forming a plurality of first dummy pillars (42), disposed in the peripheral (103) and the staircase region (102) (par 57), wherein each first dummy pillar (42) in the staircase region penetrates through the stacked structure and the first conductive layer. Zhang teaches the dummy pillars are dielectric layers passing through the stacked structure to assist with support pillars arranged in the staircase region to improve the stability of the stack structure and the reliability of the semiconductor device (par 76).
Therefore, it would have been obvious to one of ordinary skill in the art, and before the effective filing date of the claimed invention to have the arrangement of forming a first insulating wall in the oxide layer, wherein the first insulating wall penetrates through the first conductive layer and surrounds the stacked structure and forming a plurality of first dummy pillars, disposed in the staircase region and each first dummy pillar in the staircase region penetrates through the stacked structure and the first conductive layer in the device of Lee, as taught by Zhang, because the dummy pillars are dielectric layers passing through the stacked structure to assist with support pillars arranged in the staircase region to improve the stability of the stack structure and the reliability of the semiconductor device.
With respect to Claim 9, Lee discloses (Fig. 4-12b) wherein a forming method of the stacked structure and the oxide layer comprises: forming a first initial stacked structure on the first conductive layer, wherein the first initial stacked structure comprises the plurality of insulating layers (151) and a plurality of sacrificial layers (153) alternately stacked; removing a part of the insulating layers and a part of the sacrificial layers to expose the first conductive layer in the peripheral region and to form a second initial stacked structure in the memory device region, wherein the second initial stacked structure has the staircase profile in the staircase region; forming the oxide layer (169/269) on the first conductive layer; and replacing the plurality of sacrificial layers with the plurality of second conductive layers (171G).
With respect to Claim 10, Lee discloses (Fig. 4-12b) wherein after forming the oxide layer and before replacing the plurality of sacrificial layers with the plurality of second conductive layers, further comprising: forming a plurality of vertical channel structures (CP) in the memory array region, wherein each vertical channel structure penetrates through the second initial stacked structure and the first conductive layer.
With respect to Claim 11, Lee discloses (Fig. 4-12b) wherein after forming the plurality of vertical channel structures and before replacing the plurality of sacrificial layers with the plurality of second conductive layers, further comprising: forming the plurality of first dummy pillars (DPL) in the peripheral region, wherein each first dummy pillar in the peripheral region penetrates through the first conductive layer. However, Lee does not show method steps of further comprising: forming the plurality of first dummy pillars in the staircase region, and each first dummy pillar in the staircase region penetrates the oxide layer and the second initial stacked structure and the first conductive layer.
On the other hand, and in the same field of endeavor, Zhang teaches (Fig 7-9) a manufacturing method of a semiconductor structure for a three-dimensional (3D) memory, comprising providing a substrate (not depicted in Fig but describes), having a memory device region (101) and a peripheral region (103) surrounding the memory device region, wherein the memory device region comprises a memory array region (101) and a staircase region (102), a first conductive layer (lowermost conductive layer 12), a stacked structure (11,12), disposed on the first conductive layer in the memory device region, comprising a plurality of conductive layers (11) and a plurality of insulating layers (11) alternately stacked, and having a staircase profile in the staircase region, forming a plurality of first dummy pillars (42), disposed in the peripheral (103) and the staircase region (102) (par 57), wherein each first dummy pillar (42) in the staircase region penetrates through the stacked structure and the first conductive layer. Zhang teaches the dummy pillars are dielectric layers passing through the stacked structure to assist with support pillars arranged in the staircase region to improve the stability of the stack structure and the reliability of the semiconductor device (par 76).
Therefore, it would have been obvious to one of ordinary skill in the art, and before the effective filing date of the claimed invention to have the arrangement of wherein after forming the plurality of vertical channel structures and before replacing the plurality of sacrificial layers with the plurality of second conductive layers, further comprising forming the plurality of first dummy pillars in the peripheral region and the staircase region, and each first dummy pillar in the staircase region penetrates the oxide layer and the second initial stacked structure and the first conductive layer in the device of Lee, as taught by Zhang, because the dummy pillars are dielectric layers passing through the stacked structure to assist with support pillars arranged in the staircase region to improve the stability of the stack structure and the reliability of the semiconductor device.
With respect to Claim 12, Zhang teaches (Fig 7-9) wherein when forming the plurality of vertical channel structures, further comprising: forming a plurality of supporting pillars (52) in the staircase region, wherein each supporting pillar penetrates through the second initial stacked structure and the first conductive layer.
With respect to Claim 14, Lee discloses (Fig. 4-12B) wherein after forming the oxide layer and before replacing the plurality of sacrificial layers with the plurality of second conductive layers, further comprising forming the plurality of first dummy pillars (DPL) in the peripheral region. However, Lee does not show method steps of further comprising: forming the plurality of first dummy pillars in the staircase region, and each first dummy pillar in the staircase region penetrates the second initial stacked structure and the first conductive layer.
On the other hand, and in the same field of endeavor, Zhang teaches (Fig 7-9) a manufacturing method of a semiconductor structure for a three-dimensional (3D) memory, comprising providing a substrate (not depicted in Fig but describes), having a memory device region (101) and a peripheral region (103) surrounding the memory device region, wherein the memory device region comprises a memory array region (101) and a staircase region (102), a first conductive layer (lowermost conductive layer 12), a stacked structure (11,12), disposed on the first conductive layer in the memory device region, comprising a plurality of conductive layers (11) and a plurality of insulating layers (11) alternately stacked, and having a staircase profile in the staircase region, forming a plurality of first dummy pillars (42), disposed in the peripheral (103) and the staircase region (102) (par 57), wherein each first dummy pillar (42) in the staircase region penetrates the second initial stacked structure and the first conductive layer. Zhang teaches the dummy pillars are dielectric layers passing through the stacked structure to assist with support pillars arranged in the staircase region to improve the stability of the stack structure and the reliability of the semiconductor device (par 76).
Therefore, it would have been obvious to one of ordinary skill in the art, and before the effective filing date of the claimed invention to have the arrangement of wherein after forming the oxide layer and before replacing the plurality of sacrificial layers with the plurality of second conductive layers, further comprising forming the plurality of first dummy pillars in the staircase region, and each first dummy pillar in the staircase region penetrates the second initial stacked structure and the first conductive layer in the device of Lee, as taught by Zhang, because the dummy pillars are dielectric layers passing through the stacked structure to assist with support pillars arranged in the staircase region to improve the stability of the stack structure and the reliability of the semiconductor device.
With respect to Claim 15, Lee discloses (Fig. 4-12B) wherein after forming the plurality of first dummy pillars and before replacing the plurality of sacrificial layers with the plurality of second conductive layers, further comprising: forming a plurality of vertical channel structures (CP) in the memory array region, wherein each vertical channel structure penetrates through the second initial stacked structure and the first conductive layer.
With respect to Claim 16, Zhang teaches (Fig 7-9) wherein when forming the plurality of vertical channel structures (54), further comprising: forming a plurality of supporting pillars (52) in the staircase region, wherein each supporting pillar penetrates through the second initial stacked structure and the first conductive layer.
With respect to Claim 18, Lee discloses (Fig. 4,6a-9d) wherein before forming the plurality of first dummy pillars, further comprising: forming a plurality of vertical channel structures (CP) in the memory array region, wherein each vertical channel structure penetrates through the second initial stacked structure and the first conductive layer.
With respect to Claim 19, Zhang teaches (Fig 7-9) wherein when forming the plurality of vertical channel structures (54), further comprising: forming a plurality of supporting pillars (52) in the staircase region, wherein each supporting pillar penetrates through the second initial stacked structure and the first conductive layer.
With respect to Claim 20, Zhang teaches (Fig 7-9) wherein the first insulating wall (41; isolation structures) is located in the memory device region and adjacent to a boundary between the memory device region and the peripheral region, and spacing a distance from a lowermost second conductive layer in the stacked structure
Claim Objections
Claims 13 and 17 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
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/Q.A.B/ Examiner, Art Unit 2814
/WAEL M FAHMY/Supervisory Patent Examiner, Art Unit 2814
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