DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Foreign Priority
Receipt is acknowledged of certified copies of papers submitted under 35 U.S.C. 119(a)-(d), which papers have been placed of record in the file, as electronically retrieved 05/07/2024.
Information Disclosure Statement
The information disclosure statements (IDS) submitted on 03/27/2024, 12/03/2024, 01/14/2025, 08/15/2025 and 04/23/2026 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statements are being considered by the examiner.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 1-2 and 4-11 are rejected under 35 U.S.C. 103 as being unpatentable over Koezuka et al. (PG Pub 2015/0228803; hereinafter Koezuka) and Miyamoto (PG Pub 2020/0185527).
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Regarding claim 1, refer to the Examiner’s modified mark-up of Fig. 3a provided above, Koezuka teaches a semiconductor device 100i comprising:
a first insulating layer 104;
a metal oxide layer 105 mainly composed of aluminum on the first insulating layer (see para [0097]);
an oxide semiconductor layer 106 having a polycrystalline structure (a CAAC‑OS structure) on the metal oxide layer (para [0099]; see Fig. 3a);
a gate insulating layer 117 on the oxide semiconductor layer (see Fig. 3a);
a gate electrode 119 on the gate insulating layer (see Fig. 3a); and
a second insulating layer 126 on the gate electrode see Fig. 3a),
wherein the metal oxide layer and the oxide semiconductor layer are both patterned (see Fig. 3a), and the oxide semiconductor layer has a first region 106a in contact with the gate insulating layer and a second region 106b/c continuous with the first region in a first direction (horizontal) and in contact with the gate insulating layer and the second insulating layer (see Fig. 3).
para [0097] The oxide semiconductor films 105, 106, and 108 are each formed using a metal oxide containing at least In, and typically formed using an In--Ga oxide, an In-M-Zn oxide (M is Mg, Al, Ti, Ga, Y, Zr, La, Ce, Nd, or Hf), or the like. The oxide semiconductor film 105 has a higher indium content than the oxide semiconductor film 106; therefore, a buried channel can be formed in the transistor 100g. Thus, variations in the threshold voltage of the transistor 100g can be reduced and channel resistance can be lowered.
Although, Koezuka teaches the oxide semiconductor layer 106 having a crystalline oxide semiconductor structure, Koezuka does not explicitly teach a crystalline oxide semiconductor is a polycrystalline structure.
In the same field of endeavor, Miyamoto teaches examples of crystalline oxide semiconductor include a polycrystalline oxide semiconductor, a microcrystalline oxide semiconductor, and a crystalline oxide semiconductor (see para [0049]).
In light of such teachings, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have the crystalline oxide semiconductor layer of Koezuka comprise a polycrystalline oxide semiconductor, as taught by Miyamoto, for the purpose of choosing a suitable and well-recognized oxide semiconductor.
Regarding claim 2, refer to the figure provided above, in the combination of Koezuka and Miyamoto, Koezuka teaches the second insulating layer 126 contacts the gate electrode 119, the gate insulating layer 117 and the oxide semiconductor layer 106 (see Fig. 3a).
Regarding claim 4, refer to the figure provided above, in the combination of Koezuka and Miyamoto, Koezuka teaches the first region 106a is a channel region of a transistor (see Fig. 3a), and the second region 106b/c is a region of lower resistance than the channel region (para [0086]).
Regarding claim 5, refer to the figure provided above, in the combination of Koezuka and Miyamoto, Koezuka teaches the metal oxide layer 105 and the oxide semiconductor layer 106 have the same pattern shape (see Fig. 3a).
Regarding claim 6, refer to the figure provided above, in the combination of Koezuka and Miyamoto, Koezuka teaches the gate insulating layer 117 and the gate electrode 119 have the same pattern shape (see Fig. 3a).
Regarding claim 7, refer to the figure provided above, in the combination of Koezuka and Miyamoto, Koezuka teaches the oxide semiconductor layer 106 contains at least two or more metallic elements including indium, and a ratio of indium to the at least two or more metallic elements is 50% or more (para [0097]).
Regarding claim 8, refer to the figure provided above, in the combination of Koezuka and Miyamoto, Koezuka teaches a width in the first direction (horizontal) of a portion of the second region 106b/c in contact with the gate insulating layer 117 is 1 μm or less (para [0096]).
Regarding claim 9, refer to the figure provided above, in the combination of Koezuka and Miyamoto, Koezuka teaches a width of the gate electrode 119 in the first direction (horizontal) is 4 μm or less (as inferred knowing the gate width is less than the width of the second region…see claim 8).
Regarding claim 10, refer to the figure provided above, in the combination of Koezuka and Miyamoto, Koezuka teaches a width of the gate electrode 119 in the first direction (horizontal) is 1 μm or more and greater than twice a width in the first direction of the portion of the second region in contact with the gate insulating layer (see Fig. 3a and claim 8).
Regarding claim 11, refer to the figure provided above, in the combination of Koezuka and Miyamoto, Koezuka teaches a display device comprising a plurality of pixels, each of the plurality of pixels comprising the semiconductor device according to claim 1 (see para [0102] and claim 1).
2. Claim(s) 3 is rejected under 35 U.S.C. 103 as being unpatentable over Koezuka and Miyamoto and as applied to claim 1 above, and further in view of Kusunoki et al. (PG Pub 2021/0118855; hereinafter Kusunoki).
Regarding claim 3, refer to the figure provided above, in the combination of Koezuka and Miyamoto, Koezuka teaches the second insulating layer 126. Koezuka does not teach the second insulating layer has a stacked structure including a silicon nitride layer and a silicon oxide layer.
In the same field of endeavor, Kusunoki teaches an insulating layer 770 has a stacked structure including a silicon nitride layer and a silicon oxide layer (para [0168]).
In light of such teachings, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have the insulating layer of Koezuka compirse a stacked structure of silicon nitride and silicon oxide layers, as taught by Kusunoki, to “functions as a protective layer of the transistor (para [0168]).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Christina A Sylvia whose telephone number is (571)272-7474. The examiner can normally be reached on 8am-4pm (M-F).
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Marlon Fletcher can be reached on 571-272-2063. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/CHRISTINA A SYLVIA/Examiner, Art Unit 2817
/MARLON T FLETCHER/Supervisory Primary Examiner, Art Unit 2817
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